Switching voltage regulator operating without a discontinuous mode

[0001] 1. Field of the Invention

[0002] The present invention relates to a switching voltage regulator and, more particularly, to a switching voltage regulator operating without a discontinuous mode for enhancing power delivery efficiency.

[0003] 2. Description of the Related Art

[0004] Switching voltage regulators supply a required output current at a regulated output voltage to a load. Through controlling duty ratios of power transistors, the switching voltage regulator converts an unregulated input voltage source to a stable, desired output voltage. FIG. 1 is a circuit block diagram showing a conventional synchronous switching buck regulator with a current feedback control. As shown in FIG. 1, a high-side switch HS and a low-side switch LS are series-connected between an input voltage source V_in and a ground potential. An inductor L has one end connected to a common node CN between the high-side switch HS and the low-side switch LS, and the other end serving as an output terminal for supplying an output voltage V_out to a load R_L. The output terminal may be additionally provided with an output capacitor C_o for filtering the output voltage V_out. The high-side switch HS and the low-side switch LS are controlled by a high-side drive signal HD and a low-side drive signal LD generated from the switching logic circuit 10, respectively. With respect to the synchronous switching voltage regulator, the high-side switch HS and the low-side switch LS are operated out of phase. An oscillating circuit 11 outputs a pulse signal PU having a fixed frequency to the switching logic circuit 10. In the beginning of each switch cycle, the switching logic circuit 10 turns on the high-side switch HS and turns off the low-side switch LS in response to the pulse signal PU. As a result, the input voltage source V_in supplies energy to the inductor L for linearly increasing the current I_L. Once the inductor current I_L reaches a upper limit set by a slope-compensated error signal V_err2 between a voltage feedback signal V_vfb and a reference voltage signal V_ref, a comparator 12 is triggered to output HIGH instead of LOW. In response to the trigger event of the comparator 12, the switching logic circuit 10 turns off the high-side switch HS and turns on the low-side switch LS. As a result, the inductor current I_L linearly decreases since the energy stored in the inductor L delivers to the load R_L.

[0005] FIG. 2 is a timing chart showing waveforms of the inductor current I_L of the synchronous switching buck regulator of FIG. 1. As shown in FIG. 2, a curve 21 indicates a waveform of the inductor current I_L with respect to a continuous-mode operation of the switching voltage regulator. Within each switch period T_S, the inductor current I_L changes like a triangular wave having a linearly increasing portion corresponding to an operating state that the high-side switch HS is turned on for allowing the input voltage source V_in to supply energy to the inductor L and a linearly decreasing portion corresponding to another operating state that the high-side switch HS is turned off for allowing the energy stored in the inductor L to deliver to the load R_L.

[0006] A curve 22 indicates a waveform of the inductor current I_L with respect to a discontinuous-mode operation of the switching voltage regulator. At a time t1, a switch cycle begins and therefore the high-side switch HS is turned on for linearly increasing the inductor current I_L. At a time t2, the inductor current I_L reaches a upper limit I_peak2 set by the slope-compensated error signal V_err2, causing the high-side switch HS to be turned off and the low-side switch LS to be turned on. Consequently, the inductor current I_L starts to linearly decrease. At a time t3, the inductor current I_L has already decreased to zero although the next switch cycle will not start until a time t4. In this case, the inductor current I_L is subjected to polarity reversal between times t3 and t4, i.e. the flowing direction of the inductor current I_L makes a change of 180 degrees. For this reason, the conventional synchronous switching buck regulator must be additionally provided with a current reversal detecting circuit 17, as shown in FIG. 1, for triggering the switching logic circuit 10 to turn off the low-side switch LS immediately after the inductor current I_L decreases to zero. Thereby, the inductor current I_L is prevented from reversing polarity to reduce the power delivery efficiency.

[0007] Even if the current reversal detecting circuit 17 is provided or the circuit topology is replaced with a non-synchronous switching type which uses a combination of the power transistor and a flywheel diode as the switching circuit, the inductor current I_L is effectively prevented from reversing polarity. However, as shown in FIG. 2, the inductor current I_L remains zero between the times t3 and t4 with respect to the discontinuous-mode operation. In this case, the output voltage V_out inevitably rings or fluctuates up and down to cause unfavorable high-frequency noise.

[0008] In view of the above-mentioned problems, an object of the present invention is to provide a switching voltage regulator capable of being adapted to operate with the continuous mode, thereby avoiding the drawbacks caused by the discontinuous mode.

[0009] It is observed that if half the peak current flowing through the inductor is just equal to the average current flowing through the inductor, the switching voltage regulator operates at a threshold operating state between the continuous mode and the discontinuous mode. At such a threshold operating state, the peak current flowing through the inductor may be referred to as a threshold peak current of the continuous mode. Therefore, the switching voltage regulator according to the present invention is provided with a threshold peak current setting circuit for generating a threshold signal representative of the threshold peak current of the continuous mode. When the peak current flowing through the inductor is higher than the threshold peak current, it is unnecessary to adjust the inductor current since the continuous mode has been established. However, when the peak current flowing through the inductor is detected to be lower than the threshold peak current, the inductor current needs to be raised such that the peak current is substantially equal to the threshold peak current, thereby ensuring that the switching voltage regulator operates with the continuous mode.

[0010] According to one aspect of the present invention, a switching voltage regulator is provided to include a switching circuit, a control circuit, and a setting circuit. The switching circuit operates with a first operating state and a second operating state. During the first operating state, the switching circuit allows a switching current to linearly increase. During the second operating state, the switching circuit allows the switching current to linearly decrease. The control circuit is coupled to the switching circuit for controlling the switching circuit to operate with the first operating state or the second operating state. The setting circuit generates a threshold signal such that in response to the threshold signal the control circuit ensures that the switching current linearly increases to become higher than or equal to a current value set by the threshold signal during the first operating state. Thereby, the switching current is prevented from linearly decreasing to reverse polarity during the second operating state.

[0011] According to another aspect of the present invention, a method of controlling a switching voltage regulator is provided to include the following steps. A switching circuit is controlled to operate with a first operating state for allowing a switching current to linearly increase. The switching circuit is controlled to operate with a second operating state for allowing the switching current to linearly decrease. In the step of controlling the switching circuit to operate with the first operating state, the switching current is ensured to become higher than or equal to a threshold current. Thereby, the switching current is prevented from linearly decreasing to reverse polarity in the step of controlling the switching circuit to operate with the second operating state.

[0012] According to still another aspect of the present invention, a threshold current setting circuit is provided to include a first circuit, a second circuit, and a third circuit. The first circuit generates a first current signal in response to a voltage signal. The first current signal is proportional to the voltage signal. The second circuit generates a second current signal in response to the first current signal and a periodic signal. The second current signal is representative of a periodically-varying current. The third circuit generates a third current signal representative of a predetermined current value. A combination of the first to the third current signals is used to approximately simulate a threshold current signal.

[0021] The preferred embodiments according to the present invention will be described in detail with reference to the drawings.

[0022] It is observed from FIG. 2 that the relationship between the peak current and the average current flowing through the inductor presents an essential difference between the continuous and discontinuous modes. More specifically, in the continuous mode indicated by the curve 21, the average current I_ave1 flowing through the inductor L is higher than half the peak current I_peak1 flowing through the inductor L. However, in the discontinuous mode indicated by the curve 22, the average current I_ave2 flowing through the inductor L is lower than half the peak current I_peak2 flowing through the inductor L because during one part of each switch period T_S the inductor current I_L is substantially equal to zero given that a current reversal preventing device is provided. Therefore, in order to avoid the discontinuous mode, half the peak current flowing through the inductor must be made lower than or equal to the average current flowing through the inductor. As shown in FIG. 3, a curve 30 indicates a waveform of the inductor current I_L that reduces to zero immediately before the end of each switch cycle with respect to the threshold operating state. Through analytical calculation, the threshold peak current I_peak—TH is found to be determined cooperatively by the duty ratio D, the switch period T_S, the input voltage V_in, and the inductance L, as expressed in the following equation (1):

[0023] $\begin{array}{cc}{I}_{\mathrm{peak\_TH}}=\left(\frac{T_s}{L}\right)·D·\left(1-D\right)·V_{in}& \left(1\right)\end{array}$

[0024] Since the threshold peak current I_peak—TH indicates the minimum allowable peak current of the continuous mode, the voltage regulator is effectively prevented from operating with the discontinuous mode if the peak current flowing through the inductor is made higher than or equal to the threshold peak current I_peak—TH.

[0025] FIG. 4 is a circuit block diagram showing a synchronous switching buck regulator according to the present invention. As shown in FIG. 4, a high-side switch HS and a low-side switch LS are series-connected between an input voltage source V_in and a ground potential. An inductor L has one end connected to the common node CN between the high-side switch HS and the low-side switch LS, and the other end serving as an output terminal for supplying an output voltage V_out to a load R_L. The output terminal may be additionally provided with an output capacitor C_o for filtering the output voltage V_out. The high-side switch HS and the low-side switch LS are controlled by a high-side drive signal HD and a low-side drive signal LD generated from a switching logic circuit 40, respectively. The switching logic circuit 40 has an SR latch 41 for supplying the high-side drive signal HD and the low-side drive signal LD from the inverting output terminal Q. In the embodiment shown in FIG. 4, the high-side switch HS and the low-side switch LS are implemented by signals with the same phase because the high-side switch HS is implemented by a PMOS transistor and the low-side switch LS is implemented by an NMOS transistor.

[0026] The SR latch 41 has a set terminal S connected to an output terminal of an inverter 42. The inverter 42 has an input terminal connected to an oscillating circuit 11 for receiving a pulse signal PU. The SR latch 41 has a reset terminal R connected to an output terminal of an NAND gate 43. The NAND gate 43 has a first input terminal connected to an output terminal of a comparator 12 for receiving a first comparison result signal CR1. The comparator 12 has an inverting input terminal connected to an output terminal of a slope compensation circuit 13. The slope compensation circuit 13 has two input terminals connected to the oscillating circuit 11 and an output terminal of an error amplifier 14, respectively, for generating a slope-compensated error signal V_err2 in accordance with a ramp signal RA output from the oscillating circuit 111 and the error signal V_err1, between a voltage feedback signal V_vfb and a reference voltage signal V_ref, output from the error amplifier 14. The error amplifier 14 has an inverting input terminal connected to an output terminal of a voltage feedback circuit 15 for receiving the voltage feedback signal V_vfb representative of the output voltage V_out of the switching voltage regulator. The error amplifier 14 has a non-inverting input terminal for receiving the reference voltage signal V_ref. The comparator 12 has a non-inverting input terminal connected to a current feedback circuit 16 for receiving a current feedback signal V_ifb representative of the inductor current I_L.

[0027] The NAND gate 43 has a second input terminal connected to an output terminal of a comparator 44 for receiving a second comparison result signal CR2. The comparator 44 has an inverting input terminal connected to a threshold peak current setting circuit 45 for receiving a threshold signal V_peak—TH. The comparator 44 has a non-inverting input terminal connected to the current feedback circuit 16 for receiving the current feedback signal V_ifb. The threshold signal V_peak—TH generated by the threshold peak current setting circuit 45 is representative of the threshold peak current I_peak—TH calculated in accordance with the equation (1) described above.

[0028] Hereinafter is described in detail the operation of the synchronous switching buck regulator according to the present invention with reference to FIG. 4. The pulse signal PU having a period T_S generated by the oscillating circuit 11 is supplied through the inverter 42 to the set terminal S of the SR latch 41. Since the SR latch 41 is a negative-going trigger circuit, the rising edge of the pulse signal PU after inverted triggers the SR latch 41 such that the inverting output terminal Q supplies the high-side drive signal HD and the low-side drive signal LD with the LOW level for staring a switch cycle. The high-side drive signal HD with the LOW level turns on the high-side switch HS while the low-side drive signal LD with the LOW level turns off the low-side switch LS. As a result the input voltage source V_in supplies energy to the inductor L for linearly increasing the inductor current I_L. The current feedback circuit 16 detects the inductor current I_L and then generates the current feedback signal V_ifb representative of the inductor current I_L. The current feedback signal V_ifb is supplied to the comparators 12 and 44 for being compared respectively with the slope-compensated error signal V_err2 and the threshold signal V_peak—TH.

[0029] With the function of the comparator 12, the first comparison result signal CR1 immediately changes from the LOW level to the HIGH level once the current feedback signal V_ifb linearly increases in excess of the slope-compensated error signal V_err2. On the other hand, with the function of the comparator 44, the second comparison result signal CR2 immediately changes from the LOW level to the HIGH level once the current feedback signal V_ifb linearly increases in excess of the threshold signal V_peak—TH. The first and second comparison result signals CR1 and CR2 are coupled through the NAND gate 43 for controlling the reset terminal R of the SR latch 41. Therefore, the reset terminal R is triggered (i.e. the output signal of the NAND gate 43 changes from the HIGH level to the LOW level) under a condition that both of the first and second comparison result signals CR1 and CR2 must have the HIGH level. In other words, when the current feedback signal V_ifb is below the threshold signal V_peak—TH, the output signal of the NAND gate 43 is kept HIGH and incapable of triggering the reset terminal R due to the LOW level of the second comparison result signal CR2, even if the current feedback signal V_ifb has already linearly increased in excess of the slope-compensated error signal V_err2 to trigger the first comparison result signal CR1 from the LOW level to the HIGH level. As a result, the high-side switch HS stays conductive for allowing the current feedback signal V_ifb to linearly increase in excess of the threshold signal V_peak—TH.

[0030] When the reset terminal R is triggered the inverting output terminal Q of the SR latch 41 supplies the high-side drive signal HD and low-side drive signal LD with the HIGH level. The high-side drive signal HD with the HIGH level turns off the high-side switch HS while the low-side drive signal LD with the HIGH level turns on the low-side switch LS. As a result, the energy stored in the inductor L delivers to the load R_L for linearly decreasing the inductor current I_L. Since the peak current flowing th rough the inductor L must become higher than or equal to the threshold peak current I_peak—TH for triggering the reset terminal R, the inductor current I_L are effectively prevented from decreasing to reverse polarity before the pulse signal PU triggers the set terminal S again to start the next switch cycle. Therefore, the synchronous switching buck regulator according to the present invention operates without a discontinuous mode and avoids the problems caused by the inductor current reversal and/or the high-frequency fluctuation of the output voltage.

[0031] In the embodiment shown in FIG. 4, since the comparators 12 and 44 are designed as the voltage-type comparators for receiving the voltage-type input signals and supplying the voltage-type output signals, the current feedback circuit 16 and the threshold peak current setting circuit 45 are designed to output the voltage-type signals V_ifb and V_peak—TH for indirectly corresponding to the physical quantity I_L and I_peak—TH, instead of directly outputting current-type signals. It should be noted that the present invention is applicable to a case where the current feedback circuit 16 and the threshold peak current setting circuit 45 are designed to directly output the current-type signals. For example, current-to-voltage converters are additionally provided to the output terminals of the current feedback circuit 16 and the threshold peak current setting circuit 45 for converting the current-type signals to the voltage-type signals. Alternatively, voltage-to-current converter is employed to convert the voltage-type error signal V_err2 to the current-type signal while the comparators 12 and 44 are designed as the current-type comparator circuits. In this case, the current feedback circuit 16 and the threshold peak current setting circuit 45 may be designed to directly output the current-type signals.

[0032] As clearly seen from the equation (1), the threshold signal V_peak—TH is a parabolic function of the duty ratio. Except for the establishment of the steady state, the duty ratio varies in accordance with the real-time operation of the switching voltage regulator. Even in the steady state the duty ratio may need to increase for maintaining the output voltage V_out at the desired value due to a drop of the input voltage source V_in. Therefore, the threshold peak current setting circuit 45 according to the present invention must adjust the threshold signal V_peak—TH in accordance with the real-time operation of the switching voltage regulator, rather than generates a fixed signal to serve as the threshold signal V_peak—TH.

[0033] FIG. 5 is a detailed circuit diagram showing a first example of a threshold peak current setting circuit 45-1 according to the present invention. As shown in FIG. 5, in response to the unregulated input voltage Vin and the ramp signal RA having the period T_S, the threshold peak current setting circuit 45-1 generates the threshold signal V_peak—TH representative of the threshold peak current I_peak—TH calculated in accordance with the equation (1) described above. More specifically, the input voltage V_in is linearly amplified through operating amplifiers OP1 and OP2 in sequence to form the threshold signal V_peak—TH, which may be expressed as the following equation (2):

[0034] $\begin{array}{cc}{V}_{\mathrm{peak\_TH}}=\left(\frac{R_{v1}}{R_{c1}}\right)·\left(\frac{R_{v2}}{R_{c2}}\right)·V_{in}& \left(2\right)\end{array}$

[0035] wherein R_c1 is a constant resistance connected between the input voltage V_in and an inverting input terminal of the operating amplifier OP1, R_v1 is a linearly variable resistance connected between the inverting input terminal and an output terminal of the operating amplifier OP1, R_c2 is a constant resistance connected between the input voltage V_in and an inverting input terminal of the operating amplifier OP2, and R_v2 is a linearly variable resistance connected between the inverting input terminal and an output terminal of the operating amplifier OP2.

[0036] The linearly variable resistance R_v1 is designed as a time-argument function that may be expressed as the following equation (3):
R_v1(t)=R_v1,t=0·D(t)  (3)

[0037] wherein R_v1,t=0 is an initial value of the linearly variable resistance R_v1 in the beginning of the switch cycle and D(t) is a time-argument function whose value linearly increases from zero to one over the period T_S. The linearly variable resistance R_v2 is designed as another time-argument function that may be expressed as the following equation (4):
R_v2(t)=R_v2,t=0·(1−D)(t)  (4)

[0038] wherein R_v2,t=0 is an initial value of the linearly variable resistance R_v2 in the beginning of the switch cycle and (1−D)(t) is a time-argument function whose value linearly decreases from one to zero over the period T_S. The oscillating circuit 11 shown in FIG. 4 generates the ramp signal RA having amplitude that linearly increases over the period T_S. Consequently, the linearly variable resistance R_v1 may be modulated in response to the ramp signal RA generated from the oscillating circuit 11. On the other hand, the ramp signal RA becomes an inverted waveform through an inverter INV to cause its amplitude to linearly decrease over the period T_s. Consequently, the linearly variable resistance R_v2 may be modulated in response to the inverted ramp signal.

[0039] By substituting the equations (3) and (4) for the equation (2), the threshold signal V_peak—TH may be expressed as the following equation (5):

[0040] $\begin{array}{cc}{V}_{\mathrm{peak\_TH}}\left(t\right)=\left(\frac{R_{v1,t=0}}{R_{c1}}\right)·\left(\frac{R_{v2,t=0}}{R_{c2}}\right)·D\left(t\right)·\left(1-D\right)\left(t\right)·V_{in}& \left(5\right)\end{array}$

[0041] Comparing the equations (1) and (5), it is found that the proportional coefficient made up of the resistances must be designed to satisfy the following condition (6):

[0042] $\begin{array}{cc}\left(\frac{R_{v1,t=0}}{R_{c1}}\right)·\left(\frac{R_{v2,t=0}}{R_{c2}}\right)=\frac{T_s}{L}& \left(6\right)\end{array}$

[0043] During each switch cycle, the threshold signal V_peak—TH corresponding to this very moment when the current feedback signal V_ifb reaches the slope-compensated error signal V_err2 is precisely generated from the threshold peak current setting circuit 45-1. As a result, the comparator 44 effectively determines whether the current feedback signal V_ifb reaches the threshold signal V_peak—TH or not, thereby avoiding operating the switching voltage regulator with the discontinuous mode.

[0044] FIG. 6 is a detailed circuit diagram showing a second example of a threshold peak current setting circuit 45-2 according to the present invention. As shown in FIG. 6, the input voltage V_in determines a current I_a through a linear current regulator constructed of an operating amplifier OP_a, an NMOS transistor N1, and a resistance R_a, which may be expressed as the following equation (7):

[0045] $\begin{array}{cc}{I}_a=\left(\frac{V_{in}}{R_a}\right)& \left(7\right)\end{array}$

[0046] In other words, the current I_a is proportional to the input voltage V_in. PMOS transistors P1 to P4 form a current mirror with the multiple output stages P2 to P4 for supplying the current I_a. The transistor P2 supplies the current I_a to a differential pair constructed of PMOS transistors P5 and P6. The transistor P3 supplies the current I_a to another differential pair constructed of PMOS transistors P7 and P8. The transistor P5 has a gate electrode controlled by a low-boundary reference voltage V_bl while the transistor P8 has a gate electrode controlled by a high-boundary reference voltage V_bh. The transistors P6 and P7 have their gate electrodes connected together for receiving the ramp signal RA generated from the oscillating circuit 11.

[0047] The current I_a supplied from the transistor P3 is distributed to the transistor P5 in accordance with a difference between the low-boundary reference voltage V_bl and the ramp signal RA. In other words, the differential pair constructed of the transistors P5 and P6 is controlled by the low-boundary reference voltage V_bl and the ramp signal RA for allowing a periodically-varying component of the current I_a to flow through the transistor P5 in accordance with the variation of the ramp signal RA. The current I_a supplied from the transistor P4 is distributed to the transistor P8 in accordance with a difference between the ramp signal RA and the high-boundary reference voltage V_bh. In other words, the differential pair constructed of the transistors P7 and P8 is controlled by the ramp signal RA and the high-boundary reference voltage V_bh for allowing a periodically-varying component of the current I_a to flow through the transistor P8 in accordance with the variation of the ramp signal RA. Subsequently, the periodically-varying components flowing through the transistors P5 or P8 are combined together and then converted to a current I_b by a current mirror constructed of NMOS transistors N3 and N4.

[0048] The threshold signal V_peak—TH is implemented by a potential difference across a resistance Rb through which the currents I_a, I_b, and I_c flows, which may be expressed as the following equation (8):
V_peak—TH=(I_a−I_b+I_c)·R_b  (8)

[0049] The current I_a is generated to approximately simulate the variation of the input voltage V_in in the equation (1). Since the current I_b changes in response to the current I_a and the ramp signal RA, the current I_b is suitable for approximately simulating the variation of the threshold signal V_peak—TH caused by the duty ratio D and the input voltage V_in. The current I_c is a constant offset current for shifting a DC level of the threshold signal V_peak—TH. In one embodiment of the present invention, the low-boundary reference voltage V_bl is set at 0.5 volts, the high-boundary reference voltage V_bh is set at 0.75 volts, and the ramp signal RA is set to linearly change from 0 volt to 0.8 volts. Under such parameters, the combination of the currents I_a, I_b, and I_c expressed in the equation (8) is able to approximately simulate the threshold signal V_peak—TH under the situation that the duty ratio D is between 0.66 and 1.

[0050] It is should be noted that the circuitry and method according to the present invention is not limited to the preferred embodiment described above and can be widely applied to various topologies of switching voltage regulators, such as synchronous or non-synchronous, boost or buck, voltage feedback control or current feedback control, pulse width modulation (PWM) or pulse frequency modulation (PFM), and the like. FIG. 7 is a circuit block diagram showing a synchronous switching boost regulator according to the present invention. The boost regulator of FIG. 7 is different from the buck regulator of FIG. 4 in the connection relationship between the high-side switch HS and the inductor L, a switching logic circuit 70, and a threshold peak current setting circuit 75. As shown in FIG. 7, the inductor L is connected between the input voltage V_in and the common node CN while the high-side switch HS is connected between the common node CN and the output terminal. The switching logic circuit 70 supplies the high-side drive signal HD and the low-side drive signal LD through the normal output terminal Q of the SR latch. The threshold peak current setting circuit 75 generates the threshold signal V_peak—TH representative of the threshold peak current I_peak—TH flowing through the inductor L, which may be expressed as the following equation (9):

[0051] $\begin{array}{cc}{I}_{\mathrm{peak\_TH}}=\left(\frac{T_s}{L}\right)·D·\left(1-D\right)·V_{\mathrm{out}}& \left(9\right)\end{array}$

[0052] Comparing the equations (9) and (1), it is found that the output voltage term V_out of the equation (9) corresponds to the input voltage term V_in of the equation (1). Therefore, the threshold peak current setting circuit 75 applied to the boost regulator determines the threshold signal V_peak—TH in response to the output voltage V_out and the ramp signal RA generated from the oscillating circuit 11. More specifically, it is easy to obtain the threshold peak current setting circuit 75 applicable to the boost regulator of FIG. 7 if the output voltage V_out is substituted for the input voltage V_in of the threshold peak current setting circuit 45-1 shown in FIG. 5 or the threshold peak current setting circuit 45-2.

[0053] While the invention has been described by way of examples and in terms of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications.