Low switching frequency power factor correction circuit

[0001] This application claims the benefit and priority of U.S. Provisional patent application Ser. No. 60/642,826 filed Jan. 11, 2005 entitled LOW SWITCHING FREQUENCY POWER FACTOR CORRECTION CIRCUIT, U.S. Provisional patent application Ser. No. 60/638,125 filed Dec. 22, 2004 entitled LOW SWITCHING FREQUENCY POWER FACTOR CORRECTION CIRCUIT, and U.S. Provisional patent application Ser. No. 60/578,010 filed Jun. 7, 2004 entitled LOW SWITCHING FREQUENCY POWER FACTOR CORRECTION CIRCUIT, the entire disclosures of which are incorporated herein by reference.

[0002] The present invention relates to power factor correction (PFC) methods and circuits. PFC circuits are known in the literature and are applied in a broad range of electronic equipment, ranging from lighting ballast circuits, to switch mode power supplies, to motor drives.

[0003] Such types of equipment generally require a direct current (DC) input voltage to operate properly, and the DC voltage is usually obtained by rectifying and filtering an alternating current (AC) line voltage.

[0004] However, any time a non linear load (like an input rectifier bridge followed by a filtering capacitor) is applied to the AC line, such load produces a distortion of the line current from being sinusoidal and in phase with the line voltage.

[0005] Such distortion has to be limited for several reasons, but mainly to reduce the losses in the line distribution network as well as the electromagnetic interference (EMI).

[0006] Various countries (especially Europe) have issued regulations which define limits to the harmonic content of the current absorbed by any kind of equipment connected to the main distribution network (the AC line), with classifications which apply to different equipment and diversely limit such harmonic content.

[0007] For that reason, various types of power factor or harmonic correction circuits (active or passive) have been developed which, added at the input of the equipment, make the equipment compliant with such regulation limits.

[0008] For non cost sensitive applications, a properly controlled boost PFC topology is usually applied. Such topology is able to shape the input line current to be substantially sinusoidal and in phase with the line voltage, and is able to regulate quite well the output DC voltage versus load (the power drawn by the equipment) and line variations, but has the following drawbacks:

• • [0009] a) complex and expensive power electronic circuitry is required;
  • [0010] b) high frequency operation generates high frequency EMI;
  • [0011] c) the circuitry acts as a “series” connected active filter in between the rectified line voltage and the equipment to be fed, thereby transmitting all the power drawn by the equipment; and
  • [0012] d) due to that, and due to the high frequency operation, the boost PFC introduces power losses which, often, are not negligible with respect to the total power losses of the equipment to be fed. For a motor drive, for example, electrical to mechanical energy conversion efficiency is greatly reduced.

[0013] On the other hand, cost sensitive applications which handle limited amounts of power (below 1 HP) try to avoid the use of such expensive active PFC methods and only use passive filters (usually inductors) in series with the line (before or after the rectifying bridge) at the input of the equipment.

[0014] Such “passive” filters, have several drawbacks:

• • [0015] a) they are bulky (and sometime expensive);
  • [0016] b) they also transmit all the power consumed by the equipment, so dissipate significant power;
  • [0017] c) they constitute a series impedance at the equipment's input, thereby reducing the DC voltage available at the equipment itself; furthermore, the voltage drop generated by such series impedance changes with the load. For example: for a motor drive, if the motor requires more torque (hence current) at high speed, the voltage available to the motor goes down (while, at high speed, more voltage would be required).

[0018] In the recent past, some “low switching frequency” or “line frequency” active filters have been proposed.

[0019] One example is reported in the paper: “A Double-Line-Frequency Commutated Rectifier Complying with IEC-1000-3-2 Standards” by Jose' Antenor Pomilio, School of Electrical and Computer Engineering, University of Campinas (Brasil) and Giorgio Spiazzi, Department of Electronics and Informatics, University of Padova (Italy). Such methods have the general advantage that only part of the power drawn by the equipment is transmitted by the “active” filter, which then dissipates very little power itself. Also, the main filter inductor may be much smaller and cheaper when compared to the one used in a simple passive filter. The circuit switches at line frequency, so power dissipation due to switching losses is further greatly reduced. Finally, such methods generally provide quite good regulation of the output voltage of the filter stage versus load, but, when the auxiliary switch is being driven only once for every line half period as described in the paper, have the general drawback that regulation of the output voltage versus the input (line) voltage variations is very poor.

[0020] Another aspect to be considered in cost-sensitive applications is the housekeeping power supply for peripheral circuits such as logic and control circuits. Generally speaking, both the harmonic correction circuit logic or control circuitry and the logic or control circuitry of any equipment/power stage which is fed by the harmonic correction circuit needs a low voltage DC power supply. Such low voltage supply is usually derived by a dedicated circuit (very often a flyback switching power supply directly fed by the rectified line but sometimes a step-down switching regulator) which adds a significant cost to the whole power conversion chain, and, by switching at high frequency, introduces other EMI. In other cases, a simple resistive drop is used, which dissipates much more power than the power it actually delivers to the housekeeping circuitry.

[0021] It is therefore a primary objective of the invention to provide a method for limiting the harmonics of the line current by using a low switching frequency harmonic correction circuit (HCC), which only transmits a part of the total power drawn by the equipment to be fed, and which is able to provide good line and load regulation of the output DC voltage which feeds the equipment.

[0022] It is another objective of the invention to integrate the housekeeping power supply into the structure of the harmonic correction circuitry and provide an efficient housekeeping power supply which also does not generate substantial additional EMI.

[0023] A method and apparatus for limiting the harmonics of the line current by using a low switching frequency power factor correction or harmonic correction circuit (HCC) is disclosed herein. The invention comprises a power factor correction circuit for driving a switch of a boost type converter circuit having an AC line frequency input, comprising a sense circuit for sensing and comparing the output voltage of the boost type converter circuit to a reference voltage; a circuit responsive to the output of said sense circuit for providing a drive signal for driving said switch, wherein said drive signal comprises a pulsed signal comprising a pulse grouping during each half cycle of the AC line frequency comprising at least one pulse wherein the number of pulses and frequency of the pulses in the pulse grouping changes with the output of said sense circuit up to a threshold value with the pulse width of the pulses being substantially constant; and when said output of said sense circuit has reached said threshold value, the pulse width of said pulses of said pulse grouping are varied in accordance with the output of said sense circuit.

[0024] In a preferred embodiment, the sense circuit comprises an error amplifier having an output and the circuit responsive to the sense circuit comprises an oscillator having an input coupled to the output of the sense circuit and wherein the oscillator produces an oscillator signal driving the switch, the oscillator signal having a maximum frequency of operation corresponding to said threshold value.

[0025] The circuit is able to achieve good regulation of the output voltage versus both load and line variations in a large range, while keeping harmonics of the line current below limits imposed by International Regulations (mainly European EN61000-3-2 for Class A equipment). The circuit is also able to generate an auxiliary power supply which may be needed by the controller for the correction circuit itself and by other equipment or power stages which are fed by the correction circuit.

[0036] Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.

[0037] In FIG. 1, which is a prior art circuit, RL represents the equipment to be fed (very often a further power conversion stage) as the “equivalent” load to the harmonic correction (or power factor correction) circuit. The harmonic correction circuit comprises L1,C1,L2,S1, D1 and D2, while C2, together with BR1, represent the standard rectifying and filtering stage which, alone, would produce substantial distortion of the line current. In FIG. 1, the housekeeping power supply is not shown.

[0038] Referring to FIG. 1, it is clear that the circuit of FIG. 1 has several “degree of freedom” with respect to how the switch S1 can be driven ON and OFF during each line half-period.

[0039] Firstly, the modulation of switch S1 has to be the same for subsequent line half periods. In-fact, if it were different between two subsequent half line periods, the line current would become rich in even harmonics, whose regulation limits are much more stringent than for odd harmonics.

[0040] Given this constraint, there are a number of possibilities for modulating switch S1. It is, of course already known to change the pulse width. Moreover, there are other possibilities for modulating switch S1. For example, switch S1 can be driven ON and OFF more than once in each half line period. Pulses may be synchronized or non synchronized with the line voltage zero crossing, or they may be delayed with respect to the line voltage zero crossing by a desired amount. Further, they can be “grouped” in the sense that their distribution across the half line period may not be necessarily uniform.

[0041] Every time switch S1 in turned ON, energy is accumulated into inductor L2 by slightly discharging capacitor C1. Then energy stored in L2 is transferred back to the capacitor C2 via diode D2 and thus to the load RL when switch S1 is turned OFF.

[0042] Prior art describes that, by increasing pulse duration (or width), more energy is stored into L2 and thus there is more “boost” effect which increases the voltage on capacitor C2 (the DC output voltage). On the other hand, by just increasing pulse width, more stress occurs on capacitor C1, inductor L2 and switch S1 (and, partially, also on diode D2).

[0043] According to one aspect of the invention, by increasing the number of pulses and leaving the pulse width unchanged, one can achieve the same effect but without stressing the above indicated components.

[0044] Further, according to the invention, by combining changing pulse width and pulse number or frequency, very good regulation of the DC output voltage can be achieved not only for load variations, but also for line variation over a large range (for example: 198 Vrms to 254 Vrms).

[0045] On the other hand, increasing pulse number to more than one pulse for each line half-period, increases line current distortion. Thus, a preferred modulation strategy is disclosed which maintains low line current distortion while keeping the benefits of achieving DC output voltage regulation versus load and line variations, and limiting the stress on components C1, L2, S1 and D2.

[0046] A preferred modulation strategy has been found to be one where pulses are started with a delay corresponding to a quarter of the half line period (2.5 msec with 50 Hz line), and are concentrated in a portion (approximately half) of such half-line period (5 msec for 50 Hz line), so concentrated around the line voltage peak. This is shown in FIG. 4. In FIG. 4, the pulses are the gate voltage applied to switch S1 which can be an IGBT or mosfet or bipolar transistor. In case of a bipolar transistor, the pulses are the base current.

[0047] This modulation strategy has been found experimentally. It can in fact be shown that a closed solution to the system of differential equations which govern the circuit behavior does not exist for multiple pulses.

[0048] An example of how the circuit can regulate output DC voltage is now provided.

[0049] At Vline=254V, 1 pulse with a 60 usec duration and delayed by 2.5 msec with respect to the line voltage zero crossing provides a 336V output with 637 W effective output power.

[0050] Going down to 230V, 10 pulses of 60 us duration are needed to maintain the same output voltage.

[0051] Going further down to 198V, 10 pulses of 110 us duration or 15 pulses of 80 us duration or any other combination of pulse number and pulse width is available to provide a 336 V output.

[0052] FIG. 6 show the harmonic content of the line current, compared with the EN61000-3-2 Class A limits, for the above described four operating conditions.

[0053] FIG. 6 show the spectra of the line current (limited to 19^th harmonic for sake of clarity) for the proposed circuit, when the optimized pulse strategy, which is another object of the invention, is applied, to maintain constant DC output voltage versus line variations (the four columns for each harmonic number correspond to line current harmonics drawn for four different values of the line voltage between 198 and 254 Vac) at constant output power (637 W in the example).

[0054] The last column for each harmonic number in FIG. 6 are the limits as per EN61000-3-2 Class A, here reported for sake of clarity.

[0055] Now referring to FIG. 5, a preferred circuit to realize such combination of pulse number and pulse duration is described.

[0056] Zero crossing detector 10 provides short pulses every line voltage zero crossing. Such pulses (whose duration shall preferably be few usec to few tens usec) feed a logic circuit 12 (which may be realized by a monostable multivibrator and logic circuitry or by a microcontroller) which generates a fixed or programmable delay and window for a pulse grouping. Such circuit will generate the window for the pulse grouping, i.e., the window within which the pulses of the pulse grouping can be applied to the gate (or base) of S1 by the control circuit.

[0057] Error amplifier EA (14) provides an error signal which is the difference between a reference voltage (Vref: the desired DC output voltage) and the actual DC output voltage at the output of the circuit.

[0058] Such error signal commands a VCO (voltage controlled oscillator) 16 which provides, for example, a square wave whose frequency increases as the error signal increases.

[0059] Since the frequency could become very high (mainly when the circuit is first connected to the line voltage and capacitor C2 is fully discharged), a frequency limiter 18 is provided which limits the frequency to a reasonable level. This frequency, which also corresponds to the number of pulses in the grouping window, depends on the design constraints of the circuit.

[0060] The VCO 16 and the frequency limiter 18 are preferably designed to provide at least one pulse. The reason for this will be explained later on.

[0061] Power dissipation of the proposed circuit increases as the number of pulses increases. Main sources of power dissipation are the parasitic equivalent series resistance (ESR) of C1, the parasitic resistance of L2, and the conduction losses of the switch S1, plus some loss due to the forward conduction voltage of D2.

[0062] Power dissipated into L1 and D1 is instead almost constant and independent of the number of pulses provided to the control electrode of switch S1.

[0063] Thus, depending on the design of L2,C1,S1 and D2, one may want to limit the power dissipation by limiting the maximum number of pulses. This will limit the range of input voltage and load where constant VoutDC may be achieved but the best trade-off depends on the specific application requirements.

[0064] Frequency limiter 18 can also be an integral part of the VCO, i.e., the VCO can be designed in a way to be intrinsically frequency limited.

[0065] The signal from the VCO/Frequency limiter 16,18 has been described as a square wave of variable frequency. This is not a limitation. A variable frequency sinusoidal waveform can be used instead. In this case, a simple comparator (not shown in FIG. 5) can be used to provide a square wave signal.

[0066] The leading edge (or the trailing edge) of this square wave is applied to a monostable multivibrator 20, which provides a control signal to the gate (or base) of S1 comprising the pulses of the pulse grouping whose duration is generally only few tens microsec to a few hundred microsec.

[0067] Pulses are actually provided to the gate (or base) of S1 via any kind of suitable driver (not shown in the figure) whose function is to adapt the output impedance of the monostable to the input impedance of S1.

[0068] The monostable 20 generates pulses whose pulse width must be controlled in a proper way.

[0069] In particular, until the frequency has not yet reached its maximum, pulse width is fixed to the minimum value (Tpulse,min) which, in turn, depends on the design constraints of the application. When the frequency has reached its maximum, and the frequency limiter starts working, pulse width is increased to provide voltage regulation.

[0070] This is performed by a mode selector 22, which, in one possible form, is shown in FIG. 7.

[0071] With reference to FIG. 7, the block Fmax (30) provides a frequency equal to the maximum frequency set in the VCO/frequency limiter 16,18. The two frequencies must be synchronized with each other.

[0072] Assuming the two frequencies are square waves with 50% duty cycle, when the VCO frequency is lower than Fmax, the exclusive-OR 32 output of the two signals provides a series of pulses of variable duration which, when filtered by filter 34, provides an analog signal greater than zero.

[0073] When the two frequencies are equal to each other, the exclusive OR provides a constant logic ZERO, which, filtered, provides an analog output signal equal to zero volts.

[0074] Such signal feeds an operational amplifier 36, which receives on its negative input the output voltage of the error amplifier EA (14) of FIG. 5.

[0075] When the VCO frequency and Fmax are different, the gain of the operational amplifier 36 is set in such way that the signal out of the filter, through resistor R1, saturates the amplifier 36 internal to the mode selector 22. So, the output of amplifier 36 will be at the maximum level.

[0076] When the two frequencies are equal, the output voltage from the filter becomes zero, and the amplifier 36 will simply amplify, with a desired gain, the output voltage from the error amplifier 14.

[0077] The output signal of amplifier 36 feeds the gate of a signal mosfet 38 (VR in FIG. 7) which acts as variable resistance across R4 for the charging of capacitor Cmono (40).

[0078] VR, R4 and Cmono are the components of the monostable multivibrator 20 that select the pulse width of the monostable block, which, in turn, provides the pulses for the control of S1 in the circuit of FIG. 5.

[0079] In this way, when VCO 16 has not yet reached its maximum frequency, the VR resistance will be at the minimum, thus providing a constant pulse width from the monostable with a variable number of pulses based on the VCO frequency and thus variable frequency.

[0080] When the VCO frequency has reached Fmax, the output from EA 14 will start to modulate the ON-resistance of the mosfet VR, thus modulating the pulse width at constant frequency because the VCO is at Fmax.

[0081] Resistor R4 in parallel to VR will simply assure that, even in case of saturation of the EA 14 output, pulse width is limited to a maximum value.

[0082] Too long a pulse width could increase the stress level on components L2,C1,S1 and D2 of FIG. 5.

[0083] Thus, as the output voltage of the circuit of FIG. 5 decreases, assuming the maximum frequency has been reached, the output of error amplifier EA will increase causing the output of amplifier 36 to decrease, resulting in increased VR resistance and thus increasing the pulse width, thereby driving the output voltage higher. When the output voltage increases, the error amplifier output will decrease. Assuming the frequency of the VCO is at a maximum, this will result in an increased output from amplifier 36, causing the VR resistance to decrease, resulting in a reduced pulse width and driving the output voltage lower.

[0084] In case of no load at the output of the circuit of FIG. 5, error amplifier 14 will command the VCO to minimum frequency (one pulse every line half-period) and the monostable will generate a pulse with the minimum designed width.

[0085] The behavior in case of no load conditions is important for the following discussion about the housekeeping power supply.

[0086] Before discussing the housekeeping supply, the case where the input voltage is very low or the desired output voltage is very high needs to be examined. In this case, to achieve more boost action, Fmax has to be selected to be relatively high. Frequencies Fmax above 1 kHz are possible but, in that case, high frequency harmonics could start to appear in the line current spectra. More particularly, differential mode electro-magnetic noise as well as common mode electro-magnetic noise will start to be present.

[0087] While differential mode noise is well filtered by L1 (which, together with C1 also acts as a high frequency input filter), common mode noise is more difficult to predict because it strongly depends on leakage paths to Earth potential (possibly including parasitic capacitances of L1 due to its physical construction).

[0088] It is well known that common mode noise can be reduced by inserting a common mode inductor at the converter's input or, simply, by balancing the inductive impedance at the same input.

[0089] Thus, by moving L1 from the diode's bridge output side to its input side, and by splitting it into two separate but equal inductors each one equal to half of the original L1 value, while not altering in any way the behavior of the circuit, may have the added benefit of limiting the common mode noise eventually generated in case of high Fmax values. This is shown in FIG. 9.

[0090] Now with reference to FIG. 8, it may be seen that inductor L2 has been modified to be a transformer, whose turn ratio is chosen to achieve the desired housekeeping DC voltage. The voltage waveform at the transformer's output is rectified by, for example, bridge BR2 and filtered by CH.

[0091] The energy transferred to the housekeeping power supply depends on the number of pulses, according to the modulation strategy previously described.

[0092] Thus, when the correction circuit is operating with a certain load (different form zero), S1 will be driven by one or more pulses with variable width, to regulate output voltage versus line and load variations. At minimum load and maximum line voltage, a single pulse with minimum width will be generated while at maximum load and minimum line voltage a maximum number of pulses with maximum width will drive S1.

[0093] In that sense, the housekeeping power supply output will be variable, not regulated. This is not a problem because, considering the usually low power needed by the logic circuitry, a simple linear voltage regulator will provide regulated voltage required by the logic circuitry itself.

[0094] But, in the case of a completely zero load, even a single pulse on S1, with a minimum width, can provide a boost action which is too great. This could cause dangerous over voltages across capacitor C2 and the following equipment/power stages.

[0095] To avoid this, diode D1 is changed to a mosfet M1 (see FIG. 8). M1 is kept OFF during normal operation, so that its body diode performs the function which was performed by D1. When in zero load condition, C2 will start to charge until a threshold, but still safe over voltage situation is detected by comparator COMP1. When the threshold is reached, the output of COMP1 will then switch M1 ON.

[0096] With M1 ON, energy stored into L2 will be diverted back to C1, instead of being delivered to C2. In this way, C2 and the following equipment/power stages will be kept at a safe voltage.

[0097] At the same time, L2 will always be operated at least once every half line period, thereby assuring a proper energy transfer to the housekeeping output.

[0098] COMP1 should have a proper hysteresis (represented by R6 in FIG. 8). As soon as M1 is driven ON, the output voltage will fall to a level which is equal to the peak line voltage. COMP1 must continue to drive M1 ON in these conditions.

[0099] Then, in case a load is applied again at the output, the output voltage will rapidly go down and COMP1 will reset to switch M1 OFF. Error amplifier EA will now go out of saturation and normal operation will be restored.

[0100] All these transients are not very critical. The described circuit is very fail-safe in case M1 fails in a short condition or in case COMP1 fails in driving M1 always ON. If this happens, the output voltage will not rise to the level commanded by EA. EA will try to command the maximum pulse frequency and width, and there will be some power dissipation into the circuit of C1, L2, S1 and D2 but within the design limits. The circuit will continue to provide harmonic correction but will not be able to the regulate output voltage. Nevertheless, no circuit damage will occur.

[0101] In FIG. 8, a P-channel mosfet has been used for M1. The output of COMP1 can very easily drive this mosfet by using a couple of resistors (R5 and R7). Of course also an N-channel device can be used, increasing a bit the gate drive complexity, for example, by using a charge pump or bootstrap type supply.

[0102] FIG. 9 shows the circuit of FIG. 8 wherein the inductor L1 has been split and moved to the input to limit common mode noise.

[0103] Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. Therefore the present invention should be limited not by the specific disclosure herein, but only by the appended claims.