Receiver for clock and data recovery and method for calibrating sampling phases in a receiver for clock and data recovery

[0001] The present invention relates to a receiver for clock and data recovery and a method for calibrating sampling phases in a receiver for data and phase recovery.

[0002] A clock and data recovery (CDR) receiver can be used for high-speed serial links. A simplified block diagram of a high-speed serial link is shown in FIG. 1. If data, which exit as n-bit wide data words DP, should be transferred over a channel C, e.g. a cable or an optical fiber, in which the data can be transferred only serial, the n-bit wide parallel data DP have to be converted at first into a serial data stream DS. This is carried out by a multiplexer M, which switches sequentially the n-bit data lines at its multiplexer inputs M.1, M.2, M.3 to M.n to its output M.10, in fact in dependence to a clock signal TXCLK. After the data DP have been transmitted as serial data stream DS over the channel C they have to be recovered out of the data stream DS. Therefore a clock and data recovery unit R is provided, which is connected with its input R.1 to the channel C and which puts the recovered clock RCLK on its clock output R.3 and the recovered data RDATA on its data output R.2. At the data output R.2 of the clock and data recovery unit R the recovered data RDATA are still present in serial form. To convert the recovered data RDATA back into parallel data the data output R.2 of the clock and data recovery unit R is connected to a data input D.10 of a demultiplexer D, which switches the data input D.10 sequentially to the n data outputs D.1, D.2, D.3 to D.n. At the output terminal D.30 the data clock DCLK is available.

[0003] The higher the data transfer rate in the channel C is, the sooner the timing accuracy during any decision-making process gets a key issue in the design of high-speed serial links. Such decisions have to be made at several points in the system, for example when launching a bit at the transmitter, when determining the bit value of an incoming symbol at the receiver, and when measuring the position of the bit edge at the receiver to determine if the bit is early or late. Any inaccuracy or noise in the timing of those decisions is directly degrading the jitter budget of the link and therefore severely complicating the design.

[0004] The invention relates to the calibration of the relative timing positions of sampling phases. High accuracy of the sampling clocks is a key requirement in the design of high-speed serial links above 4 GBit/s in high performance CMOS (complementary metal oxide semiconductor) processes. If there is any offset in the position of the individual sampling edges, timing jitter is added to the system. At 100 ps to 200 ps cycle time, a few picoseconds are already making the difference between an acceptable and an unacceptable bit error rate (BER).

[0005] One reason for an offset which leads to inaccuracy in the sampling phase lies in the manufacturing process. The gate thickness for deep-sub-micron CMOS technologies measures only a couple of atoms. The threshold voltage of a CMOS device is a function of the gate thickness. Due to the fact that the number of atomic layers that form the gate oxide is very difficult to control, threshold voltage shifts have to be expected, which in turn lead to aforementioned inaccuracies.

[0006] One possibility to reduce the inaccuracy is to increase the power. Another possibility consists in there that the circuit layout with regard to the clock distribution is done very carefully. But both solutions are not always desirable and have obviously disadvantages.

[0007] An object of the present invention is to provide a receiver for clock and data recovery and a method for calibrating sampling phases in a receiver for data and phase recovery that allows to reach high accuracy in the sampling phase position without the associated high power.

[0008] Advantageously, also defect sampling latches can be detected with the invention.

[0009] According to one aspect of the invention, this object is achieved by a receiver for clock and data recovery with the features of the independent claim 1, and by a method for calibrating sampling phases in a receiver for clock and data recovery with the features of the independent claim 14.

[0010] The receiver for clock and data recovery according to the invention comprises n sampling latches for determining n sample values of a reference signal at n sampling phases having sampling latch inputs and sampling latch outputs. The receiver further comprises a phase position analyzer connected to the sampling latch outputs for generating an adjusting signal for adjusting the sampling phase, if the sample value deviates from a set point and a phase interpolator for generating sampling phases. A sampling phase adjusting unit connected with its adjusting inputs to the phase position analyzer and the phase interpolator and with its outputs to the sampling latches is provided for generating adjusted sampling phases depending on the sampling phases and the adjusting signal.

[0011] The method for calibrating sampling phases in a receiver for clock and data recovery according to the invention comprises the following steps:

• • [0012] First a reference signal is led to n sampling latches.
  • [0013] Then the reference signal is sampled at different sampling phases and the corresponding sample values are determined with the sampling latches.
  • [0014] At least, if the sample value deviates from a set point the corresponding sampling phase is corrected.

[0015] Advantageous further developments of the invention arise from the characteristics indicated in the dependent patent claims

[0016] Preferably the phase position analyzer in the receiver according to the invention comprises means for determining average values of the sample values. Average values can easily be calculated and make it easier to determine the appropriate adjusting signal.

[0017] The phase position analyzer of the receiver typically comprises means for increasing the adjusting signal, if the average value is lower than a set point, and for decreasing the adjusting signal, if the average value is higher than the set point.

[0018] In an embodiment of the receiver according to the invention the set point amounts 0,5 if the sample phase should be synchronized with an edge of the reference signal.

[0019] In an another embodiment of the receiver according to the invention the sampling phase adjusting unit comprises a buffer or inverter with a programmable delay time. With that the sample phase generated by the phase interpolator can be easily corrected if necessary.

[0020] In an alternative embodiment to the aforementioned the sampling phase adjusting unit of the receiver according to the invention comprises a phase interpolating device for interpolating two consecutive sample phases.

[0021] In a further embodiment the interpolating device comprises first and second means for weighting the two sample phases.

[0022] In a third alternative embodiment to the aforementioned the sampling phase adjusting unit of the receiver according to the invention comprises a phase interpolating device for interpolating three sample phases, wherein one of these is a nominal sampling phase superimposed by the two other phases.

[0023] Furthermore the receiver can comprise a data input for receiving serial data, which shall be recovered, and switching means connected to the sampling latch inputs, wherein the switching means are provided for leading the serial data signal or the reference signal to the sampling latch inputs.

[0024] In a typical application the receiver according to the invention comprises a sample memory for storing the sampled values. The sample memory is connected between the sample latches and the phase position analyzer.

[0025] In a further embodiment the reference signal in the receiver has a constant phase and a constant frequency.

[0026] In a still further embodiment the receiver according to the invention comprises a phase locked loop for generating the reference signal.

[0027] In another embodiment, the receiver comprises a data output for delivering parallel data connected to the sample memory. The receiver further comprises an edge detection unit for detecting edges in the serial data signal, which is connected between the sample memory and a control input of the phase interpolator.

[0028] In another aspect of the method according to the invention the receiver is switched in calibration mode and the reference signal is led to the sampling latches.

[0029] In a typical application the method according to the invention the receiver is switched in recovery mode after the calibration is finished. With that it can be ensured that the recovery of the data taking place after the calibration can be carried out with an optimized bit error rate.

[0030] In an embodiment of the method according to the invention the determination of the sample values comprises the following steps:

• • [0031] a) The reference signal is sampled s times at a first sample phase position, wherein the sample value of the reference signal is determined each time with the first sample latch.
  • [0032] b) From the s sample values an average value is calculated.
  • [0033] c) These steps are repeated at n sampling phases, wherein at the nth sampling phase each sample value is determined with the nth sample latch.

[0034] In an another embodiment of the method according to the invention the correction of the sampling phase comprises the following step. The sampling phase is increased if the average value is lower than 0.5. The advantage of this rule is that it can be easily implemented and evaluated.

[0035] It is also possible that the correction of the sampling phase in the method according to the invention comprises the following step. The sampling phase is decreased if the average value is higher than 0.5. The advantage of this rule is that it can be easily implemented and evaluated.

[0036] At least, the method according to the invention comprises the following steps:

• • [0037] The sampling phases are shifted by a predetermined value.
  • [0038] The reference signal is sampled at said shifted sampling phases and the corresponding sample values are determined with said sampling latches.
  • [0039] If the sample value deviates from the set point, the corresponding sampling phase is corrected.
  • [0040] These steps are repeated as often as it is necessary for synchronizing all sampling phases with the reference signal.

[0041] With this advantageously all sampling phases can be corrected.

[0055] FIG. 1 shows, as already described above, a block diagram of a serial link. The invention concerns the realization of the clock and data recovery receiver comprising the clock and data recovery unit R and the demultiplexer D.

[0056] Before the data stream DS, also called serial data signal, is received and recovered by the clock and data recovery unit R the receiver is switched in a calibration mode.

[0057] In the calibration mode a reference signal Ref2 with constant frequency and constant phase is sampled. The reference signal Ref2 may have the form as illustrated in FIG. 2a. At the time t0, what is equivalent to the phase (φ=0, the reference signal Ref2 changes its level from low to high and stays on this level for a certain period nbt. This period is called nominal bit time nbt. After this period at the phase (φ=180° the reference signal Ref2 returns to low. In practice the rising edge 21 of the reference signal Ref2 does not have a vertical course but increases during a rising period until it has reached its high level. In practice the time when the rising edge 21 appears is also subjected by a certain inaccuracy. The period in which the rising edge 21 appears is indicated in FIG. 2a by the time Δt1. The same analogously also applies to the falling edge 22 of the reference signal Ref2. The period in which the falling edge 22 appears is indicated in FIG. 2a by the time Δt2. The reference signal Ref2 is sampled now with sampling latches at the sampling phases (φ1, φ2, . . . φ6. The sample values are determined with the sampling latches SL1 . . . SL6, wherein each sampling latch is assigned to a sampling phase (φ1, φ2, . . . φ6. Therefore, there are n sampling latches SL1 . . . SLn, if there are n sampling phases (φ1, φ2, . . . φn. If at the sampling phase φ1 the sample value SV is determined s times with the sampling latch SL1, an average value AV1(φ1) of these s sampling values SV1 . . . SVs can be calculated as indicated below.

[0058] $\mathrm{AV1}\left(\phi 1\right)=\frac{\mathrm{SV1}\left(\mathrm{\phi 1}\right)+\mathrm{SV2}\left(\phi 1\right)+\dots +\mathrm{SVs}\left(\phi 1\right)}{s}$
wherein
s=number of sample values SV at a certain sampling phase φ.

[0059] Analogous the same calculation can be done at the nth sampling phase φn:

[0060] $\mathrm{AVn}\left(\phi n\right)=\frac{\mathrm{SV1}\left(\phi n\right)+\mathrm{SV2}\left(\phi n\right)+\dots +\mathrm{SVs}\left(\phi n\right)}{s}$

[0061] At the bottom region of FIG. 2a the average values AV1 to AV6 corresponding to the sample phases φ1 to φ6 are shown. For example, the average value AV1 (φ1)=1, while the average value AV4(φ4)=0.

[0062] In FIG. 2a to 2c the reference signal Ref2 is sampled in 60° phase steps.

[0063] In FIG. 2b the reference signal Ref2 is moved with 90° towards the reference signal Ref2 from FIG. 2a. A sampling with the first sampling latch at the sampling phase (PI leads now to an average value AV1 (φ1)=0. In FIG. 2b the reading from the second latch, which corresponds to the second sampling phase φ2, will on average be as often zero as will be one. This is because the received waveform Ref2 has a zero-crossing right at that time. Therefore the average value AV2(φ2)=0.5. The same analogous applies to the fifth average value AV5(φ5), which is also 0.5.

[0064] In FIG. 2c the second sampling latch, which is used for determining the s sample values SV1(φ2) . . . SVs(φ2) at the sampling phase φ2 and therefore for the calculation of the average value AV2(φ2) shows a sampling phase error Δφ of 10°. Due to this fact, the reference signal Ref2 is sampled 10° too early. Therefore, sample values SV1(φ2) . . . SVs(φ2) are more often zero than one and the average value AV2(φ2) will be decrease to 0,25. It is not zero due to jitter effects.

[0065] FIG. 3 shows a block diagram of a clock and data recovery receiver according to the invention. The serial data signal DS is put on the input IN1 of the receiver, which is connected to a preamplifier 12 for a preamplification of the serial data signal DS. The output of the preamplifier 12 in turn is connected to a first input terminal 11.2 of a switch 11. A second input terminal 11.1 of the switch 11 is connected to the output 10.2 of a phase locked loop (PLL) 10, which generates a reference signal Ref2 with a frequency fpLL from a reference signal Ref1. The reference frequency fPLL of the reference signal Ref2 is a multiple, e.g. a 16-fold of the frequency of the reference signal Ref1 and has a constant phase and a single frequency. The phase locked loop 10 serves as frequency multiplier for the frequency of the reference signal Ref1 and generates also reference signals for a 360° phase interpolator 9 and a main oscillator 14. For this purpose, the PLL outputs 10.3 and 10.4 are connected to the input 9.1 of the phase interpolator 9 and the input 14.1 of the main oscillator 14. The outputs of the main oscillator 14, which deliver in the embodiment shown in FIG. 3 three phases, are connected to the inputs 9.1, 9.2 and 9.3 of the phase interpolator 9. The main oscillator 14 is not restricted to the generation of three phases. Depending on the requests the main oscillator 14 can also generate more than three phases. The phase interpolator 9 delivers n unadjusted sampling phases φu, in which n is the number of different sampling phases, to the input 6.2 of a sampling phase adjustment unit 6. Depending on a phase adjustment signal AS, which is from a sampling phase position analyzer 5, the sampling phase adjustment unit 6 corrects the n unadjusted sampling phases φu1 . . . φun and generates n adjusted sampling phases φa1 . . . φan. Examples of how the sampling phase adjustment unit 6 can be realized are illustrated in the FIGS. 4a, 4b and 4c. They will be explained in more detail later on. The sampling phase adjustment unit 6 may have for example a resolution of 0,15 UI (unit intervals). The n adjusted sampling phases φa1 . . . φan are led to the n parallel sampling latches 2, which sample the incoming serial data signal DS or reference signal Ref2 and determine the corresponding sample values SV1 . . . SVn as already shown in the FIGS. 2a, 2b and 2c. Which one of the two signals DS or Ref2 is sampled is decided by the switch 11. The n sampling latches 2 are followed by a metastability pipeline 3, which serves for generating n stable digital outputs. The metastability pipeline 3 and the sampling latches 2 are combined to a digitizing block 1. The n outputs 3.2 of the metastability pipeline 3 respectively the outputs 1.2 of the digitizing block 1 are connected to a sample memory 4, which stores the sample values SV1(φ1) . . . SV1(φn), SV2(φ2) . . . SVs(φn). With the sampling phase position analyzer (5), whose inputs 5.1 are connected to the outputs 4.4 of the sample memory 4, the average values AV1 to AVn are calculated and depending from it the phase adjustment control signal AS is adjusted. The second output 5.3 of the sampling phase position analyzer 5 is connected to the first input 13.1 of a switch 13. The second input 13.2 of the switch 13 is connected to an edge detection and early/late generator 7. Over the switch 13 is decided whether the output 7.2 of the generator 7 or the output 5.3 of the sampling phase position analyzer 5 is led to the input 8.1 of a phase interpolator 8. The input 7.1 of the edge detection and early/late generator 7 is connected to the output 4.3 of the sample memory 4. The number p of bits transferred from the sample memory 4 to the generator 7 is typically n plus 2. The first one of the two additional bits represents the sample value which is the one before the first of the n sample values SV(φ1). The second one of the two additional bits represents the sample value which follows the last one of the n sample values SV(φn).

[0066] Over an input IN3 the clock and data recovery receiver can be switched from a calibration mode into a recovery mode. In the calibration mode the switch 11 connects the reference signal Ref2 to the inputs 2.1 of the sampling latches 2 and the switch 13 connects the output 5.3 to the input 8.1 of the phase interpolator controller 8. However, in the recovery mode the switch 11 connects the preamplified serial data signal DS to the inputs 2.1 of the sampling latches 2 and the switch 13 connects the output 7.2 of the generator 7 to the input 8.1 of the phase interpolator controller 8.

[0067] A possible embodiment of the phase rotator 9 is described in the US patent application “Phase rotator and data recovery receiver incorporating said phase rotator”, US2002/0009170A1, which is owned by the patent applicant. Especially in the FIGS. 3, 7, 8 and 9 and the corresponding description of this application such an phase rotator and oscillator is illustrated.

[0068] The receiver according to the invention works as follows. At first the receiver is switched in the calibration mode. This can be done for example in the power up phase. In the calibration mode at first the sample phase position is measured. This can be done in the following way.

Measurement of Sample Phase Position

[0069] The measurement of the phase timing or sampling phase position is performed by supplying the single frequency reference signal Ref2 over the switch 11 to the inputs 1.1 of the digitizing block 1 and by analyzing the average sampling pattern.

[0070] This reference signal Ref2 is sampled several times and for all positions of the phase adjustment device comprising the phase interpolator 9 also called phase rotator and the sampling phase adjustment unit 6 of the receiver. The analysis of the resulting average value pattern obtained after reading the sample latches 2 allows an accurate determination of the phase error Δφ, e.g. the sampling phase error for the second latch is Δφ2=φ2−φ2′ as illustrated in FIG. 2c. The FIGS. 2a, 2b and 2c show the nominal sampling pattern for three-fold oversampling operating at half-rate.

[0071] By letting the phase interpolation device 9 go thru all its potential phase positions φ1 . . . φn, the average values AV1 . . . AVn of the sampling latches SL1 . . . SLn will change according to FIGS. 2a, 2b and 2c. For example, the reading from the second latch in FIG. 2b will on average be as often a ‘zero’ as will be a ‘one’. This is because the received waveform of the reference signal Ref2 has a zero-crossing right at that time.

[0072] Under the assumption that a 10° phase error Δφ2 in the second sampling latch occurs, the situation from FIG. 2b will change into the situation shown in FIG. 2c. The sampling phase φ2 is shifted by 10°, and therefore the average reading from sampling latch 2 is only 0.25. It is not zero due to jitter effects. Any average value AV not equal to 0.5 indicates that the sampling phase position φ is deviating from its ideal position. This information is used to adaptively shift the sampling phase φ to its ideal position, meaning to an average reading of AV=0.5. For this purpose the raising and the falling edges of the reference signal Ref2 are used. The sampling phases φ1 . . . φn are shifted as often as necessary so that each sampling phase φ1 . . . φn can be synchronized with a rising or a falling edge 21, 22 of the reference signal Ref2. In FIG. 2b the sampling phases φ2 and φ5 and therefor the sampling latches 2 and 5 can be synchronized with the edges of the reference signal Ref2 by reducing the sampling phase error Δφ=φ−φ′ so long till the average value AV is 0.5. By shifting the sampling phases φ1 . . . φn by 60° to the right, what is not shown in the FIG. 2a to 2c, the sampling phases φ3 and φ6 can be fine tuned and therefore be synchronized with the edges of the reference signal Ref2. In other words, if the phase interpolating device 9 has shifted the sampling phases φ1 . . . φ6 by additional 60°, the same situation as before can be expected now at the sampling latch SL3 and SL6. The calibration can therefore be repeated for the sampling phases φ3 and φ6. By shifting the sampling phases φ1 . . . φn by 60° to the left, what is also not shown in the FIG. 2a to 2c, the sampling phases φ1 and φ4 can also be fine tuned and therefore be synchronized with the edges of the reference signal Ref2. After that all sampling phases φ1 . . . φ6 and with that all sampling latches SL1 . . . SL6 are synchronized with the reference signal Ref2.

[0073] If the phase interpolator 9 is shifting the phases φ1 . . . φn to all nominal phase positions, all n sampling positions may be accurately calibrated.

[0074] It is noted that the receiver is still in calibration mode. In a second step the correction of phase positions is executed.

Correction of Phase Position

[0075] If the phase interpolating device 9 has the capability to control each of the sampling phases φ1 . . . φn individually, programming offset values OV in the phase interpolation control 8 is sufficient to correct the position of the sampling phase sφ1 . . . φn. However, this would require significant amount of on-chip memory to store the phase offset value for each sampling signal for each of its potential settings.

[0076] A more efficient way of implementing the phase adjustment is to add a programmable phase delay element 6 also called sampling phase adjustment unit after the phase interpolator 9 as shown in FIG. 3. Due to the fact that this phase delay element 6 has only to correct the residual errors Δφ, the dynamic range may be small and will probably be in the order of ±0.15 UI.

[0077] Various methods exist to adjust the phase of a sampling signal over a small range. In a first embodiment buffers 41 with programmable delay times as illustrated in FIG. 4a can be implemented in the sampling phase adjustment unit 6. The programming can affect the drive current or can add variable amount of capacitive loading to the output of the driver.

[0078] In a more preferred embodiment, which is shown in FIG. 4b, a phase interpolating device 42 that gets its inputs from two consecutive phases can be implemented in the sampling phase adjustment unit 6. This allows to interpolate from one phase to the other. The signals received at the two phase inputs can also be weighted by weighting units 44 and 45. Afterwards, the weighted signals are added by an adder 43.

[0079] In a third embodiment, a phase interpolating device 46 as shown in FIG. 4c can be implemented in the sampling phase adjustment unit 6. The phase interpolating device 46 can be realized in a form where the nominal sampling signal is superimposed by programmable levels of signal energy from on of its neighbors. The reference signs 48 and 49 indicate again two weighting units. The weighted signals and the nominal sampling signal are added with the help of an adder 47.

[0080] Preferably, this phase interpolation is integrated into the output stage of the 360° phase interpolating device 9.

[0081] After determination of the correction of the phase position the calibration mode is left and the receiver is switched in the recovery mode. The receiver works now with high accuracy concerning the clock and data recovery and with a very low bit error rate.

[0082] The FIG. 5 shows the result of a phase accuracy typical analysis. Each of the three sampling latches was read 512 times at a stable manual phase setting of the phase rotator 9. After that, the phase rotator 9 was manually moved by one phase step (1 UI/27) and each latch was read again 512 times. This read-step-read procedure was repeated over 1024 UI cycles (=512 times 54 phase steps). This corresponds to a total of 14 million measurements. The large amount of data allows good average factors in the post-mortem analysis to reduce timing noise, but in fact far less data would do the job as well.

[0083] In the FIG. 5, each phase reading was averaged over the 512 double bit cycles and three consecutive phases were timewise adjusted to have the same nominal transition time. As might be seen, the maximum phase difference is approximately 25 ps.

[0084] FIGS. 6, 7 and 8 demonstrate that this analysis method is a very powerful tool to analyze internal effects.

[0085] The FIG. 6 shows the three phases from FIG. 5 over one half-rate rotation (54 phase rotator steps). A comparison of the sampling latches SL1 and SL3 with the sampling latch SL2 shows that the second latch SL2 has problems with the falling edge of the input as might be seen from the early drop. Please note that the y-axis is showing averaged values with the implication that the falling edge jitter of phase 2 is significantly larger than it should be.

[0086] This is also a valid method to check if the sampling latch and its metastability pipeline are actually working. It would allow at-speed BIST. The FIG. 7 shows a latch SL6 that has problems with the falling edge. FIG. 8 gives the measurement result from a latch SL5 that is obviously dead, what is not very helpful for good BER performance.

[0087] Below are signs used in this document.

[0088]

M	multiplexer
C	data channel
D	demultiplexer
R	clock and data recovery unit
1	digitizing block
2	sampling latches
3	metastability pipeline
4	sample memory
5	sampling phase position analyzer
6	sampling phase adjustment unit
7	edge detector and early/late generator
8	phase interpolator controller
9	phase interpolator
10	PLL
11	switch
12	preamplifier
13	switch
14	main oscillator
IN1	receiver input
IN2	PLL input
IN3	control input
OUT	receiver output
φu	unadjusted sampling phase
φa	adjusted sampling phase
φ1	first sampling phase
φ2	second sampling phase
φ2′	second sampling phase with phase error
DS	serial data signal
DP	parallel output data
AS	phase adjustment control signal
Ref1	first reference signal
Ref2	second reference signal
fPLL	PLL output frequency
n	number of sampling latches
m	bit width of parallel output data
p	number of bits
s	number of sampling values at one sample phase
SV	sample value
AV	average value
Δt1, Δt2	periods
21	rising edge
22	falling edge
nbt	nominal bit time
41	buffer
42	phase interpolator
43	adder
44	first weighting unit
45	second weighting unit
46	phase interpolator
47	adder
48	first weighting unit
49	second weighting unit

[0089] Having illustrated and described a preferred embodiment for a novel data processing device and a method for data transfer, it is noted that variations and modifications in the device and the method can be made without departing from the spirit of the invention or the scope of the appended claims.