Transport processor for processing multiple transport streams

[0001] 1. The Field of the Invention

[0002] The present invention relates to methods and apparatus for processing incoming video streams, and more particularly, to methods and apparatus for performing a plurality of demultiplex processing operations on one or more incoming video transport streams.

[0003] 2. Background and Related Art

[0004] Advances in the field of digital video and digital video formats have increased the popularity of using digital video to transport video programming to users. Digital video data is transmitted to viewers using transport streams, which contain the encoded digital video data and the information used by transport stream processors to decode the video data so that it can be displayed to the viewers.

[0005] A transport stream includes a series of packets representing digital video data. The exact configurations of the data packets are defined by the digital video format used to encode the video programming. Two of the most common formats are digital video broadcast (DVB), which is based on the Moving Pictures Expert Group-2 (MPEG-2) standard, and digital satellite system (DSS) developed by DIRECTV. DVB has 188-byte packets while DSS has 130-byte packets. The packets of the transport stream include a payload in which the digital video data is encoded and a header that includes an identifier so that the transport stream processor can select packets that correspond to a desired program. In DVB, the identifier is called a packet identifier (PID), while in DSS, the identifier is called a service channel identifier (SCID). Each PID/SCID operates to identify packets of the given type.

[0006] There can be approximately 20 to 40 different PIDS/SCIDS within a transport stream, which typically includes multiple programs, each being represented by one or more PIDS/SCIDS. For example, a program may have one PID representing all audio packets, a different PID representing all video packets, and another PID representing packets containing processing information. Transport processing includes demultiplexing the packets so as to obtain the packets associated with a desired program and assembling the packets in such a way that a video decompressor can configure the data into a digital video program.

[0007] FIG. 1 illustrates a conventional transport stream processor 1. The transport stream processor includes a processor 10, a memory 12, an input/output (I/O) chip block 16, a descrambler 18, a PID filter 20, a direct memory access (DMA) engine 22, and a list 24. Also provided is host communication 14 through which data, including transports stream data, are provided to the transport stream processor.

[0008] Packets in the transport stream are received by processor 10 through host communication 14. Packets are then sent to I/O chip block 16, through which the packets are delivered to descrambler 18. Descrambler 18 performs descrambling operations on the incoming transport stream, including application of PID filter 20. PID filter 20 identifies packets having desired packet identifier information. Descrambler 18 then descrambles the information contained in the identified packets.

[0009] Once the packets have been descrambled, they are sent back to processor 10 through the I/O chip block 16. Processor 10 performs additional demultiplexing operations and other operations to prepare data for display as video programming. Memory 12 typically comprises a random access memory or a read-only memory. One function of memory 12 is to provide a code space for instructions defining the demultiplexing processing operations to be performed by processor 10.

[0010] Once the incoming packets have been filtered, descrambled, and processed, they are transported to DMA engine 22 through the I/O chip block 16. Because packets in the transport stream are not necessarily sequentially ordered, DMA engine 22 transmits packets into list 24. List 24 allows the packets to be sequenced appropriately for video decoding and image rendering operations performed in preparation for displaying the video data to the viewer.

[0011] One of the limitations of the conventional transport stream processor of FIG. 1 is that only a single transport stream may be processed at any given time. Additionally, only a single video program maybe decoded from the transport stream at any given time. To overcome these limitations, user systems may be include multiple transport processors for decoding multiple programs from a transport stream or from multiple transport streams.

[0012] FIG. 2 illustrates an architecture for processing multiple video programs. Specifically, FIG. 2 illustrates four separate transport stream processors 1a–d. Each transport stream processor 1a–d performs a unique demultiplexing operation on an incoming video transport stream. Moreover, each transport processor 1a–d is an independent system that includes all hardware necessary for processing a transport stream. While the illustrated architecture allows the system to simultaneously process multiple programs from one or more transport streams, the redundancy of architecture makes the apparatus both expensive to manufacture and inefficient in operation.

[0013] In view of the above, it is apparent that there is a need for new and improved methods and apparatus for processing a plurality of video programs from one or more transport streams. It is desirable that the method reduce redundancy of architecture and provide streamlined processing and retrieval of digital video packets from the one or more transport streams.

[0014] The present invention is directed to methods and apparatus for processing multiple transport streams by utilizing a novel processing apparatus. The processing apparatus has a transport memory unit and a transport processing circuit. The transport processing circuit includes multiple transport processor units. The processing apparatus streamlines processing and reduces the redundancy of transport processing components that have been used in conventional systems. The multiple transport processing circuits of the processing apparatus can be implemented on a single integrated circuit if desired.

[0015] The transport processor memory unit is utilized by all of the transport processor units of the transport processing circuit. The transport processor memory unit contains processing information and also maintains the hardware state of each packet identifier that the transport processor units are assigned to acquire and process. By utilizing a common transport processor memory unit, a separate memory for each transport processor unit is no longer needed. This allows for fewer system components, streamlined operation and design, and reduced cost compared with prior art systems for processing multiple transport streams, in which each transport stream processor has its own memory.

[0016] According to the invention, each transport processor unit includes a transport interface, a demultiplexing processor, and a demultiplexing DMA. The transport interface identifies packets to be acquired from the video transport stream. The demultiplexing processor performs demultiplexing processing operations on the acquired data packets. The demultiplexing DMA performs memory handling operations related to the processed data packets.

[0017] The present invention also utilizes a method of index chaining, in which indices are used to access the processing information and the hardware state of previously processed packet identifiers from the common transport processor memory unit. A unique index is provided for every packet identifier that the transport processor units acquire and process. In one embodiment, a packet identifier index representing the packet type is provided by the transport interface. The packet identifier index is used by the demultiplexing processor to access a demultiplexing context entry from the shared context storage of the transport processor memory unit. The demultiplexing context entry contains control fields for informing the demultiplexing processor operations. The demultiplexing processor provides a DMA index for the data packet. The demultiplexing DMA uses the DMA index to access memory handling information from the shared context storage of the transport processor memory unit.

[0018] One embodiment of the present invention utilizes a transport stream switch for arbitrating multiple transport streams into the transport processing circuit. The transport processing circuit can process one video program for each transport processor unit. By utilizing a transport stream switch, video transport streams from more than one source can be fed to the system. In one embodiment, six transport stream inputs are provided. Four inputs from tuner/demodulator pairs, one from an internal system source, and one from a playback DMA. In the embodiment, the transport stream switch selects which of the six transport streams will be processed and by what transport processor unit.

[0019] Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The features and advantages of the invention may be realized and obtained by means of the instruments and combinations particularly pointed out in the appended claims. These and other features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.

[0033] As discussed above, the present invention is directed to methods and apparatus for processing multiple video programs for one or more video transport streams. A set-top box or other video processing device that includes multiple transport processor units according to the invention can simultaneously decode and process multiple programs or other data included in a transport stream. For example, a set-top box having four transport processor units according to the invention can perform as many as four simultaneous operations on video data. For instance, these four simultaneous operations could include decoding two programs for a picture-in-picture display, decoding a third program for recording at the set-top box, and decoding broadcast data (electronic program guides, software encoded in a transport stream, etc.). Of course, these represent only specific examples of the wide variety of applications and functionality that is enabled by the invention. Moreover, because the multiple transport processor units can be included in a single integrated circuit and can share other hardware, the invention enables such functionality to be less expensive and available in more operating environments than would otherwise be possible.

[0034] With reference now to FIG. 3, there is shown a transport processor memory unit 40 and transport processing circuit 30 of processing apparatus 28. The transport processing memory unit 40 functions as the memory for the transport processing circuit 30. The transport processing circuit 30 processes multiple video programs from one or more processing streams.

[0035] Transport processing circuit 30 comprises a plurality of transport processor units. In the illustrated embodiment, transport processing circuit 30 includes a first transport processor unit 34a, a second transport processor unit 34b, a third transport processor unit 34c, and a fourth transport processor unit 34d. Each transport processor unit 34a–d is configured to receive an incoming video transport stream. In the illustrated embodiment, the first transport processor unit 34a is configured to receive first transport stream 26a. Second transport processor 34b is configured to receive second transport stream 26b. The third transport processor unit 34c is configured to receive a third incoming transport stream 26c. The fourth transport processor unit 34d is configured to receive fourth transport stream 26d. Transport processor units 34a–d and other processor units disclosed herein are examples of means for processing incoming transport streams.

[0036] In the illustrated embodiment, transport streams 26a–d can be multiple copies of the same incoming transport stream or, alternatively, can be distinct and unique transport streams. Where transport streams 26a–d are multiple copies of the same transport stream, each transport processor unit 34a–d performs a different demultiplexing operation on the stream, thus allowing the system to process multiple video programs from the same transport stream.

[0037] Where transport streams 26a–d are distinct and unique video transport streams, each of the transport processor units 34a–d processes a video program from the received transport stream. For example, where the system is equipped with multiple tuner/demodulator pairs, transport streams from different sources may be received by the system. These sources could include a digital broadcasting source, a digital satellite link source, or a digital/video cable source. Additionally, a digital video transport stream could be fed from an internal system source such as from a DVD optical disk read by the system. Transport streams associated with different transponders of a digital satellite system represent another situation in which the transport processor units 34a–d can process distinct transport streams.

[0038] Each of transport processor units 34a–d includes a transport interface, a demultiplexing processor, and a demultiplexing direct memory access unit (referred to herein as a “demultiplexing DMA”). For example, first transport processor unit 34a includes a first transport interface 36a, a first demultiplexing processor 38a, and a first demultiplexing DMA 39a. Transport interfaces 36a–d identify data packets to acquire from the incoming transport stream. Demultiplexing processors 38a–d perform processing operations on acquired data packets. Demultiplexing DMAs 39a–d determine where acquired data packets are to be transported. The operation of these components as data packets are acquired and processed will be described in greater detail below.

[0039] The transport processor units 34a–d utilize the common transport processor memory unit 40. By utilizing a common transport processor memory unit 40, the transport processor units 34a–d are able to streamline processing of incoming transport streams. Moreover, transport processor units 34a–d can be assembled on a single chip or integrated circuit, thereby reducing the physical footprint and expense that would be otherwise associated with multiple transport processors in a single system. Utilizing a common transport processor unit 40 also eliminates redundancy in the architecture of the processing apparatus 28, as was described with reference to FIG. 2. Transport processor memory unit 40 and other transport memory units disclosed herein are examples of means for storing information. Additional detail regarding the method by which individual transport processor units 34a–d utilize the common transport processor memory unit 40 will be provided below.

[0040] With reference now to FIG. 4, there is shown an incoming transport stream 26. Incoming transport stream 26 includes individual data packets represented by first data packet 44 and second data packet 46. It will be understood by those skilled in the art that first and second data packets 44, 46 are illustrative of any number of data packets included in a transport stream.

[0041] FIG. 4 illustrates additional detail with respect to data packet 46. Data packet 46 is representative of some or all of the data packets in the incoming transport stream. Data packet 46 comprises a header 48 and a payload 52. Header 48 contains, among other information, a packet identifier 50, such as a PID or a SCID. As discussed above, there can be approximately 20 to 40 packet identifiers within a transport stream. A stream can carry multiple programs, each being represented by a different set of packets having one or more packet identifiers. Each packet identifier operates to identify packets of a given type associated with a particular program. For example, all audio packets of a given program can be given a unique packet identifier. Packets having a particular packet identifier are interleaved in the transport stream with packets having other packet identifiers. The sequence in which the various packets are included in the transport stream varies and depends on a number of factors, including the number of programs associated with the transport stream and the allocation of bandwidth of the transport stream among the multiple programs.

[0042] The transport processor units of the present invention filter the packets in a transport stream to obtain the packets of a desired program and assemble the packets such that a decompressor can process the packets. The transport processor units of the present invention are configured to identify and process all data packets representing a particular video program. Accordingly, each incoming data packet in a transport stream is either accepted or rejected based on the packet identifier associated with the data packet. As will be appreciated by those skilled in the art, details regarding header information, payload information, and packet identifier depend largely on the digital video format in which the packets are encoded.

[0043] With reference now to FIG. 5, there is shown one embodiment of a processing apparatus that performs the operations of the invention. In the illustrated embodiment, processing apparatus 28 includes a transport processing circuit 30, a transport processing memory unit 40, a transport stream switch 80, and a DMA switch 90. In the illustrated embodiment, processing apparatus 28 is configured with six transport stream inputs. One of the incoming transport streams, namely, incoming transport stream 82, includes data provided by a playback DMA 100, which is described in greater detail below. A second incoming transport stream 26 is generated by a component or source external to the processing apparatus 28, but internal to the set-top box or other user system in which processing apparatus 28 is included. An example of a transport stream from a component or source external to the processing apparatus 28 but internal to the user system is a 1394 fire wire implementation or similar internal video feeds to the processing apparatus 28. This provides connectivity in the chip instead of feeding through the system board. The remaining four transport streams 26b–e in the illustrated embodiment represent external transport streams fed through four individual tuner/demodulator pairs.

[0044] As will be appreciated by those skilled in the art, a variety of embodiments arranged in a variety of configuration are possible without departing from the spirit or scope of the invention. For example, different numbers and arrangements of transport streams and transport stream sources can be implemented. Additionally transport streams can originate from sources other than tuner/demodulator pairs, external system sources, and playback DMA. It will be appreciated that transport streams 26b–e can represent four copies of the same transport stream or distinct and unique transport streams from alternative sources. Examples of such alternative sources could include a satellite link, a digital/video cable, broadcast media, or any other source through which a transport stream can be transmitted to the system.

[0045] In the illustrated embodiment, transport streams are passed through a transport switch 180. Because each transport processor unit can process a single video program from an incoming transport stream, the number of transport streams that may be processed simultaneously is generally limited to the number of transport processor units contained in the transport processing circuit 30. In the illustrated embodiment, the number of incoming transport streams exceeds the number of transport processor units. Thus, only four of the six incoming transport streams are processed at any time. Software determines which transport streams are passed to the various transport processor units. Transport stream switch 80 allows only the requisite number of incoming transport streams to be passed to the transport processing circuit 30.

[0046] As described above, the transport processing circuit 30 includes four transport processor units in the illustrated embodiment. As described above, each transport processor unit includes a transport interface, a demultiplexing processor, and a demultiplexing DMA. The transport interface, the demultiplexing processor, and the demultiplexing DMA all perform unique functions on the incoming transport streams. The transport interface identifies the packets that are to be obtained from the transport stream. The demultiplexing processor determines the processing that is to be performed on the acquired packets. The demultiplexing DMA determines where the data packets are to be stored.

[0047] Each of the four transport processor units performs a demultiplexing operation on an incoming transport stream. In performing demultiplexing operations, the transport processor units utilize a common transport processor memory unit 40. In the illustrated embodiment, transport processor memory unit 40 comprises shared context storage 60 and a shared filter storage 70. Shared context storage 60 is associated with a shared context storage RAM 62, while shared filter storage 70 is associated with a shared filter storage RAM 72. Transport processor memory unit 40 is one example of means for holding information.

[0048] The shared context storage 60 provides access to demultiplexing (demux) context entries. Demux context entries maintain the hardware state of each packet identifier on which the transport processor units are assigned to work. For example, while a given transport processor unit is working on an audio packet, for example, the state of the previously processed video and program packets are maintained in the demultiplexing context. The shared storage RAM 62 provides the necessary memory for maintaining shared context storage 60. The context storage functionality of the invention is described in greater detail below in reference to FIG. 8. Shared filter storage 70 contains section filters for processing acquired data packets. Shared filter storage RAM 72 provides the necessary memory for maintaining section filters.

[0049] DMA switch 90 is coupled to transport processing circuit 30. Processed data packets, which are being transported as outgoing DMA, are transported through DMA switch 90. Outgoing DMA is transported across a common PCI system bus 94. Accordingly, only a single transport processor unit may transport outgoing DMA across system bus 94 at any given time. DMA switch 90 arbitrates between individual transport processor units, ensuring that only a single transport processor unit is transporting outgoing DMA at any given time. The DMA switch 90 ensures that the data portion of each data packet has been transported in its entirety. Once the data portion has been sent in its entirety, an error status packet can be sent to the software module if an error status packet has been generated. Finally, the DMA switch 90 ensures that, if an interrupt is appropriate, the interrupt is given to the software module.

[0050] FIG. 5 further illustrates the outgoing packets from the transport processor units and the manner in which the outgoing packets are arbitrated by DMA switch 90. As shown in FIG. 5, transport processor units 34a–d transmit outgoing packet DMA 92a–d, respectively. Outgoing DMA data may be transmitted to one of at least three places: 1) to the system bus 94; 2) to a smart card interface 96; or 3) to the playback DMA 100. In one embodiment, DMA data transported via system bus 94 is sent primarily to conventional system buffers used for transport processing. In an alternative embodiment, DMA data sent via system bus 94 is sent to specifically designed ring buffers configured to accommodate packet data from processed transport streams. In yet another embodiment, DMA data sent via system bus 94 is sent to ping-pong buffers configured to accommodate data from processed transport streams.

[0051] The smart card interface 96 can retrieve encryption keys needed for additional operations to be performed outgoing DMA. Such operations, which may include conditional access to video programming as defined by the smart card, are independent from and in addition to the operations performed by the transport processing circuit 30.

[0052] Outgoing DMA data can also be transmitted to the playback DMA unit 100. Playback DMA interface 102 provides connectivity between DMA switch 90 and playback DMA unit 100 and allows outgoing DMA to be sent to playback DMA unit 100. Outgoing DMA data transmitted to playback DMA 100 may be transmitted to multiple locations from the playback DMA 100. In the illustrated embodiment, playback DMA unit 100 can transmit outgoing DMA data to transport output 104 or back to the transport stream switch 80. Transport output 104 allows outgoing DMA data to be sent to a location external to processing apparatus 28. Sending outgoing DMA data back to transport stream switch 80 allows the system to send outgoing DMA back through the transport processor unit.

[0053] With reference now to FIG. 6, there is shown a transport interface 36. Transport interface 36 is representative of transport interfaces 36a–d. Transport interface 36 receives data packets from the incoming transport stream 26. The transport interface 36 identifies data packets to acquire from the incoming transport stream 26 based on the packet identifiers associated with the desired program that is to be decoded.

[0054] The transport interface includes a single RAM, which is divided into two sections, the top being a first-in first-out buffer (fifo) and the bottom being a packet identifier filter. When a packet is received into the transport interface it is first received into the fifo. In the fifo, a time stamp is generated in the first byte of every packet. The time stamp indicates the point in time in which the packet was received. By indicating the point in time in which the packet was received, the system is capable of performing clock recovery operations on acquired data packets. Clock recovery is necessary for proper playback of many digital formats, such as DVD.

[0055] As illustrated in FIG. 6, the packet identifier for each data packet of the incoming transport stream 26 is compared to a filter table 110. Filter table 110 includes filter table entries 112a, 112b, 112c . . . 112n. Each filter table entry represents a packet identifier of a data packet to be acquired. The packet identifier for each incoming data packet is compared to the filter table entries. If a table entry matches the packet identifier, the transport interface 36 associates the packet identifier index associated with the table entry with the data packet and passes the index to the demultiplexing processor. If the packet identifier for an incoming data packet does not match a table entry, the packet is discarded.

[0056] Thus, each packet identifier index represents a given packet identifier. This allows the transport interface 36 to identify packets to be acquired. In one embodiment, the packet identifier index comprises a 7 bit code. Because packet identifiers are typically at least 13 bits, the packet identifier index allows for streamlined processing of data packets. This is particularly useful in index chaining which will be discussed in greater detail below.

[0057] With reference now to FIG. 7, there is shown a flow diagram illustrating the logic functions performed by transport interface 36. In step 122, a packet is received into the transport interface. Once the packet is received into the transport interface, a time stamp is generated in step 124. The packet identifier is then identified in step 126. Once the packet identifier is identified, the packet identifier is compared with table entries of the filter table in step 128. The transport interface then determines whether the packet identifier is located in the filter table according to decision block 130. In the event that the packet identifier is not located in the filter table, the packet is discarded in step 132. If, however, the packet identifier is located in the filter table, a packet identifier index associated with the table entry is identified in step 134. Once the index is identified, the index is associated with the packet in step 136. The transport interface then sends the packet to the demultiplexing processor in step 138.

[0058] Thus, the transport interface performs two primary functions: 1) generating time stamps for clock recovery necessary for proper playback of the digital video program; and 2) identifying data packets to acquire. According to one embodiment of the invention, the packet identifier filter is either a 13 or 12-bit filter, depending on whether it is filtering PIDs or SCIDs, for identifying packet identifiers that system software has determined represent packet identifiers of packets to be processed and stored in memory. Transport interface 36 and other transport interfaces disclosed herein are examples of means for identifying data packets to acquire from an incoming transport stream.

[0059] With reference now to FIG. 8, there is shown demultiplexing processor 38 and shared context storage 60. Demultiplexing processor 38 filters packet data, controls descrambling operations, and performs other data processing. Demultiplexing processor 38 and other demultiplexing processors disclosed herein are examples of means for performing processing operations.

[0060] One of the complexities of demultiplexing processor 38 is that it is assigned to process packets from several different packet identifiers, although the demultiplexing processor can only process one packet at a time. An important component of the processing apparatus 28 that allows the demultiplexing processor 38 to process packets having several different packet identifiers is the shared context storage 60. Shared context storage 60 maintains the hardware state for each packet identifier on which the demultiplexing processor 38 is assigned to work. The hardware state for each packet identifier is maintained in a demultiplexing (demux) context entry.

[0061] The demux context entry contains both the general packet processing information and specific status information related to recently processed packets for each packet identifier on which it is assigned to work. For example, if the demultiplexing processor 38 is processing an audio packet, the processing instructions and the state of the previously processed video and program packets are maintained in the demux context entries.

[0062] The demux context allows the demultiplexing processor to determine where it left off the last time it was processing a given type of packet. In one embodiment of the invention, each demux context entry is 32 bits wide by five words deep. As will be appreciated by those skilled in the art, demux context entries may be embodied in a variety of configurations without departing from the scope or spirit of the present invention. In this embodiment, each demux context entry contains fields that instruct the demultiplexing processor regarding descrambling control, demultiplexing filter selection, storage format, DMA channel selection, and error detection.

[0063] When a packet identifier index is sent to demultiplexing processor 38, the demultiplexing processor 38 compares the packet identifier index 140 to a demux context index 142. The demux context index 142 includes demux index entries 144a, 144b . . . 144n. The packet identifier index 140 points to a demux index entry 144n. The demux index entry 144n is used to calculate the position of the corresponding demux context entry 146 in the shared context storage RAM. The hardware of the demultiplexing processor 38 reads the corresponding demux context entry 146 into a holding register. The demultiplexing processor 38 may then perform operations on the acquired data packet 46 based on information contained in the demux context entry 146.

[0064] The demux context entry 146 contains demux context control field 145a, 145b . . . 145n. The demux context control fields instruct the demultiplexing processor 38 on various processing operations including descrambling control, demultiplexing filter selection, storage format, DMA channel selection, and other relevant demultiplexing processor operations. For example, when a packet is received, descrambling control determines whether the incoming packet requires any descrambling. If descrambling is required, the appropriate descrambling key index is located and the data is sent to a descrambler before additional processing operations are performed.

[0065] With reference now to FIG. 9, there is shown a flow diagram illustrating the logic operations performed by the demultiplexing processor 38. In this method, the demultiplexing processor receives a data packet in step 152. The packet identifier index is then identified in step 154. Once the packet identifier index is identified, step 156 is performed, in which a demux context entry is accessed. The demultiplexing processor analyzes payload data of the packet in light of demux context control fields in step 158.

[0066] The method then proceeds to decision block 160, in which it is determined whether descrambling of the data associated with the packet is needed. In the event that descrambling is needed, a descrambling key index is located according to step 162. Once the decsrambling key index is located, the packet is sent to a descrambler in step 164 and the data is descrambled in step 166.

[0067] If, however, descrambling is not needed, the method proceeds to step 170, in which a filter select field is identified. Once a filter select field is identified, the corresponding filter in the shared filter storage is accessed in step 172. Next, in step 174, the demultiplexing processor applies the filter from the shared filter storage to the packet data. The selected storage format is identified in step 176, after which the demultiplexing processor saves the filtered data in the selected storage format in step 178. The demultiplexing processor then locates a DMA channel on which it can write according to step 180. Once the DMA channel has been located, step 182 is performed, in which a DMA index is associated with the packet. Finally, the packet is sent to the demultiplexing DMA in step 184.

[0068] As will be appreciated by those skilled in the art, method 150 and the corresponding processing operations are merely representative of operations that can be performed on data packets of a incoming transport stream. Various processing operations may be performed by the demultiplexing processor, or by other hardware of the transport processor unit, without departing from the spirit and scope of the present invention.

[0069] With reference now to FIG. 10, there is shown the method by which a section filter from the shared filter storage may be accessed utilizing the demultiplexing context entry 144. As described with reference to FIG. 9, a packet identifier index is used to locate a demux context entry 146 by means of a demux index entry 144n. The demux context entry 146 includes demux context control fields. One of the demux context control fields comprises a section filter select field 190.

[0070] Selection filter select field 190 provides a pointer to a section filter 192 of shared filter storage 70. According to one embodiment of the invention, the section filter select field 190 is a 32-bit value that directly corresponds with one of the 32 sections filters in the shared filter storage. Each filter, including section filter 192, includes a mask that forces all bits in the data packet payload to known values. The match is then used as a bit-wide comparison against the mask value. If the bits satisfy the mask filter, the filter passes and the section is stored.

[0071] Shared filter storage 70 stores section filters for performing filter operations on data packets acquired by the demultiplexing processor. Because the shared context storage and the shared filter storage are contained in a common memory utilized by each of the transport processor units, information relating to processing is centralized. Centralizing information related to processing streamlines processing of data packets and eliminates redundant architecture present in other transport processing systems.

[0072] With reference now to FIG. 11, there is shown a method whereby the demultiplexing DMA 39 accesses DMA information from a DMA context entry 210 utilizing a DMA index 200. When a DMA index 200 is received from demultiplexing processor 38, the demultiplexing DMA utilizes the DMA index 200 to access memory handling information. The DMA index 200 points to a base register. The base register points to a DMA context entry 210 stored in the shared context storage.

[0073] DMA context entry 210 includes DMA control fields. DMA context entry control fields include DMA address information 212, DMA length information 214, interruption information 216, and buffer control information 218. DMA address information supplies the address of the DMA buffer to which the processed packet data is to be transferred. The DMA length information 214 supplies the length of the DMA buffer in which the packet information is to be transferred. Interrupt information 216 and buffer control information 218 are provided so that interrupts can be generated for packets that need service in a timely fashion.

[0074] As illustrated in FIG. 11, demultiplexing DMA 39 is configured to read information from DMA control fields 212, 214, 216, 218. Demultiplexing DMA 39 includes a DMA RAM 219, which operates to store incoming packet information. When sufficient packet information accumulates to constitute outgoing DMA, the demultiplexing DMA 39 communicates with the DMA switch 90 to transfer the packet information to the appropriate buffer. Demultiplexing DMA 39 and other demultiplexing DMAs disclosed herein are examples of means for determining where acquired data packets are to be transported.

[0075] With reference now to FIG. 12, there is shown the arbitration module 220 of the present invention. Arbitration module 220 is a component of the DMA switch 90. Arbitration module 220 arbitrates transfer request from the transport processor units. In the event that two or more of the demultiplexing DMAs 39a–d simultaneously communicate with DMA switch 90 in an effort to transfer packet information to DMA buffers, the arbitration module 220 arbitrates transfer requests from the transfer processors. Arbitration module 220 allocates access to the system bus 94 by determining which demultiplexing DMA will send data over the system bus 94 at any given time. DMA switch 90 acquires the system bus through the system bus interface and allows the data to be sent to system memory (i.e. DMA buffer). Thus, outgoing packet data from the first transport processor unit 92a, outgoing packet data from the second processor unit 92b, outgoing packet data from the third transport processor 92c, and outgoing packet data from the fourth transport processor unit 92d maybe sent over the system bus to the appropriate DMA buffer in an organized and coordinated fashion.

[0076] Once the packets have been completely processed, the hardware portions of the demux context and DMA contexts are updated. The contexts are then sent back to the shared context storage to be reinitialized when a packet of the corresponding packet identifier is again detected. This is accomplished by modifying the demux context entries in the holding registers with new data and writing the modified entries back to the common memory.

[0077] While the use of indices was described with reference to the functioning of the transport interface, demultiplexing processor, and the demultiplexing DMA, a more succinct explanation focusing solely on index chaining will now be explained. Index chaining facilitates the use of a common storage memory 40 by the plurality of transport processor units. The use of a common storage memory 40 simplifies processing of incoming data packets and reduces redundant architecture that would otherwise be required in the processing apparatus 28.

[0078] Index chaining utilizes an index, or series of associated indices, to access packet processing information from the common storage memory. For example, in one embodiment a packet identifier index is associated with each packet acquired by the transport interface. The index is used by the demultiplexing processor to access a demux context entry from the shared context storage. Utilizing information stored in the shared demux context entry, a demultiplexing DMA index is associated with the data packet. The DMA index is used by the demultiplexing DMA to access a DMA context entry from in the shared context storage. Thus, in this embodiment, index chaining allows demux context entries stored in the shared context storage to be accessed by each of the demultiplexing processors and each of the demultiplexing DMAs of the transport processor units. The context entries allow the demultiplexing processors to determine where they let off the last time they were working on a given type of packet. The context entries also allow the demultiplexing DMAs to identify necessary memory handling information, such as the DMA address, DMA length, and the corresponding interrupt information for data packets that are being processed.

[0079] The use of index chaining also enables the system to delay playback and/or recording of a video program received as part of an incoming video stream. In order to do so, when the incoming video stream is first received, the transport stream processor identifies all PIDs associated with the video program and acquires the packets. A time stamp is prepended to the packets. The packets of the video program are then associated with a unique index. For example, all video packets can be labeled as PID 1, while all audio packets can be labeled as PID 2. Each unique index is associated with a single DMA context which points to where the processed data packet is to be sent in system memory. Because the demultiplexing DMA operates independently of the demultiplexing processor, the transport stream processor can DMA the packets to memory without first processing the packets.

[0080] The system can then send the acquired video program back to the transport stream processor at a desired point in time for processing and playback. Since the packets have an associated index and the index points to the location of the unprocessed packets in system memory, the system can locate all the packets of the acquired video program. The time stamps prepended to the packets are used to reconstruct the program. The program can then be sent to the transport stream processor for processing and playback as if it were being received for the first time. Once the program packets are processed, the program can be played or recorded as desired by the user. Thus, the transport stream processor allows the processing and playback of a video program to be delayed without first processing the data packets associated with the video program. In one embodiment, the video program is reconstructed as a video stream before being sent to the transport stream processor for processing, playback, and/or recording.

[0081] The use of the index chaining and corresponding use of indices to access the common storage memory may be embodied in a variety of configurations without departing the scope and spirit of present invention. While in the above referenced embodiment, unique indices are provided by each of the sub-components of the transport processor units, one skilled in the art may appreciate that a single packet identifier index, even the packet identifier itself, can function as the index to access information from the common transport processor memory unit 40. In view of the description of the invention included herein, numerous additional embodiments of variations of the discussed embodiments the present invention will be apparent to one of ordinary skilled in the art. As will be understood by those skilled in the art such embodiments do not depart from the scope or spirit of the present invention.

[0082] The embodiments of the present invention may comprise a special purpose or general purpose computer including various computer hardware, as discussed in greater detail below. Set top boxes that enhance the capabilities of conventional televisions represent an example of a special purpose computer. The embodiments may further comprise multiple computers linked in a networked environment.

[0083] Embodiments within the scope of the present invention also include computer-readable media for carrying or having computer-executable instructions or data structures stored thereon. Such computer-readable media can be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise physical storage media such as RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code means in the form of computer-executable instructions or data structures and that can be accessed by a general purpose or special purpose computer. When information is transferred or provided over a network or another communications connection (either hardwired, wireless, or a combination of hardwired or wireless) to a computer, the computer properly views the connection as a computer-readable medium. Thus, such a connection is also properly termed a computer-readable medium. Combinations of the above should also be included within the scope of computer-readable media. Computer-executable instructions comprise, for example, instructions and data which cause a general purpose computer, special purpose computer, or special purpose processing device to perform a certain function or group of functions.

[0084] The present invention maybe embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.