Semiconductor light emitting device capable of suppressing silver migration of reflection film made of silver

[0001] This application is based on and claims priority of Japanese Patent Application No. 2004-095217 filed on Mar. 29, 2004, the entire contents of which are incorporated herein by reference.

[0002] A) Field of the Invention

[0003] The present invention relates to a semiconductor light emitting device, and more particularly to a semiconductor light emitting device which uses nitride semiconductor and has positive and negative electrodes disposed on the same side of a substrate.

[0004] B) Description of the Related Art

[0005] FIG. 15A is a cross sectional view of a semiconductor light emitting device disclosed in Japanese Patent Laid-open Publication No. 2003-224297. On a sapphire substrate 200, a buffer layer 201 is formed. On the buffer layer 201, an n-type contact layer 202 of n-type GaN, an n-type clad layer 203 of n-type AlGaN, a light emitting or luminous layer 204 of InGaN, a p-type clad layer 205 of p-type AlGaN and a p-type contact layer 206 of p-type GaN are stacked in this order. In a partial region, the layers from the p-type contact layer 206 to the surface layer of the n-type contact layer 202 are etched to expose a partial area of the n-type contact layer 202.

[0006] A p-side ohmic electrode 207 is formed on the p-type contact layer 206 and an n-side ohmic electrode 208 is formed on the exposed surface of the n-type contact layer 202. The lamination structure of these layers is covered with a translucent insulating film 210. Openings 210a and 210b are formed through the insulating film 210 to expose partial surfaces of the n-side ohmic electrode 208 and p-side ohmic electrodes 207, respectively.

[0007] A reflection film 211 is formed on the insulating film 210, covering the p-side ohmic electrode 207. A p-side pad 213 is formed on a partial surface of the reflective film 211, and an n-side pad 212 is formed on the n-side ohmic electrode 208.

[0008] The reflection film 211 is made of Al, Ag or Rh and reflects light radiated in the luminous layer 204 toward the substrate 200 side. Light passes through the substrate 200 to be output to an external. In order to improve a light output efficiency, it is desired to increase a reflectance of the reflection film 211. Ag has a very high reflectance in the range from ultraviolet light to visual light. Ag is, however, the metal likely to evolve electrochemical migration. According to “High Reliability Micro Soldering Techniques” by Tadashi TAKEMOTO and Ryouhei SATO (Kogyou Chousakai, Publishing, Co., Ltd), the Ag migration evolution mechanism is described as in the following.

[0009] As an electric field is applied under the existence of moisture, Ag is dissolved at the anode and hydrogen (H₂) is generated at the cathode. Ag⁺ ions and OH⁻ ions react near the anode and silver hydroxide AgOH is formed. Chemically unstable silver hydroxide AgOH is decomposed and colloidal silver oxide Ag₂O is formed. Silver oxide further reacts to form Ag⁺ ions. These reactions are repeated so that Ag₂O and Ag⁺ ions move to the cathode, Ag is precipitated and silver grows on the anode dendritically.

[0010] As silver migration evolves, silver grown dendritically short-circuits the anode and cathode and leak current increases. Inventions relating to suppressing silver migration are disclosed in Japanese Patent Laid-open Publications Nos. 2003-168823 and HEI-11-220171.

[0011] FIG. 15B is a cross sectional view of a semiconductor light emitting device disclosed in Japanese Patent Laid-open Publication No. 2003-168823. On a sapphire substrate 220, an AIN buffer layer 221, an n-type GaN layer 222, an InGaN luminous layer 223 and a p-type GaN layer 224 are stacked in this order. The p-type GaN layer 224 and luminous layer 223 are partially etched to expose a partial area of the n-type GaN layer 222. On the surface of the p-type GaN layer, an Ag layer 225 is formed being covered with a silicon oxide film 227.

[0012] A via hole is formed through the silicon oxide film 227 to expose a partial upper surface of the Ag layer 225. An Au layer 228 is formed on the silicon oxide film 227. The Au layer 228 is connected to the Ag layer 225 via the via hole formed through the silicon oxide film 227.

[0013] On the exposed surface of the n-type GaN layer 222, an n-side ohmic electrode 226 is formed which has a lamination structure of a V layer and an Al layer. Since the Ag layer 225 is covered with the silicon oxide film 227, Ag migration can be suppressed.

[0014] FIG. 15C is a cross sectional view of a semiconductor light emitting device disclosed in Japanese Patent Laid-open Publication No. HEI-11-220171. On a sapphire substrate 230, an AIN buffer layer 231, an n-type GaN layer 232, an n-type GaN clad layer 233, a luminous layer 234, a p-type GaN clad layer 235 and a p-type GaN contact layer 236 are stacked in this order. The lamination structure from the p-type GaN contact layer 236 to n-type GaN clad layer 233 is partially etched to expose a partial area of the n-type GaN layer 232.

[0015] An Ag layer 237 is formed on a partial surface of the p-type GaN contact layer 236. The Ag layer 237 is covered with a V layer 238 and an Al layer 239 so that Ag migration can be suppressed.

[0016] As disclosed in the above-described Japanese Patent Laid-open Publication No. 2003-168823 and Japanese Patent Laid-open Publication No. HEI-11-220171, Ag migration can be suppressed by covering the Ag layer used as the reflection film and electrode with an insulating film or another metal film. However, this migration suppression effect is not sufficient. It is desired to provide a semiconductor light emitting device capable of effectively suppress Ag migration.

[0017] An object of this invention is to provide a semiconductor light emitting device capable of suppressing migration and improving reliability although it uses the metal likely to evolve migration.

[0018] According to one aspect of the present invention, there is provided a semiconductor light emitting device comprising: a luminous lamination structure including a first layer made of n-type nitride semiconductor and a second layer made of p-type nitride semiconductor and disposed over the first layer wherein a luminous region is defined between the first and second layers and the second layer is removed to expose the first layer in a first area which is a partial surface of the first layer; a p-side electrode disposed on a surface of the second layer and electrically connected to the second layer; an insulating film covering the p-side electrode; an n-side electrode electrically connected to the first layer in the first area; and a reflection film disposed on the insulating film, extending to the n-side electrode, electrically connected to the n-side electrode, and made of silver containing alloy or silver.

[0019] The reflection film may be made in an electrically floating state.

[0020] The reflection film is connected to the n-side electrode, i.e., cathode. It is therefore possible to suppress ionization of metal constituting the reflection film and suppress the generation of migration.

[0041] FIG. 1A is a cross sectional view of a semiconductor light emitting device according to the first embodiment, and FIG. 1B is a plan view of the device shown in FIG. 1A. A cross sectional view taken along one-dot chain line A1—A1 shown in FIG. 1B corresponds to FIG. 1A. On an underlying substrate 1 made of sapphire, an initial nucleus forming layer 2, an n-type contact layer 3, an n-type clad layer 4, a luminous layer 5, a p-type clad layer 6, a p-type contact layer 7 are stacked in this order. These layers are made of nitride compound semiconductor such as In_xAl_yGa_zN (x+y+z=1).

[0042] In a first area 25 of a partial substrate in-plane, the layers from the p-type contact layer 7 to a surface layer of the n-type contact layer 3 are etched to partially expose the n-type contact layer 3.

[0043] A p-side ohmic electrode 10 is formed on the p-type contact layer 7. The p-side ohmic electrode 10 is made of platinum (Pt) and has a thickness of about 5 nm. An n-side ohmic electrode 11 is formed on the surface of the n-type contact layer 3 in the first area 25. The n-side ohmic electrode 11 has a two-layer structure of an Al layer having a thickness of about 3 nm and a rhodium (Rh) layer having a thickness of about 100 nm. The p-side ohmic electrode 10 and n-side ohmic electrode 11 are in ohmic contact with the p-type contact layer 7 and n-type contact layer 3, respectively.

[0044] Adhesion layers 60 and 61 made of Ti, Ni, W, Mo or the like and each having a thickness of 0.3 nm to 3 nm are formed on the p-side ohmic electrode 10 and n-side ohmic electrode 11, respectively. The adhesion layers can improve adhesion to an insulating film 15 deposited on the adhesion layers.

[0045] The insulating film 15 is formed on the substrate, covering the p-side ohmic electrode 10 and n-side ohmic electrode 11. For example, the insulating film 15 is made of silicon oxide and has a thickness of about 300 nm. Openings 15a and 15b are formed through the insulating film 15. A partial surface of the p-side ohmic electrode 10 is exposed on the bottom of the opening 15a, and a partial surface of the n-side ohmic electrode 11 is exposed on the bottom of the opening 15b.

[0046] A reflection film 16 is formed on the insulating film 15. The reflection film 16 extends from the area superposed upon the p-side ohmic electrode 10 to the upper surface of the n-side ohmic electrode 11 in the first area 25, and is electrically connected to the n-side ohmic electrode 11 exposed on the bottom of the opening 15b. The reflection film 16 is made of silver (Ag) and has a thickness of about 200 nm.

[0047] An adhesion layer (not shown) made of Ti, Ni, Al, W, Mo or the like and having a thickness of 0.3 nm to 3 nm is inserted between the insulating film 15 and reflection film 16. This adhesion layer improves adhesion properties between the insulating film 15 and reflection film 16. A similar adhesion layer 62 is formed also on the reflection film 16. This adhesion layer 62 improves adhesion to a protective film 17 to be formed thereon. The upper adhesion layer 62 has a thickness of, for example, 10 nm.

[0048] A p-side pad electrode 20 is formed on the p-side ohmic electrode 10 exposed on the bottom of the opening 15a, and an n-side pad electrode 21 is formed on the n-side ohmic electrode 11 exposed on the bottom of the opening 15b. The p-side pad electrode 20 and n-side pad electrode 21 have a multi-layer structure of Ti/Pt/Au/(Pt/Au)_n where n is the number of repetitions of two layers of a Pt layer and an Au layer. A thickness of the lowermost Ti layer is, for example, 3 nm and a thickness of each of the Pt layer and Au layer is, for example, 100 nm. The number of repetitions is, for example, 2. The number n of repetitions is preferably 1 to 5 from the viewpoint of film forming works and an amount of material to be used. If flip chip bonding is to be performed, it is preferable to set a thickness of the third Au layer of the n-side pad electrode 21 as measured from the substrate side to 100 nm to 1000 nm to make the upper surface height of the n-side pad electrode 21 be flush with the upper surface height of the p-side pad electrode 20.

[0049] An adhesion layer (not shown) made of Ti, Ni, Al, W, Mo or the like and having a thickness of 0.3 nm to 3 nm is formed on the p-side pad electrode 20 and n-side pad electrode 21. This adhesion layer improves adhesion to a protective film 17 to be deposited thereon.

[0050] The protective film 17 is formed covering the reflection film 16 and pad electrodes 20 and 21. The protective film 17 is made of silicon oxide and has a thickness of 100 nm to 300 nm, preferably about 200 nm. Openings 17a and 17b are formed through the protective film 17. The upper surfaces of the p-side pad electrode 20 and n-side pad electrode 21 are exposed on the bottoms of the openings 17a and 17b, respectively.

[0051] As shown in FIG. 1B, the plan shape of one semiconductor light emitting device is, for example, a square having one side length of 300 μm. The first area 25 contains one vertex of the square and is constituted of an area near this vertex. For example, the shape of the first area is a sector shape having a center angle of 90° around one vertex. The p-side ohmic electrode 10 is disposed in an area excluding the first area 25 and occupies most of the surface of the semiconductor light emitting device. The p-side pad electrode 20 is disposed in an area near the diagonally opposite vertex to the vertex contained in the first area 25. The reflection film 16 occupies most of the surface of the semiconductor light emitting device excluding the area where the p-side pad electrode 20 is disposed.

[0052] Next, description will be made on a method of manufacturing the semiconductor light emitting device of the first embodiment. Each of the layers from the initial nucleus forming layer 2 to the p-type contact layer 7 formed on the underlying substrate 1 made of sapphire is formed, for example, metal organic vapor phase epitaxial (MOVPE) growth, molecular beam epitaxial (MBE) growth or the like. After the p-type contact layer 7 is formed, the surface of the substrate is washed, and the p-side ohmic electrode 10 and the adhesion layer thereon are formed by electron beam vacuum deposition and lift-off.

[0053] By using as a mask a resist pattern having an opening corresponding to the first area 25, etching is performed down to the surface layer region of the n-type contact layer 3 by reactive ion etching to partially expose the n-type contact layer 3. After etching, the resist pattern used as the mask is removed. On the exposed surface of the n-type contact layer 3, the n-side ohmic electrode 11 is formed by electron beam vacuum deposition and lift-off.

[0054] The p-side ohmic electrode 10 and n-side ohmic electrode 11 may be formed after the surface of the n-type contact layer 3 is partially exposed.

[0055] The insulating film 15 is formed by sputtering. The openings 15a and 15b are formed through the insulating film 15. The openings 15a and 15b may be formed by lift-off. The lower adhesion layer, reflection film 16 and upper adhesion layer are formed by electron beam vacuum deposition and lift-off. In order not to short-circuit the reflection film 16 and the p-side ohmic electrode 10 exposed on the bottom of the opening 15a, the boundary of the reflection film 16 is retracted from the boundary of the opening 15a by 1 μm or longer, preferably by about 5 μm. In order to electrically connect the n-side ohmic electrode 11 exposed on the bottom of the opening 15b, an overlap width of about 3 μm to 5 μm is retained between the reflection film 16 and opening 15b. In this manner, the reflection film 16 is not connected to the p-side ohmic electrode 10, but is electrically connected to the n-side ohmic electrode 11.

[0056] The p-side pad electrode 20, n-side pad electrode 21 and adhesion layers thereon are formed by electron beam vacuum deposition and lift-off. The p-side pad electrode 20 is preferably formed in such a manner that the outer periphery thereof is disposed slightly inner than the boundary of the opening 15a. If the p-side pad electrode 20 does not contact the reflection film 16, the area near the outer periphery of the p-side pad electrode 20 may overlap the insulating film 15.

[0057] The protective film 17 is formed by sputtering. Thereafter, the openings 17a and 17b are formed through the protective film 17. The openings 17a and 17b may be formed by lift-off. The surface of the p-side pad electrode 20 is exposed on the bottom of the opening 17a, and the n-side pad electrode 21 is exposed on the bottom of the opening 17b.

[0058] The bottom surface of the underlying substrate 1 is ground and polished to thin the thickness of the underlying substrate 1 μm to about 100 μm. The thickness of the underlying substrate 1 may be 60 μm to 210 μm. Scribing and breaking are performed to separate the wafer into light emitting devices. Each separated light emitting device can be used in various application fields. For example, the separated light emitting device is flip-chip-bonded to a sub-mount substrate. The underlying substrate 1 may be adhered to a light guiding plate by transparent adhesive, and the p-side pad electrode 20 and n-side pad electrode 21 are connected to wiring lines formed on the light guiding plate by gold wires.

[0059] As a forward voltage is applied to the lamination structure constituted of the n-type clad layer 4, luminous layer 5 and p-type clad layer 6, light is radiated in the luminous layer 5. Light radiated in the luminous layer 5 passes through the underlying substrate 1 and is irradiated to an external. Light radiated in the luminous layer 5 and propagated toward the p-type clad layer 6 passes through the p-side ohmic electrode 10 and insulating film 15, is reflected by the reflection film 16 toward the underlying substrate 1, passes through the underlying substrate 1 and is irradiated to the external.

[0060] Ag migration may be ascribed to that Ag is dissolved at the anode when an electric field is applied under the existence of moisture. In the above-described first embodiment, since the reflection film 16 made of Ag is connected to the cathode (n-side ohmic electrode 11), Ag will not be dissolved so that Ag migration can be suppressed.

[0061] FIG. 2 shows the result of a lifetime evaluation test of the semiconductor light emitting device of the first embodiment. The abscissa represents a lapse time in the unit of “hour” and the ordinate represents a luminous output indicated by a relative scale. As a comparative example, the result of the lifetime evaluation test of a semiconductor light emitting device is shown, the device having the structure that the p-side ohmic electrode 10 shown in FIG. 1A is made of Ag and used as the reflection film. A black rectangle symbol in FIG. 2 shows a change with time of the luminous output of the semiconductor light emitting device of the first embodiment, and a black circle symbol shows a change with time of the luminous output of the semiconductor light emitting device of the comparative example. The lifetime evaluation test measured a luminous output in the atmospheric air while the semiconductor light emitting device is flip-chip-bonded to a sub-mount substrate. The luminescence wavelength was 405 nm.

[0062] The luminous output of the semiconductor light emitting device of the comparative example abruptly lowers in several tens hours, whereas the luminous output of the semiconductor light emitting device of the embodiment hardly lowers even after the lapse of 1000 hours. By connecting the reflection film 16 made of Ag to the cathode, the semiconductor light emitting device can have a long lifetime.

[0063] In the above-described first embodiment, although the p-side ohmic electrode 10 is made of Pt, it may be made of a different conductive material which allows light in the luminescence wavelength range of the luminous layer 5 to transmit and can have an ohmic contact with the p-side contact layer 7. Such materials may be rhodium (Rh), palladium (Pd) and the like. A two-layer structure of a Pt layer and an Rh layer or a two-layer structure of an Ni layer and an Au layer may also be adopted. If a two-layer structure of an Ni layer and an Au layer is used, an annealing process is required to be performed after the layers are formed in order to obtain an ohmic contact. A translucent oxide film made of oxide of Au and Ni may be used. In this case, after the layer is formed, an annealing process in an oxidizing atmosphere is required to be performed.

[0064] In the above-described first embodiment, although the n-side ohmic electrode 11 has the two-layer structure of an Al layer and an Rh layer (Al/Rh structure), a different structure capable of obtaining an ohmic contact with the n-side contact layer 3 may be used. For example, usable structures include an Al/Pt structure, an Al/Ir structure, an Al/Pd structure, a Ti/Al structure and a V/Al structure. If the Ti/Al structure or V/Al structure is adopted, an annealing process is necessary after the layers are formed, in order to obtain an ohmic contact.

[0065] In the first embodiment, although the insulating film 15 is made of silicon oxide, it may be made of different insulating material which allows light in the radiation range of the luminous layer 5 to transmit. For example, usable materials of the insulating film may be oxide such as titanium oxide (TiO₂), tantalum oxide (Ta₂O₅), alumina (Al₂O₃), zirconium oxide (ZrO₂) and hafnium oxide (HfO₂), heat resistant organic polymeric material such as polyimide, and the like.

[0066] In the first embodiment, although the p-side pad electrode 20 has the multi-layer structure of Ti/Pt/Au/(Pt/Au)_n, it may have a different multi-layer structure such as Ti/Rh/Au/(Pt/Au)_n and Ni/Rh/Au/(Pt/Au)_n. A thickness of the lower most layer of the Ti or Ni layer is set to, for example, 0.3 nm to 1 nm. A thickness of each of upper Rh, Pt and Au layers is set to 100 nm. The number n of repetitions is set to 1 to 5. The multi-layer structure satisfying these conditions allows the p-side pad electrode 20 to present the function of the reflection film, and improves the light output efficiency.

[0067] In the first embodiment, although the reflection film 16 is made of Ag, it may be made of alloy which contains Ag as a main composition. A thickness of the reflection film 16 is preferably set to 80 nm or thicker in order not to allow light radiated in the luminous layer 5 to transmit. Even if the reflection film 16 is made of the metal other than Ag likely to invoke migration, the migration suppression effect can be expected. This embodiment is particularly effective when the reflection film 16 is made of the metal likely to invoke migration more than the p-side ohmic electrode 10.

[0068] In the first embodiment, although the protective film 17 is made of silicon oxide, it may be made of different insulating material. For example, usable materials of the insulating film may be oxide such as titanium oxide (TiO₂), tantalum oxide (Ta₂O₅), alumina (Al₂O₃), zirconium oxide (ZrO₂) and hafnium oxide (HfO₂), heat resistant organic polymeric material such as polyimide, and the like.

[0069] As shown in FIG. 16, a conductive layer 63, which is made of metal such as Al having a larger ionization tendency than Ag, may be formed on a surface of the reflection film 16. By using a junction between different metals having a difference between ionization tendencies, electric corrosion of the reflection film 16 can be suppressed even under the condition that electricity is applied between the electrodes.

[0070] In the first embodiment, the p-side ohmic electrode 10, insulating film 15 and reflection film 16 constitute the multi-layer reflection film. The reflectance is dependent upon the thicknesses of these films. It is difficult to determine from experiments the conditions suitable for raising the reflectance of the multi-layer film constituted of a metal thin film and a dielectric film. Therefore, the film thickness dependency of a reflectance of a multi-layer reflection film was evaluated by simulation. The evaluation result by simulation will be described hereinunder.

[0071] FIG. 3 shows a model of a multi-layer reflection film used by simulation. On a contact layer 7 made of GaN, a p-side ohmic electrode 10 of Pt, an adhesion layer 10a of Ti, an insulating film 15 of SiO₂, an adhesion layer 16a of Ti and a reflection film 16 of Ag are stacked in this order. A reflectance of light having a wavelength of 460 nm and propagating from the contact layer 7 to the reflection film 16 was obtained by simulation.

[0072] FIG. 4 shows the relation between a thickness of the p-side ohmic electrode 10 and a reflectance. The abscissa represents a thickness of the p-side ohmic electrode 10 in the unit of “nm” and the ordinate represents a reflectance in the unit of “%”. The thicknesses of the adhesion layer 10a, insulating film 15, adhesion layer 16a and reflection film 16 were set to 0.3 nm, 285 nm, 0.3 nm and 200 nm, respectively. The reflectance is hardly influenced by the film thickness in the film thickness range equal to or thinner than 7 nm of the p-side ohmic electrode 10. In the film thickness range equal to or thicker than 7 nm, the reflectance lowers as the film thickness increases.

[0073] FIG. 5 shows the relation between a thickness of the reflection film 16 and a reflectance. The abscissa represents a thickness of the reflection film 16 in the unit of “nm” and the ordinate represents a reflectance in the unit of “%”. The thicknesses of the p-side ohmic electrode 10, adhesion layer 10a, insulating film 15 and adhesion layer 16a were set to 5 nm, 0.3 nm, 285 nm and 0.3 nm, respectively. It can be understood that as the reflection film 16 becomes thick, the reflectance increases and the reflectance saturates at a film thickness of near 80 nm. It can be understood from this result that the thickness of the reflection film 16 is preferably set to 80 nm or thicker.

[0074] FIG. 6 shows the relation between a thickness of the insulating film 15 and a reflectance. The abscissa represents a thickness of the insulating film 15 in the unit of “nm” and the ordinate represents a reflectance in the unit of “%”. The thicknesses of the adhesion layer 10a, adhesion layer 16a and reflection film 16 were set to 0.3 nm, 0.3 nm and 200 nm, respectively. Three curves in FIG. 6 show reflectances at the thicknesses of 3 nm, 5 nm and 8 nm of the p-side ohmic electrode 10. The reflectance changes periodically in accordance with a change in the thickness of the insulating film 15. The reflectance takes maximum values at the thicknesses of the insulating film 15 near about 130 nm, 286 nm and 440 nm.

[0075] It can be seen that the reflectance at the minimum value lowers as the p-side ohmic electrode 10 becomes thicker. In order to suppress a lower reflectance when the thickness of the insulating film 15 varies, it is preferable that the p-side ohmic electrode 10 is made thin. If the p-side ohmic electrode is made too thin, it is not possible to achieve the primary object of the electrode that carriers should be injected uniformly into the p-type contact layer 7. In order to meet the requirements of both a high reflectance and a uniform carrier injection, the thickness of the p-side ohmic electrode 10 is preferably set to 1 nm to 15 nm and more preferably to 3 nm to 8 nm. The thickness of the p-side ohmic electrode 10 may be thinned to 1 nm to 5 nm and a mesh type auxiliary electrode of Pt or Rh may be formed on the p-side ohmic electrode. For example, a width of one electrode constituting the mesh is set to 2 μm to 5 μm, and a distance between electrodes is set to 10 μm to 15 μm.

[0076] The measured reflectance of an actually formed evaluation sample had a maximum value at a thickness of near 300 nm of the insulating film 15, although simulation indicates a maximum reflectance at a thickness of about 286 nm of the insulating film 15. A shift of the optimum film thickness of the insulating film 15 obtained by experiments from the optimum film thickness of the insulating film 15 obtained by simulation may be ascribed to that the optical characteristics of each film used by simulation do not correctly coincide with the optical characteristics of each film actually formed. From the viewpoint of guarantee of insulating properties, etching time and the like, the thickness of the insulating film 15 is preferably set to 100 nm to 600 nm and more preferably to 200 nm to 400 nm.

[0077] FIGS. 7 and 8 show the relation between a thickness of the insulating film 15 and a reflectance, at different wavelengths. The abscissa represents a thickness of the insulating film in the unit of “nm” and the ordinate represents a reflectance in the unit of “%”. The thicknesses of the p-side ohmic electrode 10, adhesion layer 10a, adhesion layer 16a and reflection film 16 were set to 5 nm, 0.3 nm, 0.3 nm and 200 nm, respectively. A numerical number added to each of a plurality of curves shown in FIGS. 7 and 8 indicates the wavelength of light to be reflected.

[0078] As the wavelength of light to be reflected changes, the thickness of the insulating film 15 at the maximum reflectance changes. It is preferable to set the thickness of the insulating film 15 near to a thickness providing the maximum reflectance, in accordance with the wavelength of light radiated in the luminous layer.

[0079] The film thickness conditions for increasing the reflectance have been obtained through simulation. In an actual case, the refractive index and attenuation coefficient of each film change more or less depending upon a film forming method. The reflectance is also influenced by a surface roughness of a film. It is therefore preferable to determine an optimum film thickness of each film, by forming a plurality of evaluation samples having different film thicknesses by referring to the optimum film thickness and by measuring actual reflectances. The simulation results can be used as the criterion of determining a thickness of each film of the evaluation sample.

[0080] Next, description will be made on the measurement results of the reflectance of each of evaluation samples actually formed. For each evaluation sample, a sapphire substrate having a thickness of 320 μm was used as the p-side contact layer 7 shown in FIG. 3. Pt films having thicknesses of 5 nm, 8 nm and 10 nm were used as the p-side ohmic electrode 10. A Ti film having a thickness of 0.3 nm was used as the adhesion layers 10a and 16a. An SiO₂ film having a thickness of 313 nm was used as the insulating film 15. An Ag film having a thickness of 200 nm was used as the reflection film 16.

[0081] As a GaN film having a thickness of about 4 μm to 8 μm is formed on the sapphire substrate, a warp is formed on the substrate. As the warp is formed on the substrate, it is not possible to correctly adjust the incidence angle of incidence light to be used for measuring a reflectance. From this reason, a sapphire substrate not formed with a GaN layer was used as the measurement sample.

[0082] FIG. 9 shows the measurement results of reflectances. The abscissa represents a wavelength in the unit of “nm” and the ordinate represents a reflectance in the unit of “%”. The samples actually formed had maximum reflectances in the wavelength range of 350 nm to 360 nm and in the wavelength range of 510 nm to 520 nm. By measuring reflectances of various samples actually formed, it is possible to obtain the relation between the reflectance of a multi-layer reflection film formed on the sapphire substrate and the reflectance of a multi-layer reflection film formed on the GaN layer. By utilizing this relation, an optimum film thickness of the insulating film 15 can be estimated.

[0083] Next, with reference to FIGS. 10 and 11, a semiconductor light emitting device of the second embodiment will be described.

[0084] FIG. 10 is a plan view of a semiconductor light emitting device of the second embodiment. In the first embodiment shown in FIG. 1B, the reflection film 16 is made of a plain film and superposes most area of the p-side ohmic electrode 10. In the second embodiment, in place of the reflection film 16, a reflection pattern 16a of a grid shape is disposed. The other fundamental structure is similar to that of the semiconductor light emitting device of the first embodiment. In the example shown in FIG. 10, although a p-side pad electrode 20 and an n-side pad electrode 21 are disposed slightly inside of the central area of a pair of opposing sides of a rectangle, they may be disposed near at the vertexes of the rectangle as in the case of the first embodiment shown in FIG. 1B.

[0085] In the semiconductor light emitting device of the second embodiment, light radiated in the luminous layer is irradiated to an external via the support substrate and to the side opposite to the support substrate via openings of the reflection pattern 16a. Light is also scattered by the reflection pattern 16a and irradiated to the side of the semiconductor light emitting device.

[0086] FIG. 11 is a schematic cross sectional view of a lamp having the semiconductor light emitting device of the second embodiment built therein. On the bottom of a recess of a metal frame 30, the semiconductor light emitting device 28 shown in FIG. 10 is mounted with the support substrate directed to the frame side. A cathode lead 31 extends from the frame 30. An n-side pad electrode 21 of the semiconductor light emitting device 28 is connected to the frame 30 via a gold wire 35. The p-side pad electrode 20 is connected to an anode lead 32 via a gold wire 36.

[0087] The fluorescent member 37 buries the recess of the frame 30. The semiconductor light emitting device 28 is covered with the fluorescent member 37. The frame 30, cathode lead 31 and anode lead 32 are molded with sealing resin 38.

[0088] Light irradiated toward the lower portion of the semiconductor light emitting device 28 (on the side of the support substrate) is reflected by the frame 30 and becomes incident upon the fluorescent member 37. Light irradiated toward the side and upper portions of the semiconductor light emitting device 28 (on the side opposite to the support substrate) becomes also incident upon the fluorescent member 37. Upon reception of light, the fluorescent member 37 radiates fluorescence which is irradiated to the outside of the resin mold 38.

[0089] Since light is irradiated toward the lower, side and upper portions of the semiconductor light emitting device 28, it is possible to alleviate color shade.

[0090] In the second embodiment, although the reflection pattern 16a of the grid shape is used, another pattern having openings and scattering light may be used. For example, a stripe pattern, a honeycomb pattern or the like may be used.

[0091] Next, with reference to FIGS. 12A and 12B and FIG. 13, a semiconductor light emitting device of the third embodiment will be described.

[0092] FIG. 12A is a cross sectional view of the semiconductor light emitting device of the third embodiment, and FIG. 12B is a plan view thereof. A cross sectional view taken along one-dot chain line A12—A12 shown in FIG. 12B corresponds to FIG. 12A. Description will be made on different points from the semiconductor light emitting device of the first embodiment.

[0093] In the first embodiment, the n-side pad electrode 21 is disposed on the n-side ohmic electrode 11, whereas in the second embodiment, an n-side pad electrode 21 is disposed over a p-side ohmic electrode 10 and contacts a reflection film 16. A p-side pad electrode 20 and the n-side pad electrode 21 are exposed on the bottoms of openings 17a and 17b formed through a protective film 17.

[0094] As shown in FIG. 12B, the n-side ohmic electrode 11 is disposed along one side of a support substrate 1. The p-side pad electrode 20 is disposed near at one end of the side facing the side along which the n-side ohmic electrode 11 is disposed. The reflection film 16 occupies most of the area where the p-side pad electrode 20 is not disposed. The n-side pad electrode 21 occupies most of the area where the reflection film 16 superposes the p-side ohmic electrode 10.

[0095] FIG. 13 is a schematic cross sectional view of a lamp having the semiconductor light emitting device of the third embodiment built therein. The semiconductor light emitting device 50 of the third embodiment is flip-chip-bonded to a sub-mount substrate 43. The p-side pad electrode 20 and n-side pad electrode 21 of the semiconductor light emitting device 50 are connected to respective anode wiring 44 and cathode wiring 45 formed on the sub-mount substrate 43. The sub-mount substrate 43 is fixed to a stem 40. An anode lead 42 and a cathode lead 41 are fixed to the stem 40. The anode wiring 44 is connected to the anode lead 42 via a gold wire 46, and the cathode wiring 45 is connected to the cathode lead 41 via a gold wire 47.

[0096] The semiconductor light emitting device 50 and sub-mount substrate 43 are sealed with sealing resin 48. Light radiated in the luminous layer of the semiconductor light emitting device 50 is reflected by the reflection film 16 shown in FIG. 12A and transmits through the support substrate 1 and sealing resin 48 to be irradiated to an external.

[0097] In the semiconductor light emitting device of the third embodiment, the n-side pad electrode 21 occupies a broader area of the device surface, as compared to the semiconductor light emitting device of the first embodiment. Via this broad n-side pad electrode 21, heat generated in the device efficiently flows to the sub-mount substrate 43. A good heat radiation effect can therefore be retained.

[0098] Next, with reference to FIGS. 14A and 14B, a semiconductor light emitting device of the fourth embodiment will be described.

[0099] FIG. 14A is a cross sectional view of the semiconductor light emitting device of the fourth embodiment, and FIG. 14B is a plan view thereof. A cross sectional view taken along one-dot chain line A14—A14 shown in FIG. 14B corresponds to FIG. 14A. In the fourth embodiment, four n-side ohmic electrodes 11 are disposed along four sides of a support substrate 1 of a square shape. A reflection film 16 is connected to four n-side ohmic electrodes 11. An opening 16a is formed through the reflection film 16 in such a manner that a p-side pad electrode 20 exists in this opening. By forming this opening 16a, a short circuit between the reflection film 16 and p-side pad electrode 20 can be avoided.

[0100] In the fourth embodiment, since four n-side ohmic electrodes 11 are formed, a contact area of the electrodes can be broadened so that a contact resistance can be lowered. Since four n-side ohmic electrodes 11 are disposed along the four sides of the square, a current deviation in the substrate in-plane can be reduced.

[0101] The areas near the vertexes of the support substrate 1 are likely to be broken during device separation. It is therefore preferable that the n-side ohmic electrodes 11 are not extended near to the vertexes of the support substrate 1.

[0102] In the fourth embodiment, the whole side area of a mesa portion constituted of the lamination structure from the n-type clad layer 4 to p-type clad layer 7 is covered with the reflection film 16. It is therefore possible to efficiently reflect light irradiated from the luminous layer 5 toward the side portion, toward the support substrate 1 side and improve the light output efficiency. In order to further improve the light output efficiency, it is preferable to make the side wall of the mesa portion be inclined. For example, the inclination angle of the side wall of the mesa portion is preferably set to 60° or larger.

[0103] In the following, description will be made on an example of a method of inclining the side wall of the mesa portion. When a usual resist pattern is formed, exposure is performed under the condition that a photomask is made in contact with a resist film. If the side wall of the mesa portion is to be made inclined, exposure is performed under the condition that a photomask is slightly floated above a resist film. Since there is a gap between the resist film and the photomask, the edges of the pattern of the photomask are transferred unsharply. As the resist film is developed, a resist pattern having an inclined side wall can be obtained.

[0104] By using this resist pattern as an etching mask, a nitride semiconductor layer is dry-etched. Since the resist pattern is also gradually etched, the side wall of the mesa portion of the nitride semiconductor is made inclined in correspondence with the inclination of the side wall of the resist pattern.

[0105] In the above-described embodiments, although the reflection film 16 is connected to the n-side ohmic electrode 11, the reflection film 16 may be made in a floating state by connecting it neither to the p-side ohmic electrode 10 nor to the n-side ohmic electrode 11. Also in the floating state, migration can be suppressed more than when the reflection film is connected to the anode as shown in FIGS. 15B and 15C.

[0106] The present invention has been described in connection with the preferred embodiments. The invention is not limited only to the above embodiments. It will be apparent to those skilled in the art that other various modifications, improvements, combinations, and the like can be made.