Integrated circuit with self-aligned line and via and manufacturing method therefor

[0001] The present invention relates generally to integrated circuits and more specifically to line and via interconnects for semiconductor devices.

[0002] Semiconductor technology has been progressing rapidly to the point where integrated circuits incorporating over a million transistors are possible. However, the rapid development of technologies, which require such integrated circuits, has increased just as rapidly. Applications such as real-time graphics, high-definition television, virtual reality, and other scientific and industrial applications are demanding higher speed, greater functionality, and even more rapid advances in very large-scale integrated circuit technology.

[0003] The demand for more functionality requires a tremendous increase in the number of transistors to be integrated onto a single integrated circuit chip. This requires shrinking the sizes of the transistors and/or having larger die sizes.

[0004] As the sizes of the transistors decrease, the resulting increased density requires an increasing number of interconnections within the integrated circuit chip. As the number of interconnections increases, the amount of area on the semiconductor die occupied by the interconnections becomes relatively large and may offset the savings made by reducing the size of the transistors.

[0005] A long sought goal in the semiconductor industry for very large-scale integrated circuits has been to achieve minimum area layouts for interconnections because minimum area layouts typically provide optimum performance and economy.

[0006] In addition, as the number of transistors proliferate, multiple levels of interconnections are required between the interconnect lines and the vias which connect different levels.

[0007] As everything is shrunk in size, misalignment comes to play a major factor in determining the performance capabilities of the interconnects. Unfavorable circumstances of misalignment can be fatal in the operation of an integrated circuit.

[0008] Further, it has been found that top misalignment between the uppermost interconnect line and a via has a great influence on via resistance and via chain yield. Small areas of line—via overlap, and incidents of via being corroded by etch clean solutions magnify the problems caused by misalignment.

[0009] Solutions to these problems have been long sought, but have equally as long eluded those skilled in the art.

[0010] The present invention provides an integrated circuit, and manufacturing method therefor, having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals, such as aluminum or copper are deposited in the trench openings to form self-aligned trench interconnects. This self-aligned patterning technique achieves self-aligning interconnects which avoid misalignment and enhance the performance capabilities of the interconnects.

[0011] The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.

[0030] Referring now to FIG. 1, therein is shown a portion of an integrated circuit in an intermediate stage of manufacture according to the present invention. The integrated circuit interconnect 10 is built on a base 12 which may be a semiconductor substrate, silicon for a silicon-on-insulator (SOI) structure, a dielectric layer, a stop layer, or other lines, vias, or contacts. The other lines, vias, and contacts would be connected to semiconductor devices on, in, or under the semiconductor substrate, silicon-on-insulator, dielectric layers, or stop layers. In the present invention, the first dielectric layer 14 is already deposited on an initial stop layer 15 over the base 12. The dielectric layers herein may be materials such as silicon oxide, silicon nitride, or low dielectric constant dielectric material having a dielectric constant under about 3.9.

[0031] A first stop layer 16 is also already deposited on the first dielectric layer 14 and a second dielectric layer 18 is also already deposited over the first stop layer 16. The term “stop layer” is used as a matter of convenience herein because such a layer is generally used to stop various etching processes although it does not necessarily have to perform this function. The stop layers may be a material such as silicon nitride or silicon oxide.

[0032] The term “horizontal” as used in herein is defined as a plane parallel to the conventional plane or surface of a wafer, such as the base 12, regardless of the orientation of the wafer. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “on”, “above”, “below”, “side” (as in “sidewall”), “higher”, “lower”, “over”, and “under”, are defined with respect to the horizontal plane.

[0033] Referring now to FIG. 2, therein is shown the structure of FIG. 1 with the deposition of a protective dielectric layer 20 and a second stop layer 22. The protective dielectric layer 20 is optional and is used primarily with low dielectric constant dielectric materials to prevent them from being poisoned by subsequent depositions of photoresist.

[0034] Referring now to FIG. 3, therein is shown the structure of FIG. 2 after patterning of the second stop layer 22 with a trench mask and processing to remove a portion of the second stop layer 22 and expose portions of the protective dielectric layer 20.

[0035] Referring now to FIG. 4, therein is shown the structure of FIG. 3 after deposition, patterning, and processing of a conformal photoresist layer 24 which is patterned with a via mask. The conformal photoresist layer 24 and the second stop layer 22 cooperate to expose generally rectangular areas of the protective dielectric layer 20. It will be understood by those skilled in the art that a dielectric layer, which may be the protective dielectric layer 20 or the second dielectric layer 18, may be exposed in any desired configuration so that the resulting vias may be round, square, or otherwise.

[0036] Referring now to FIG. 5, therein is shown the structure of FIG. 4 having been anisotropically etched to form vias 26 and 28. The vias 26 and 28 are etched through the protective dielectric layer 20, the second dielectric layer 18 to the first stop layer 16.

[0037] Referring now to FIG. 6, therein is shown the structure of FIG. 5 after removal of the conformal photoresist layer 24 in preparation for formation of the interconnect lines.

[0038] Referring now to FIG. 7, therein is shown the structure of FIG. 6 after removal by anisotropic etching of the protective dielectric layer 20 to expose the second dielectric layer 18.

[0039] Referring now to FIG. 8, therein is shown the structure of FIG. 7 after etching through the first stop layer 16 and optionally etching the second stop layer 22.

[0040] Referring now to FIG. 9, therein is shown the structure of FIG. 8 after removal by anisotropic etching of the exposed second dielectric layer 18 down to the first stop layer 16 and the first dielectric layer 14 down to the initial stop layer 15. This step forms the interconnect line openings 30 and 32 which precisely intersect the respective via openings 26 and 28 such that the widths of the contiguous openings between first dielectric layer 14 and the second dielectric layer 18 are exactly the same and self-aligned.

[0041] Referring now to FIG. 10, therein is shown the structure of FIG. 9 after etching of the first stop layer 16 and the initial stop layer 15. The etching of the initial stop layer is for connection to other structures of the integrated circuit such as semiconductor transistors or other components (not shown).

[0042] Referring now to FIG. 11, therein is shown the completed interconnect 10 in accordance with the present invention. With the via openings 26 and 28 and the interconnect line openings 30 and 32 (of FIG. 10) being respectively filled by conductive metals 34 and 36, vias 38 and 40 form a borderless interconnection with interconnect lines 42 and 44, respectively. It will be understood that various conductive metals may be used including aluminum and copper. Copper will have a diffusion barrier deposited first.

[0043] Because the via level and the interconnect level are formed at the same time, this method of formation would be described as a dual inlaid or dual damascene technique borderless interconnect.

[0044] Referring now to FIG. 12, therein is shown an alternate embodiment of an interconnect 50 in an intermediate stage of manufacture. In FIG. 12, the equivalent steps as shown in FIGS. 1–3 have been completed. A base 52 has an initial stop layer 53 and a first dielectric layer 54 deposited thereon. A first stop layer 56 is deposited on the first dielectric layer 54 and a second dielectric layer 58 is deposited on the first stop layer 56. A protective dielectric layer 60 is optionally deposited on the second dielectric layer 58 when it is a low dielectric constant dielectric material.

[0045] A second stop layer 62 has been deposited and patterned and a photoresist layer 64 has been deposited on the second stop layer 62 and processed so that the second stop layer 62 and the photoresist layer 64 cooperate to expose via or deep trench areas on the protective dielectric layer 60. In this configuration, the photoresist layer 64 overlays the center of the interconnect 50.

[0046] Referring now to FIG. 13, therein is shown the structure of FIG. 12 having been anisotropically etched for deep trenches 66 through 69. The deep trenches 66 through 69 are etched through the protective dielectric layer 60, the second dielectric layer 58, the first stop layer 56, and the first dielectric layer 54, down to the initial stop layer 53.

[0047] Referring now to FIG. 14, therein is shown the structure of FIG. 13 after removal of the photoresist layer 64 and the protective dielectric layer 60. A removal process by anisotropic etching of the second dielectric layer 58 and the first dielectric layer 54 have been performed down to the first stop layer 56 and initial stop layer 53, respectively. Subsequently, the first stop layer 56 and the initial stop layer 53 have also been removed by anisotropic etching so as to form the interconnect line openings 70 and 72 which precisely intersect the respective deep trenches 66–67 and 68–69 such that the widths of the contiguous openings between the first dielectric layer 54 and the second dielectric layer 58 are exactly the same and self-aligned.

[0048] Referring now to FIG. 15, therein is shown the structure of FIG. 14 after deposition of conductor metals 74 and 76, which will form deep trenches 78–81 connected by shallow trenches 82 and 84, respectively. The completed structure of the interconnect 50 will be a dual inlaid or dual damascene technique borderless interconnect.

[0049] Referring now to FIG. 16, therein is shown a further alternate embodiment wherein the structure of FIG. 3 has an additional layer of dielectric deposited thereon which is patterned and processed in a conventional manner to form dielectric spacers 23, 25, 27, and 29. As would be evident to those skilled in the art, this would permit the manufacture of the previous structures described herein to result in bordered structures wherein the upper layers of conductor metal are larger than the lower layers of conductor metal so that, while the self-alignment characteristics are maintained, the interconnect lines will be wider than the width of the vias by the width of the spacers.

[0050] Referring now to FIG. 17, therein is shown a cross-section of a dual inlaid or dual damascene technique borderless interconnect 100 taken along line 17—17 of FIG. 11 for clarity with via 38 borderless with channel 34 and the via 40 borderless with the channel 36.

[0051] Referring now to FIG. 18, therein is shown a cross-section of a dual inlaid or dual damascene technique bordered interconnect 110 taken along line 18—18 of a completed version of FIG. 16 for clarity with the via 38′ smaller than the channel 34 and the via 40′ smaller than the channel 36. The dielectric spacers 23, 25, 27, and 29 have been used in etching the vias 38′ and 40′ and then are removed. The channels 34 and 36 are then etched without the dielectric spacers 23, 25, 27, and 29 and are wider by their width.

[0052] While the invention has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the aforegoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations which fall within the spirit and scope of the included claims. All matters hither-to-fore set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.