Voltage source circuit with selectable temperature independent and temperature dependent voltage outputs

[0001] This application claims the benefit of provisional patent application No. 60/540,704 to Daly et al., filed Jan. 30, 2004.

[0002] 1. Field of the Invention

[0003] This invention relates to the field of voltage source circuits, and particularly to voltage source circuits capable of producing multiple output voltages having different characteristics.

[0004] 2. Description of the Related Art

[0005] Voltage source circuits, which provide one or more output voltages, are well-known. Typically, such a circuit produces one or more output voltages, all of which have similar characteristics. For example, a voltage source might provide a temperature independent output voltage. Alternatively, an output voltage which is proportional to temperature might be provided. The desired characteristics of the circuit's output voltage would be determined based on the application for which the voltage is used.

[0006] One voltage source circuit which provides a temperature independent output voltage is described in U.S. Pat. No. 5,867,012 to Tuthill. This “switching bandgap reference” employs first and second pn junctions which conduct first and second currents to establish first and second base-emitter voltages at first and second nodes. An operational amplifier has its non-inverting input connected to the second node and its inverting input connected to the first node through an input capacitor. A feedback capacitor is connected between the amplifier's inverting input and its output, and a switch is connected across the feedback capacitor.

[0007] The circuit operates with first and second clocks which initiate first and second operating phases. During the first phase, the switch is closed such that the op amp operates as a follower, and the second output current is made greater than the first output current; the resulting ΔV_be between the first and second nodes is applied across the input capacitor via the op amp. During the second phase, the switch is opened and the second output current is made less than the first output current, thereby creating another ΔV_be term between the first and second nodes. At the end of the second phase, the amplifier's output voltage contains both proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) voltage terms. When the circuit is properly arranged, these terms sum to produce a temperature stabilized voltage at the amplifier output.

[0008] This circuit design is capable of providing an output voltage having a particular characteristic—i.e., a temperature stabilized voltage. However, it is unable to provide an output voltage having different characteristics, should such a voltage be needed by a particular application.

[0009] A voltage source circuit is presented which overcomes the problem noted above, in that it is capable of selectively providing either of two output voltages having different characteristics.

[0010] The present voltage source circuit is capable of selectively providing a temperature independent output voltage or a temperature dependent output voltage. The voltage source circuit includes a base-emitter voltage generating circuit, in which first and second pn junctions conduct the outputs of respective current sources to establish respective base-emitter voltages (V_be1 and V_be2) at respective nodes. The generating circuit is arranged such that V_be1 and V_be2 can be generated with either of two different currents (I or N*I), such that each can be at one of two different voltages.

[0011] An amplifier has its non-inverting input connected to the second node and its inverting input connected to the first node through an input capacitor; a feedback capacitor is connected between the inverting input and a third node. A first switch S1 is connected between the amplifier's inverting input and its output, a second switch S2 is connected between the third node and the amplifier's output, and a third switch S3 is connected between the third node and a circuit common point.

[0012] A control circuit is arranged to operate the switches and the base-emitter voltage generating circuit during first and second operating phases to selectively provide either a temperature independent or temperature dependent output voltage. In a preferred embodiment, the temperature dependent output voltage is a PTAT voltage. When producing a temperature independent output voltage, the control circuit's operation results in an output voltage V_out which contains both PTAT and CTAT terms, which can be balanced to make V_out temperature independent. Alternatively, the control circuit can operate such that V_out is temperature dependent, such as a PTAT or CTAT voltage. The voltage source circuit could be operated such that sequentially produced output voltages have different characteristics; for example, the circuit could be arranged such that its output alternates between temperature independent and temperature dependent output voltages.

[0013] Several variations to the basic embodiment are described which provide enhanced performance and/or operational flexibility. In a preferred embodiment, a fourth switch is added and operated such that the amplifier's input offset voltage is substantially eliminated from V_out.

[0014] Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.

[0025] A basic embodiment of a voltage source circuit capable of selectively providing a temperature independent or temperature dependent output voltage is shown in FIG. 1. The present voltage source circuit includes a “base-emitter voltage generating circuit” 10, which comprises first and second current sources (12, 14) which provide first and second currents (i1, i2), respectively, and first and second pn junctions (16, 18) connected to conduct i1 and i2, respectively, and thereby establish first and second base-emitter voltages V_be1 and V_be2 at first and second nodes 20 and 22, respectively. Generating circuit 10 is arranged such that V_be1 can be selectively set to a first value V_be1(I) or a second value V_be1(N*I), and such that V_be2 can be selectively set to a first value V_be2(I) or a second value V_be2(N*I). This is preferably accomplished by making current sources 12 and 14 variable, such that each of currents i1 and i2 can be set to a value I or a value N*I.

[0026] The voltage source circuit also includes an amplifier A1 having an output 30, a non-inverting input 32 and an inverting input 34. A1's non-inverting input is connected to second node 22, and its inverting input is connected to first node 20 through an input capacitor 36 having a capacitance C1. A1's output is connected to a terminal 38 which serves as the voltage source's output, identified as V_out.

[0027] Also included as part of the present voltage source circuit is a feedback capacitor 40 having a capacitance C2, connected between A1's inverting input 34 and a third node 42, a first switch S1 connected between A1's inverting input and its output 30, a second switch S2 connected between third node 42 and A1's output 30, and a third switch S3 connected between third node 42 and a circuit common point 44; common point 44 would typically be ground, but could also be a non-zero potential.

[0028] A control circuit 46 is provided to operate switches S1–S3 and base-emitter voltage generating circuit 10 during first and second operating phases to produce a temperature independent output voltage or a temperature dependent output voltage such as a PTAT or CTAT voltage. The examples below describe how the present voltage source circuit can be used to selectively provide a temperature independent or PTAT voltage. Note, however, that the present circuit is not limited to producing temperature independent and PTAT voltages. Voltages having other characteristics, such as a CTAT voltage, could also be produced by properly adjusting the circuit's switch sequencing and/or component values.

[0029] When producing a temperature independent output voltage, control circuit 46 (not shown in FIGS. 2a, 2b, 3a and 3b) is arranged to, during the first operating phase (see FIG. 2a) operate base-emitter voltage generating circuit 10 such that first and second nodes 20 and 22 are at V_be1(N*I) and V_be2(I), respectively. This is accomplished by making output current i1 of current source 12 equal to N*I and output current i2 of current source 14 equal to I. Switches S1 and S2 are closed (and S3 is open). V_be2(I) is applied to the non-inverting input of A1, which operates as a follower such that C1 has a voltage across it equal to
V_be2(I)−V_be1(N*I)+V_os,
where V_os is the amplifier's input offset voltage.

[0030] During the second operating phase, control circuit 46 is arranged to (see FIG. 2b) operate base-emitter voltage generating circuit 10 such that first and second nodes 20 and 22 are at V_be1(I) and V_be2(N*I), respectively, accomplished by making output current i1 of current source 12 equal to I and output current i2 of current source 14 equal to N*I. Switch S1 is opened (and S3 is kept open). The charge on C1 is transferred to C2. The magnitude of the voltage lost from C1 is equal to: 2*(V_be2(N*I)V_be1(I)); V_os remains across C1. This charge increases the voltage on C2 by: 2*(V_be2(N*I)V_be1(I))*(C1/C2). The voltage at A1's inverting input 34 is V_be2(N*I)+V_os, such that, at the end of the second phase, output voltage V_out is given by:
V_out=V_be2(N*I)+V_os+2*(V_be2(N*I)−V_be1(I))*(C1/C2).
The equation for V_out contains a PTAT term (V_be2(N*I)−V_be1(I)) and a CTAT term (V_be2(N*I)); as such, output voltage V_out can be made substantially independent of temperature by choosing appropriate values for “N” and/or for the ratio C1/C2.

[0031] When producing a PTAT output voltage, control circuit 46 is arranged to, during the first operating phase (see FIG. 3a) operate base-emitter voltage generating circuit 10 such that first and second nodes 20 and 22 are at V_be1(N*I) and V_be2(I), respectively, by making i1=N*I and i2=I. Switches S1 and S3 are closed (and S2 is open) such that C1 has a voltage across it equal to V_be2(I)−V_be1(N*I)+V_os, and C2 has a voltage across it equal to V_be2(I)+V_os.

[0032] During the second operating phase, control circuit 46 is arranged to (see FIG. 3b) operate base-emitter voltage generating circuit 10 such that first and second nodes 20 and 22 are at V_be1(I) and V_be2(I), respectively, accomplished by making output currents i1 and i2 both equal to I. Switch S2 is closed and switches S1 and S3 are opened, causing a charge proportional to V_be2(I)−V_be1(N*I)=ΔV_be to be transferred from C1 to C2. The voltage at A1's inverting input 34 remains at V_be2+V_os, and this voltage is subtracted from the output due to C2 having sampled this same voltage during the first operating phase. At the end of the second phase, output voltage V_out is given by:
V_out=2*k*(C1/C2)*ΔV_be,
where k is a proportionality constant. The equation's ΔV_be term makes V_out PTAT.

[0033] As noted above, the voltage source circuit could be operated such that sequentially produced output voltages have different characteristics; for example, the circuit could be arranged such that its output alternates between temperature independent and temperature dependent output voltages.

[0034] Pn junctions 16 and 18 can be implemented with simple diodes. However, they are preferably implemented with respective diode-connected PNP transistors as shown. If the present voltage source is used with CMOS circuitry, pn junctions 16 and 18 can be implemented with respective parasitic substrate bipolar transistors. For simplicity, the areas of pn junction 16 and 18 are preferably equal, though this is not essential.

[0035] A preferred embodiment of the invention, capable of selectively providing a temperature independent or a PTAT output voltage, and which substantially reduces or eliminates the magnitude of A1's input offset voltage in output voltage V_out, is shown in FIG. 4. This embodiment is similar to the one discussed above, except for the addition of a switch S4 connected between A1's non-inverting input 32 and node 42, a resistive divider 50 connected between the output 30 of amplifier A1, a switch S5 connected between A1's output 30 and output terminal 38, and a switch S6 connected between the divider output 52 and output terminal 38. Also note that here, switches S1 and S2 are connected to terminal 38 rather than A1's output 30.

[0036] Here, control circuit 54 operates switches S1–S6 and base-emitter voltage generating circuit 10 during first and second operating phases to produce a temperature independent output voltage or a PTAT output voltage. When producing a temperature independent output voltage, control circuit 54 (not shown in FIGS. 5a, 5b, 6a and 6b) is arranged to, during the first operating phase (see FIG. 5a) operate base-emitter voltage generating circuit 10 such that first and second nodes 20 and 22 are at V_be1(N*I) and V_be2(I), respectively, by making output current i1=N*I and i2=I. As before, A1 acts as a follower. Switches S1 and S5 are closed such that C1 has a voltage across it equal to V_be2(I)−V_be1(N*I)+V_os, and S4 is closed such that C2 has a voltage across it equal to V_os; switches S2, S3 and S6 are open.

[0037] During the second operating phase, control circuit 54 is arranged to (see FIG. 5b) operate base-emitter voltage generating circuit 10 such that first and second nodes 20 and 22 are at V_be1(I) and V_be2(N*I), respectively, by making i1=I and i2=N*I. Switches S1 and S4 are opened, S2 is closed, and the other switches are unchanged. The charge on C1 is transferred to C2. The magnitude of the voltage lost from C1 is equal to 2*(V_be2(N*I)−V_be1(I)); V_os remains across C1. This charge increases the voltage on C2 by 2*(V_be2(N*I)−V_be1(I))*(C1/C2). The voltage at A1's inverting input 34 is V_be2(N*I)+V_os, such that, at the end of the second phase, output voltage V_out is independent of the offset voltage, as V_os gets subtracted by C2 because it has sampled this voltage during the first operating phase. The final result is an output voltage V_out given by:
V_out=V_be2(N*I)+2*(V_be2(N*I)−V_be1(I))*(C1/C2)
The equation for V_out contains a PTAT term (V_be2(N*I)−V_be1(I)) and a CTAT term (V_be2(N*I)); as such, output voltage V_out can be made substantially independent of temperature by choosing appropriate values for “N” and/or for the ratio C1/C2.

[0038] When producing a PTAT output voltage, control circuit 54 is arranged to, during the first operating phase (see FIG. 6a) operate base-emitter voltage generating circuit 10 such that first and second nodes 20 and 22 are at V_be1(N*I) and V_be2(I), respectively, by making output current i1=N*I and i2=I. Switches S1, S3 and S6 (which connects divider output 52 to output terminal 38) are closed such that C1 has a voltage across it equal to V_be2(I)−V_be1(N*I)+V_os and C2 has a voltage across it equal to V_be2(I)+V_os. Switches S2 and S4 are open.

[0039] During the second operating phase, control circuit 54 is arranged to (see FIG. 6b) operate base-emitter voltage generating circuit 10 such that first and second nodes 20 and 22 are at V_be1(I) and V_be2(I), respectively, by making i1=i2=I. Switch S2 is closed and switches S1 and S3 are opened, causing a charge proportional to V_be2(I)−V_be1(N*I)=ΔV_be to be transferred from C1 to C2. The voltage at A1's inverting input 34 remains at V_be2(I)+V_os, and this voltage is subtracted from the output due to C2 having sampled this same voltage during the first operating phase. At the end of the second phase, output voltage V_out is given by:
V_out=2*k*(C1/C2)*ΔV_be,
where k is a proportionality constant. The equation's ΔV_be term makes V_out PTAT.

[0040] The constant of proportionality, k, can be altered using the variable resistor in divider 50, and/or by varying the capacitor ratio C1/C2. Using a resistive divider as shown is preferred (though not essential), as this allows C1/C2 to be independently selected as needed to provide the temperature independent output voltage.

[0041] The configuration shown in FIG. 4 is preferred because it enables output voltage V_out to be substantially free of amplifier offset. In addition, the common mode voltage (i.e., the average input voltage into the amplifier), does not change from cycle to cycle, which prevents V_out from being adversely affected by parasitic capacitance at the inputs to amplifier A1.

[0042] The base-emitter voltage generating circuit required by the present invention could be implemented in a number of different ways. As noted above, pn junctions 16 and 18 could be diodes or transistors, preferably—but not necessarily—of equal size. Current sources 12 and 14 could provide output currents which vary in response to respective control signals, or multiple current sources providing fixed output currents could be connected to pn junctions 16 and 18 via a switching network as needed to provide the desired current (N or N*I).

[0043] While particular embodiments of the invention have been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art. Accordingly, it is intended that the invention be limited only in terms of the appended claims.