US 7,105,434 B2Grant
Advanced seed layery for metallic interconnects
Issue Date:2006-09-12
•21 Claims
•5 Drawing Sheets
Abstract
One embodiment of the present invention is a method for making metallic interconnects, which method is utilized at a stage of processing a substrate having a patterned insulating layer which includes at least one opening and a field surrounding the at least one opening, the field and the at least one opening being ready for depositing one or more seed layers, which method includes steps of: (a) depositing by an ALD technique at least an initial portion of a substantially conformal seed layer on the field and inside surfaces of the at least one opening, wherein said at least one opening has a width of less than about 0.13 μm; (b) depositing by a PVD technique a substantially non-conformal seed layer over the substantially conformal seed layer, said substantially non-conformal seed layer being thicker than said substantially conformal seed layer over the field; and (c) electroplating a metallic layer over the substantially non-conformal seed layer, wherein the electroplated metallic layer consists of a material selected from a group consisting of Cu, Ag, or alloys comprising one or more of these metals.
Metadata
Inventor
- Uri Cohen
Application Information
Application Number:US 11/023,833
Filing Date:2004-12-28
Priority Date:1999-10-02
Art Unit:2891
Classifications
IPC:
H01L21/4763
Patent Drawings (5 sheets)
Description
[0001] This is a continuation of a patent application entitled “Methods for Making Multiple Seed Layers for Metallic Interconnects”, Ser. No. 10/328,629, filed on Dec. 23, 2002 now U.S. Pat. No. 6,924,226, which itself is a continuation-in-part of a patent application entitled “Multiple Seed Layers for Metallic Interconnects”, Ser. No. 09/730,220, filed on Dec. 4, 2000, now U.S. Pat. No. 6,518,668, which itself is a continuation-in-part of a patent application entitled “Seed Layers for Interconnects and Methods and Apparatus for Their Fabrication”, Ser. No. 09/563,733, filed on May 3, 2000, now U.S. Pat. No. 6,610,151, which itself is a continuation-in-part of a patent application entitled “Seed Layers for Interconnects and Methods for Fabricating Such Seed Layers”, Ser. No. 09/410,898, filed on Oct. 2, 1999, now U.S. Pat. No. 6,136,707 which issued on Oct. 24, 2000.
Technical Field of the Invention
[0002] The present invention pertains to the field of electroplating metals or alloys on a workpiece (or substrate) having openings upon its surface.
Background of the Invention
[0003] As is well known in the prior art, filling trenches and/or vias formed on a wafer by electroplating copper metal to form semiconductor device interconnects (often referred to as a “Damascene” or a “Dual Damascene” process) requires that a metallization layer (often referred to in the art as a seed layer or a base layer) be formed over the wafer surface. As is also well known in the prior art, the seed layer is required: (a) to provide a low-resistance electrical path (to enables uniform electroplating over the wafer surface); (b) to adhere well to the wafer surface (usually to an oxide-containing a dielectric film such as SiO2, SiOX, or SiOXNY); and (c) to be compatible with subsequent electroplating copper upon its surface.
[0004] As is well known, the requirement of providing a low-resistance electrical path is fulfilled by choosing the seed layer to be comprised of an adequately thick, low-resistivity material.
[0005] As is further well known, since copper has a rather poor adhesion to oxide surfaces, the requirement of adhering well to the wafer surface is typically fulfilled by disposing an intermediary barrier (or adhesion) metallic layer having a strong affinity for oxygen atoms under the seed layer. As is well known in the prior art, the barrier metallic layer is formed prior to the seed layer to provide good adhesion: (a) to the oxide surface underneath it (the barrier layer provides good adhesion to the oxide surface by sharing oxygen atoms) and (b) to the seed layer above it (the barrier metallic layer provides good adhesion to the seed layer by metal to metal bonds). The barrier layer is often also referred to as an “adhesion layer” or a “liner”. In addition to providing good adhesion, the barrier layer also serves to mitigate copper out-diffusion directly into the device, or indirectly (through an insulating or a dielectric layer) into the device. As is well known in the prior art, the barrier layer is usually chosen from the refractory metals or their alloys, such as for example, Ta, TaNX, Cr, CrNX, Ti, TiNX, W, WNX, TaSiXNY, TiSiXNY, WSiXNY, and other alloys containing one or more of these materials.
[0006] As is still further well known, the requirement of being compatible with electroplating copper is fulfilled by choosing a seed layer that does not react spontaneously (i.e., by displacement) with copper electrolyte used during the electroplating. This is satisfied by requiring that the seed layer does not comprise a metal or alloy that is less noble than copper.
[0007] Typically, a seed layer comprises a copper layer that is deposited by a “dry” technique, such as by physical vapor deposition (“PVD”), including but not limited to sputtering, ion plating, or evaporation, or by chemical vapor deposition (“CVD”). However, the seed layer may also be deposited by a “wet” electroless plating process. In such cases, the copper seed layer thickness is typically in a range of about 300 Å to about 2,000 Å on the field (i.e., the top surface of the wafer outside trenches and via openings). In such cases, the barrier layer is typically deposited to a thickness of about 50 Å to about 500 Å (on the field) by either a PVD or a CVD technique.
[0008] The PVD techniques include, for example and without limitation, techniques such as evaporation, ion plating, and various sputtering techniques. Sputtering techniques include, for example and without limitation, techniques such as DC and/or RF plasma sputtering, bias sputtering, collimated sputtering, magnetron sputtering, Hollow Cathode Magnetron (HCM) sputtering, Self Ionized Plasma (SIP) sputtering, or Ionized Metal Plasma (IMP) sputtering. As is well known in the art, in general, due to their anisotropic and directional (“line of sight”) nature, the PVD techniques produce non-conformal deposition. For a comprehensive description of sputtering techniques and their applications, see for example an article entitled “Sputter Deposition Processes” by R. Parsons, pp. 177–208 in Thin Film Processes II, edited by J. L. Vosen and W. Kern, Academic Press (1991). However, some of the PVD techniques (such as ion plating) may produce, under certain conditions, a relatively more conformal deposition. For a comprehensive description of the ion plating technique and its applications, see for example an article entitled “The Cathodic Arc Plasma Deposition of Thin Films” by P. C. Johnson, pp. 209–285 in Thin Film Processes II, edited by J. L. Vosen and W. Kern, Academic Press (1991). The CVD techniques include, for example and without limitation, thermal CVD, Plasma Enhanced CVD (“PECVD”), Low Pressure CVD (“LPCVD”), High Pressure CVD (“HPCVD”), Atomic Layer CVD (“ALCVD”), and Metallo Organic CVD (“MOCVD”). Atomic Layer Deposition or Alternating Layer Deposition (ALD) is generally considered to be a CVD (ALCVD) technique, or a particular variant thereof. However, it is sometimes referred to as a class by its own. Similar to other CVD techniques, the ALD techniques include particular variants such as, for example, Thermal ALD, Low Pressure ALD (LPALD) and Radical Assisted or Plasma Enhanced ALD (PEALD). In general, the ALD techniques produce more conformal deposits, at lower deposition temperatures, than other CVD techniques. However, the ALD techniques are generally much slower than the other CVD techniques. As defined herein, the term “ALD” refers to (and includes) all variants of the ALD techniques, such as, for example and without limitation, Thermal ALD or ALCVD, Low Pressure ALD (LPALD) and Radical Assisted or Plasma Enhanced ALD (PEALD). For a comprehensive description of CVD techniques and their applications, see for example an article entitled “Thermal Chemical Vapor Deposition” by K. F. Jensen and W. Kern, pp. 283–368 in Thin Film Processes II, edited by J. L. Vosen and W. Kern, Academic Press (1991). For example, one precursor used for CVD Cu is Cupraselect™, which precursor is sold by Schumacher, Inc. Another precursor is Cu(II) hexafluoroacetylacetonate. The latter can be reacted with hydrogen gas to obtain high purity copper. As is well known in the art, in general, due to their isotropic and non-directional nature, the CVD (and ALD) and the electroless techniques produce conformal deposition, with substantially uniform thickness over the entire surface, including over the field and the bottom and sidewall surfaces of the openings. However, under certain conditions, some of the CVD (and ALD) techniques (such as PECVD or PEALD) can be made to deposit less conformal or non-conformal layers.
[0009] Aspect ratio (“AR”) is typically defined as a ratio between a vertical dimension, D (depth), of an opening and its smallest lateral dimension, W (width, or diameter): AR=D/W. Usually, in electroplating metals or alloys to fill patterns having high aspect ratio openings (for example, in an insulator or a dielectric), the electroplating rate inside openings is slower than the rate outside openings (i.e., on the field). Further, the higher the AR of the openings, the slower the electroplating rate is inside. This results in poor or incomplete filling (voids) of high AR openings, when compared with results achieved with low AR openings. To overcome this problem in the prior art, commercial copper electrolytes contain additives that adsorb and locally inhibit (or suppress) growth outside the openings (i.e., on the field). Further, growth inhibition inside the openings is decreased from that achieved outside the openings due to slow replenishment of the additives inside the openings as compared with replenishment of the additives on the field. As a result, the deposition rate inside the openings is faster than outside, thereby facilitating void-free copper fill. Other well known reasons for voids in copper electrofill include discontinuous (or incomplete coverage of) seed layers inside the openings, and pinching-off of opening walls (for example, by overhangs of the top corners) prior to plating.
[0010] The openings may consist of vias, trenches, or patterned photoresist. As is well known, in damascene or dual damascene processes, an insulating or a dielectric layer is pattern-etched to form openings therein. Next, a barrier (or an adhesion) metallic layer and a seed layer are deposited over the insulating layer to metallize its field (the surface surrounding openings), as well as the sidewalls and bottom surfaces of the openings. Next, copper electroplating is performed over the entire metallized surface, including the top surface (the field) surrounding the openings, and inside the patterned openings. Finally, excess plated copper overlying the openings and the top surface (the field) of the insulating layer, as well as the barrier and seed layers on the field, are removed, for example, by a mechanical polishing or by a chemical mechanical polishing (“CMP”) technique. The end result is copper filled openings (trenches and vias), including bottom and sidewall surfaces lined by the barrier and seed layers. In today's most advanced copper filling processes for trenches and vias, the openings have ARs as high as 7:1 (D=1.4 μm; W=0.2 μm). Future trenches and vias openings will likely require W=0.10–0.13 μm, or narrower, and AR=8:1–20:1, or larger.
[0011] As semiconductor device dimensions continue to shrink, there is an ever increasing demand for narrower interconnect cross-sections and, thus, smaller openings and larger aspect ratios (AR) during the copper electrofill. To ensure void-free copper filling, the seed layer inside the openings must completely cover the bottom and the sidewall surfaces inside the openings without discontinuities, or else there will be voids in the copper electrofill. On the other hand, the seed layer must not be so thick on the sidewalls that it pinches-off or seals the very narrow openings and should not overhang the top corners of the openings. It should leave enough room inside the small openings for a successive electrofilling step. In contrast to these requirements with respect to the openings, the seed layer must be sufficiently thick on the top surface (the field) to provide a low-resistive electrical path that facilitates uniform plating across the surface of the wafer. That is, the seed layer must be sufficiently thick (for example, a Cu seed layer thickness is preferably at least about 1,000 Å) on the field to avoid radial non-uniformity across the wafer caused by a voltage (or IR) drop between a contact at the edge of the wafer to the center of the wafer. Any voltage drop (and resulting non-uniformity therefrom) becomes more severe with increasing wafer size (200 mm to 300 mm), and as the resistance of the seed layer increases due to insufficient thickness and/or high resistivity. To ensure a sufficiently low-resistance seed layer, it is now common to deposit a copper seed layer to a thickness of about 1,000 Å to about 2,000 Å on the top surface (field) by a PVD technique. However, the typical conformal seed layer thickness of about 300 Å to about 800 Å (on the field), deposited by the CVD or electroless techniques, may not be sufficient.
[0012] Neither of these techniques satisfies all of the above-identified requirements. The non-conformal PVD techniques, while providing adequate thickness on the field, fail to provide continuous and complete sidewall and/or bottom coverage inside very narrow openings with large AR. They also result in substantial overhangs at the top corners of the openings. The conformal techniques (such as CVD, ALD, or electroless), on the other hand, while providing continuous and complete sidewalls and bottom coverage of the seed layer inside very narrow openings, pinch-off or seal the small openings when used at thicknesses required on the field for a low-resistance electrical path. As a result, typical conformal seed layers are too thin on the field and too thick inside the very narrow openings.
[0013] As one can readily appreciate from the above, a need exists in the art for a method and apparatus to produce a continuous seed layer on the sidewalls and bottom of the openings, while maintaining sufficient thickness on the field to facilitate good uniformity across the wafer and void-free copper electrochemical filling of very narrow openings having high aspect ratios.
Summary of the Invention
[0014] Embodiments of the present invention advantageously satisfy the above-identified need in the art and provide multiple seed layer structures used to produce void-free copper or silver interconnect by electrochemical filling of small openings having high aspect ratios.
[0015] One embodiment of the present invention is a method for making metallic interconnects, which method is utilized at a stage of processing a substrate having a patterned insulating layer which includes at least one opening and a field surrounding the at least one opening, the field and the at least one opening being ready for depositing one or more seed layers, which method comprises steps of: (a) depositing by an ALD technique at least an initial portion of a substantially conformal seed layer on the field and inside surfaces of the at least one opening, wherein said at least one opening has a width of less than about 0.13 μm; (b) depositing by a PVD technique a substantially non-conformal seed layer over the substantially conformal seed layer, said substantially non-conformal seed layer being thicker than said substantially conformal seed layer over the field; and (c) electroplating a metallic layer over the substantially non-conformal seed layer, wherein the electroplated metallic layer comprises a material selected from a group consisting of Cu, Ag, or alloys comprising one or more of these metals.
Brief Description of the Figures
[0016] FIG. 1 shows a cross-sectional view of an inventive structure formed in accordance with one embodiment of the present invention wherein a first, substantially conformal seed layer is deposited over a barrier layer, followed by a second, substantially non-conformal seed layer deposited over the first, conformal seed layer;
[0017] FIG. 2 shows a cross-sectional view of the inventive structure of FIG. 1 after removing excess plated copper or silver overlying an opening and the field, as well as removing the seed layers and barrier layer overlying the field surrounding the opening;
[0018] FIG. 3 shows a cross-sectional view of an inventive structure formed in accordance with an alternative embodiment of the present invention wherein a first, substantially non-conformal seed layer is deposited over a barrier layer, followed by a second, substantially conformal seed layer deposited over the first, non-conformal seed layer;
[0019] FIG. 4 shows a cross-sectional view of the inventive structure of FIG. 3 after removing excess plated copper or silver overlying an opening and the field, as well as removing the seed layers and barrier layer overlying the field surrounding the opening;
[0020] FIG. 5 shows a scanning electron microscope (“SEM”) photograph of a cleaved cross-section (with a tilt angle of 30°) of a trench (the trench is ˜0.10 μm wide, ˜1.4 μm deep, and has an aspect ratio of ˜14:1) having seed layers formed in accordance with one embodiment of the present invention;
[0021] FIG. 6 shows an SEM photograph of the trench shown in FIG. 5 without a tilt, and with a larger enlargement; and
[0022] FIG. 7 shows a schematic (not to scale) top view of a cluster tool apparatus, and a frontal view of its controller (e.g. computer), in accordance with other embodiments of the invention.
Detailed Description
[0023] FIG. 1 shows a cross-sectional view of an inventive structure formed in accordance with one embodiment of the present invention wherein a substantially conformal seed layer is deposited over a barrier layer, followed by a substantially non-conformal seed layer deposited over the substantially conformal seed layer. As defined herein, a “substantially conformal seed layer” is a layer whose thickness on the sidewalls of an opening (at about mid-depth) is about 25–100% of its thickness on the field. Similarly, a “substantially non-conformal seed layer” is defined herein as a layer whose thickness on the sidewalls of an opening (at about mid-depth) is less than about 25% of its thickness on the field. In accordance with this embodiment, the conformal seed layer provides step coverage inside the openings 16, while the non-conformal seed layer provides a low resistance electrical path over the top surface (field 14) surrounding the openings to enable uniform plating across the substrate (or wafer). As defined herein, sidewall or step coverage means continuous sidewall coverage, and conformal and non-conformal seed layers, respectively, mean substantially conformal and substantially non-conformal seed layers, respectively. To enable uniform plating, it is preferable that the thickness of the combined seed layers be at least about 1,000 Å on the field. However, the combined thickness of the seed layers on the sidewalls should be thin enough to avoid pinching-off or sealing the openings and should leave enough room inside the openings for a successive electrofilling step.
[0024] Narrow openings (e.g., 0.18 μm, or narrower), with large aspect ratios, require minimization of the conformal seed layer thickness. On one hand, the conformal seed layer must be sufficiently thick to ensure adequate sidewall coverage and, on the other hand, it must not be too thick, to pinch-off the opening. In such cases, in order to provide sufficient thickness of the combined seed layers on the field (this is required to provide adequate electrical conduction on the field), the thickness of the non-conformal seed layer (on the field) may need to exceed the thickness of the conformal seed layer (on the field). In wider openings, with smaller aspect ratios, the thickness of the non-conformal seed layer may, or may not, exceed the thickness of the conformal seed layer (on the field).
[0025] In accordance with this embodiment of the present invention, barrier layer 18 is deposited over the entire surface of wafer 10, including over patterned insulating layer 12 (having had opening 16 patterned therein in accordance with any one of a number of methods that are well known to those of ordinary skill in the art), using a conformal Chemical Vapor Deposition (“CVD”) technique. Although the term barrier layer is used, it should be understood by those of ordinary skill in the art that the term barrier layer includes examples wherein: (a) the barrier layer acts both as an adhesion layer and as a barrier layer; (b) a barrier layer separate from an adhesion layer is used; and (c) a multiplicity of layers is used, some acting as adhesion layers, some acting as barrier layers, or some acting as both. Further, although the term wafer is used, this also includes the term substrate as it is used in the art. Still further, although the present invention is described in the context of opening 16, in practice, a multiplicity of openings are patterned and filled in accordance with the present invention.
[0026] Advantageously, in accordance with the present embodiment, the use of a conformal CVD (preferably ALD) technique to deposit barrier layer 18 ensures substantially complete and continuous coverage of sidewall surfaces inside opening 16. However, it is within the scope of the present invention that barrier layer 18 may also be deposited using a Physical Vapor Deposition (“PVD”) technique that provides substantially continuous sidewall coverage. In accordance with the present invention, barrier layer 18 may comprise, for example and without limitation, a material selected from Ta, TaNX, Cr, CrNX, Ti, TiNX, W, WNX, TaSiXNY, TiSiXNY, WSiXNY, and other alloys containing one or more of these materials. Further, the thickness of barrier layer 18 can be in a range of about 30 Å to about 500 Å, and more preferably in a range of about 50 Å to about 300 Å. Since barrier layer 18 occupies a certain fraction of interconnects formed in accordance with the present invention, and since barrier layer 18 has a relatively large resistivity, its thickness should be minimized. However, the thickness of barrier layer 18 should be sufficiently large to mitigate copper out-diffusion and to provide continuous sidewall coverage inside opening 16. Many CVD techniques and PVD techniques are well known to those of ordinary skill in the art for forming barrier layer 18.
[0027] Next, substantially conformal seed layer 20 is deposited over barrier layer 18. Conformal seed layer 20 can be preferably deposited by using a CVD or an ALD technique, but it can also be deposited by using an electroless technique or any other substantially conformal deposition technique. Many CVD techniques and electroless techniques are well known to those of ordinary skill in the art for forming conformal seed layer 20. For example and without limitation, the CVD techniques may include thermal CVD, Plasma Enhanced CVD (“PECVD”), Low Pressure CVD (“LPCVD”), High Pressure CVD (“HPCVD”), Atomic Layer CVD (ALCVD), and Metallo Organic CVD (“MOCVD”). Atomic Layer Deposition (ALD) is generally considered to be a CVD technique, or a particular variant thereof. As defined herein, the term “ALD” refers to (and includes) all variants of the ALD techniques, such as, for example and without limitation, ALCVD, Low Pressure ALD (LPALD) and Plasma Enhanced ALD (PEALD). The thickness of conformal seed layer 20 can be in a range of about 20 Å to about 500 Å, preferably in a range of about 50 Å to about 500 Å, and more preferably in a range of about 100 Å to about 300 Å. Finally, substantially non-conformal seed layer 22 is deposited over conformal seed layer 20. Non-conformal seed layer 22 can be preferably obtained using a PVD technique. Many PVD techniques are well known to those of ordinary skill in the art for forming non-conformal seed layer 22. For example and without limitation, the PVD techniques include, evaporation, ion plating, and various sputtering techniques. Sputtering techniques may include, for example and without limitation, techniques such as DC and/or RF plasma sputtering, bias sputtering, collimated sputtering, magnetron sputtering, Hollow Cathode Magnetron (HCM) sputtering, Self Ionized Plasma (SIP) sputtering, or Ionized Metal Plasma (IMP) sputtering. The thickness of non-conformal seed layer 22 can be in a range of about 100 Å to about 3,000 Å, and more preferably in a range of about 500 Å to about 2,000 Å (on the field).
[0028] In accordance with the present invention, the conformal and non-conformal seed layers may comprise the same material, or they may comprise different materials. Although copper is commonly used as a seed layer, a highly conductive silver (Ag) layer can also be used. In fact, Ag has lower resistivity than that of Cu and, therefore, can be formed with a smaller thickness than that required when using Cu. Thus, conformal seed layer 20 and non-conformal seed layer 22 may comprise, for example, a material selected from Cu, Ag, or alloys comprising one or more of these metals.
[0029] Those of ordinary skill in the art will readily understand that, although the above-described structure comprises individual conformal and non-conformal seed layers 20 and 22, respectively, these individual layers may not be discernible or distinguishable from each other in the structure after complete fabrication of the seed layers, particularly if they are comprised of the same metal or alloy.
[0030] Due to the non-directional, isotropic nature of CVD deposition techniques, the thickness of the CVD layers is substantially uniform over the entire surface (i.e., conformal), including over field 14, and over bottom and sidewall surfaces inside opening 16. In reality, however, even the best conformal CVD layers are thicker over the field than inside the openings. In fact, it is quite common for CVD Cu seed layers inside openings to have a thickness of about 80% of that over the field. Also, the thickness of a typical CVD barrier layer inside the openings may only be ˜50% of that over the field. Thus, even the best CVD layers exhibit some overhangs at the top corners of the openings.
Example 1
[0031] The following presents an example of an embodiment of the inventive method for 0.18 μm wide vias or trenches. In accordance with this embodiment, one deposits, by a CVD technique, a barrier layer comprised of about 200 Å of TaNX or WNX, then one deposits, by a CVD technique, a conformal seed layer comprised of about 300 Å of Cu, finally one deposits, by a PVD technique, a non-conformal seed layer comprised of about 900 Å of Cu (as measured on the field). This will result in a total combined (including the barrier) thickness of about 400 Å inside the openings: {Cu(PVD˜50 Å)/Cu(CVD˜250 Å)/TaNx(CVD˜100 Å)} and a total combined Cu seed layers and barrier layer thickness of about 1,400 Å on the field: {Cu(PVD˜900 Å)/Cu(CVD˜300 Å)/TaNx(CVD˜200 Å}. Advantageously, in accordance with the present invention, the inventive “two-step” seed layer deposition ensures a continuous seed layer having excellent step coverage, and a low-resistance electrical path on the field to ensure uniform copper plating across the wafer. It may be noted that although the combined thickness of the copper seed layers inside the openings is only about 300 Å, due to the very short distance to the field (on the order of about 1 μm), the voltage drop from the field to the inside of the openings is negligible. Thus, the combined thickness of the “two-step” seed layers inside the openings is adequate for copper plating therein. In fact, if necessary, the combined thickness of the “two-step” seed layers inside the openings can be further decreased (to a range from about 20 Å to about 200 Å, and preferably to a range from about 100 Å to about 200 Å) to enable void-free copper filling of even narrower openings (for example, below 0.10–0.13 μm). In the above example, the combined thicknesses of the barrier and seed layers at the sidewalls of the openings is about 400 Å on each side, thus occupying about 800 Å of the 1,800 Å opening. This leaves enough room (˜1,000 Å), without sealing or pinching-off of the top corners, to facilitate electroplating inside the openings.
[0032] In accordance with a preferred embodiment of the present invention, substantially non-conformal seed layer 22 is thicker than substantially conformal seed layer 20 on the field 14, thereby providing most of the field conduction.
[0033] After depositing seed layers 20 and 22 shown in FIG. 1 , substrate 10 is placed in a copper electroplating bath, and electroplating is carried out in accordance with any one of a number of methods that are well known to those of ordinary skill in the art to deposit a thickness of copper sufficient to fill patterned opening 16, with some excess, and to cover field 14 surrounding opening 16. Finally, excess plated copper overlying opening 16 and overlying field 14, as well as seed layers 20 and 22 and barrier layer 18 overlying field 14, are removed using any one of a number of techniques that are well known to those of ordinary skill in the art, for example, using a mechanical polishing or a chemical mechanical polishing (CMP) technique. Other removal techniques, such as wet etching techniques (chemical, electrodissolution, or electropolishing) or dry etching techniques (ion milling, reactive ion etching or RIE, or sputter etching) may also be used to remove excess plated copper overlying opening 16 and field 14, and to remove seed layers 20 and 22 and barrier metallic layer 18 overlying field 14. It should be clear to those of ordinary skill in the art that removal may also be accomplished using a combination of techniques, including those identified above.
[0034] Although the detailed description above refers to filling opening 16 by electroplating copper, it is within the scope of the present invention to electrofill opening 16 with any low resistivity material, such as a material selected from Cu, Ag, or an alloy comprising one or more of these metals. In fact, silver (Ag) has lower resistivity than that of Cu, and may be attractive for further reducing the dimensions of the interconnects.
[0035] FIG. 2 shows a cross-sectional view of the inventive structure of FIG. 1 after removing excess plated copper (or silver) 24 overlying opening 16 and field 14, and removing seed layers 20 and 22 and barrier layer 18 overlying field 14 surrounding opening 16. FIG. 2 illustrates the filling of openings (trenches and vias) with electroplated copper (or silver) 24, as well as the lining of the bottom and sidewall surfaces of opening 16 by barrier layer 18 and seed layers 20 and 22. As shown in FIG. 2 , all metallic layers were removed from field 14 of insulating layer 12 which surrounds embedded electroplated copper (or silver) interconnect 24.
[0036] Those of ordinary skill in the art will readily understand that, although the above-described structure comprises metal (or alloy) layer 24 electroplated over separately deposited conformal and non-conformal seed layers 20 and 22, respectively, following the electroplating of the metallic layer 24, these individual layers may not be discernible or distinguishable from each other in the structure, particularly if they are comprised of the same metal or alloy. Thus for example, if seed layers 20 and 22 and electroplated metal 24 are comprised of Cu, they may not be discernible from each other inside the filled openings 16, or on field 14 (prior to their removal from the field).
[0037] FIG. 3 shows a cross-sectional view of an inventive structure formed in accordance with an alternative embodiment of the present invention wherein a first, substantially non-conformal seed layer is deposited over a barrier layer, followed by a second, substantially conformal seed layer deposited over the first, non-conformal seed layer. The non-conformal seed layer provides a low resistance electrical path over the top surface (field 114) surrounding the openings 116 to enable uniform plating across the substrate (or wafer), while the conformal seed layer provides continuous and complete bottom and sidewalls (or step) coverage inside the openings.
[0038] In accordance with the alternative embodiment of the inventive method of the present invention, barrier layer 118 is deposited over the entire surface of wafer 110, including over patterned insulating layer 112 (having had opening 116 patterned therein in accordance with any one of a number of methods that are well known to those of ordinary skill in the art), using a conformal Chemical Vapor Deposition (“CVD”) technique. Although the term barrier layer is used herein, it should be understood by those of ordinary skill in the art that the term barrier layer includes examples wherein: (a) the barrier layer acts both as an adhesion layer and as a barrier layer; (b) a barrier layer separate from an adhesion layer is used; and (c) a multiplicity of layers is used, some acting as adhesion layers, some acting as barrier layers, or some acting as both. Further, although the term wafer is used, this also includes the term substrate as it is used in the art. Still further, although the present invention is described in the context of opening 116, in practice, a multiplicity of openings are patterned and filled in accordance with the present invention.
[0039] Advantageously, in accordance with the present embodiment, the use of a conformal CVD (preferably ALD) technique to deposit barrier layer 118 ensures complete and continuous coverage of sidewall surfaces inside opening 116. However, it is within the scope of the present invention that barrier layer 118 may also be deposited using a Physical Vapor Deposition (“PVD”) technique that provides substantially continuous sidewall coverage. In accordance with the present invention, barrier layer 118 may comprise, for example and without limitation, a material selected from Ta, TaNX, Cr, CrNX, Ti, TiNX, W, WNX, TaSiXNY, TiSiXNY, WSiXNY, and other alloys containing one or more of these materials. Further, the thickness of barrier layer 118 can be in a range of about 30 Å to about 500 Å, and more preferably in a range of about 50 Å to about 300 Å. Since barrier layer 118 occupies a certain fraction of interconnects formed in accordance with the present invention, and since barrier layer 118 has a relatively large resistivity, its thickness should be minimized. However, the thickness of barrier layer 118 should be sufficiently large to mitigate copper out-diffusion and to provide continuous sidewall coverage inside opening 116. Many CVD techniques and PVD techniques are well known to those of ordinary skill in the art for forming barrier layer 118.
[0040] Next, a substantially non-conformal seed layer 126 is deposited over barrier layer 118. Non-conformal seed layer 126 can be preferably obtained using a PVD technique. Many PVD techniques are well known to those of ordinary skill in the art for forming non-conformal seed layer 126. For example and without limitation, the PVD techniques may include, evaporation, ion plating, and various sputtering techniques. Sputtering techniques include, for example and without limitation, techniques such as DC and/or RF plasma sputtering, bias sputtering, collimated sputtering, magnetron sputtering, Hollow Cathode Magnetron (HCM) sputtering, Self Ionized Plasma (SIP) sputtering, or Ionized Metal Plasma (IMP) sputtering. The thickness of non-conformal seed layer 126 can be in a range of about 100 Å to about 3,000 Å, and more preferably in a range of about 500 Å to about 2,000 Å (on the field). Finally, a substantially conformal seed layer 128 is deposited over non-conformal seed layer 126. Conformal seed layer 128 can be preferably obtained using a CVD or an ALD technique, or electroless technique, or any other substantially conformal deposition technique. Many CVD techniques and electroless techniques are well known to those of ordinary skill in the art for forming conformal seed layer 128. For example and without limitation, the CVD techniques may include thermal CVD, Plasma Enhanced CVD (“PECVD”), Low Pressure CVD (“LPCVD”), High Pressure CVD (“HPCVD”), Atomic Layer CVD (ALCVD), and Metallo Organic CVD (“MOCVD”). Atomic Layer Deposition (ALD) is generally considered to be a CVD technique, or a particular variant thereof. As defined herein, the term “ALD” refers to (and includes) all variants of the ALD techniques, such as, for example and without limitation, ALCVD, Low Pressure ALD (LPALD) and Plasma Enhanced ALD (PEALD). The thickness of conformal seed layer 128 can be in a range of about 20 Å to about 500 Å, preferably in a range of about 50 Å to about 500 Å, and more preferably in a range of about 100 Å to about 300 Å.
[0041] In accordance with a preferred embodiment of the present invention, substantially non-conformal seed layer 126 is thicker than substantially conformal seed layer 128 on the field 114, thereby providing most of the field conduction.
[0042] In accordance with the present invention, the conformal and non-conformal seed layers may comprise the same material, or they may comprise different materials. Although copper is commonly used as a seed layer, a highly conductive silver (Ag) layer can also be used. Non-conformal seed layer 126 and conformal seed layer 128 may comprise, for example, a material selected from Cu, Ag, or alloys comprising one or more of these metals.
[0043] Although reference is made here to individual non-conformal and conformal seed layers 126 and 128, respectively, it should be understood by those of ordinary skill in the art that, following the deposition of these seed layers, they may not be discernible or distinguishable from each other, particularly if they are comprised of the same metal or alloy.
[0044] After depositing seed layers 126 and 128 shown in FIG. 3 , substrate 110 is placed in a copper electroplating bath, and electroplating is carried out in accordance with any one of a number of methods that are well known to those of ordinary skill in the art to deposit a thickness of copper sufficient to fill patterned opening 116, with some excess, and to cover field 114 surrounding opening 116. Finally, excess plated copper overlying opening 116 and field 114 of insulating layer 112, as well as seed layers 126 and 128 and barrier layer 118 overlying field 114, are removed using any one of a number of techniques that are well known to those of ordinary skill in the art, for example, using a mechanical polishing or a chemical mechanical polishing (CMP) technique. Other removal techniques, such as wet etching techniques (chemical, electrodissolution, or electropolishing) or dry etching techniques (ion milling, reactive ion etching or RIE, or sputter etching) may also be used to remove excess plated copper overlying opening 116 and field 114, and to remove seed layers 126 and 128 and barrier layer 118 overlying field 114. It should be clear to those of ordinary skill in the art that removal may also be accomplished using a combination of techniques, including those identified above.
[0045] Although the detailed description above refers to filling opening 116 by electroplating copper, it is within the scope of this invention to electrofill opening 116 with any low resistivity material, such as a material selected from Cu, Ag, or alloys comprising one or more of these metals. In fact, silver (Ag) has lower resistivity than that of Cu, and may be attractive for further reducing the dimensions of the interconnects.
[0046] FIG. 4 shows a cross-sectional view of the inventive structure of FIG. 3 after removing excess electroplated copper (or silver) 130 overlying opening 116 and field 114, and removing seed layers 126 and 128 and barrier layer 118 overlying field 114 surrounding opening 116. FIG. 4 illustrates the filling of openings (trenches and vias) with electroplated copper (or silver) 130, as well as the lining of the bottom and sidewall surfaces of opening 116 by barrier layer 118 and seed layers 126 and 128. As shown in FIG. 4 , all metallic layers were removed from field 114 of insulating layer 112 which surrounds embedded electroplated copper (or silver) interconnect 130.
[0047] Although reference is made here to individual electroplated metal or alloy 130 over seed layers 126 and 128, it should be understood by those of ordinary skill in the art that, following the electroplating of metallic layer 130, the individual layers may not be discernible or distinguishable from each other, particularly if they are comprised of the same metal or alloy. Thus for example, if seed layers 126 and 128 and electroplated metal 130 are comprised of Cu, they may not be discernible from each other inside the filled openings 116, or on field 114 (prior to their removal from the field).
Example 2
[0048] FIGS. 5 and 6 show scanning electron microscope (“SEM”) photographs of a cross-section of a 0.10 μm wide trench having Cu seed layers prepared in accordance with one embodiment of the invention. In accordance with this embodiment, a pattern of trenches was formed in a SiO2 insulating layer. The trenches were about 0.10 μm wide (at their bottom) and about 1.4 μm deep (thereby having an aspect ratio of about 14:1). Next, a barrier layer (WNX) was deposited using a CVD technique. Next, a relatively thin, conformal Cu seed layer was deposited using a CVD technique. The barrier layer and thin, conformal Cu seed layer is seen at 501 in FIG. 6 . In accordance with this embodiment, the combined thickness of the barrier and the CVD Cu seed layer was about 500 Å on the field, and about 400–500 Å on the sidewalls and bottom of the trenches. Next, a non-conformal PVD Cu seed layer having a thickness of about 1,400 Å (on the field) was deposited by sputtering. In this embodiment, the non conformal PVD Cu seed layer was applied in two steps and is seen at 510 in FIG. 6 . The end result, as shown in FIGS. 5 and 6 , was a combined thickness (including the barrier and the Cu seed layers) of only about 400–500 Å on the sidewalls and bottom of the trench (with excellent continuity and uniformity there), and about 1,900 Å on the field, without pinching-off of the trench. One should note that, while FIG. 5 shows the cross-section with a tilt of about 30° and an enlargement of 20,000× (thus providing also a partial view of the top surface), FIG. 6 shows the same cross-section with an enlargement of 40,000× and without a tilt.
Example 3
[0049] Similar to Example 2 above, trenches ˜0.10 μm wide (at their bottom) and ˜1.4 μm deep (thereby having an aspect ratio of ˜14:1) were formed in a SiO2 insulating layer. Next, a barrier layer (WNX) was deposited using a CVD technique. Next, a relatively thin, conformal Cu seed layer was deposited using a CVD technique. The combined thickness of the barrier layer and the CVD Cu layer was ˜500 Å on the field, and ˜400–500 Å on the sidewalls and bottom of the trenches. Next, a non-conformal PVD Cu seed layer having a thickness of ˜500 Å (on the field) was deposited by sputtering. The end result was a combined thickness (including the barrier layer and the Cu seed layers) of only about 400–500 Å on the sidewalls and bottom of the trenches (with excellent continuity and uniformity there), and about 1,000 Å on the field, without pinching-off the trenches.
[0050] It should be understood that the scope of the present invention is not limited to the embodiments described above with respect to FIG. 1 and FIG. 3 . For example, in accordance with further embodiments of the present invention, a relatively thin (50–300 Å) “Flash” PVD seed layer can be deposited first, followed by a relatively thin (20–300 Å) conformal CVD (preferably ALD) or electroless seed layer, and finally followed by a relatively thick (300–2,000 Å) PVD seed layer to produce three separately deposited seed layers. The relatively thick top PVD seed layer is preferably deposited under conditions which minimize overhangs at the top corners of the openings.
[0051] Adhesion of a metallo-organic CVD (MOCVD) deposited Cu seed layer to the underlying barrier layer is rather poor, and may not be adequate for use in devices when mechanical or chemical mechanical polishing (CMP) processing follows Cu plating. In addition, when an MOCVD Cu layer is deposited directly over a barrier layer containing a refractory metal, further problems arise. In particular, the morphology, uniformity, and electrical resistivity of the MOCVD Cu layer may not be adequate for use in devices. It is believed that these problems are due to the high affinity of the refractory metal in the barrier layer to oxygen and/or carbon atoms. Specifically, during the initial stages of MOCVD Cu deposition, the refractory metal of the barrier layer spontaneously reacts with carbon or oxygen containing species (from the organic part of the metallo-organic compound) to form an oxide, carbide, or a mixed oxide-carbide interfacial layer between itself and the depositing Cu. Such an interfacial layer adversely impairs the adhesion of the MOCVD Cu layer. Cu (as well as other noble metals) does not adhere well to oxide or carbide layers, and requires a clean metal-to-metal bond in order to adhere well to another metal. Similarly, the oxide, carbide, and/or oxide-carbide interfacial layer impairs proper nucleation of the MOCVD Cu on the refractory metal barrier layer. This adversely affects the morphology, uniformity, and resistivity of the deposited MOCVD Cu seed layer.
[0052] In accordance with one embodiment of the present invention, at least an initial stage of CVD or ALD Cu deposition is carried out utilizing high purity, inorganic Cu compounds (precursors), such as, for example and without limitation, compounds containing hydrogen and/or halogen atoms such as chlorides or fluorides, which do not contain oxygen or carbon atoms. The resulting clean metal-to-metal interface between a barrier layer containing a refractory metal and the depositing copper ensures good adhesion, morphology, uniformity, and low electrical resistivity of the CVD Cu layer. In a further embodiment, the entire CVD or ALD Cu layer can be deposited using the inorganic precursors. In a still further embodiment, only the initial stage of the CVD (or ALD) Cu is carried out using inorganic precursors, switching later to an MOCVD Cu deposition process, to form the rest of the CVD Cu layer.
[0053] In accordance with one embodiment of the present invention that solves the problems involved with the deposition of an MOCVD Cu layer on a barrier deposited layer containing a refractory metal, a first, relatively thin, “Flash” PVD seed layer is deposited to enhance adhesion to the barrier layer and/or to improve grain morphology and uniformity of a subsequently deposited CVD seed layer.
[0054] In another embodiment of the invention, an electroless deposited metal or alloy is first deposited on the barrier layer, followed by the CVD Cu seed layer. In another embodiment, following the deposition of the electroless metal or alloy on the barrier layer, a PVD Cu seed layer is deposited directly on the electroless deposited metal or alloy. In yet another embodiment, a relatively thick PVD Cu seed layer is first deposited on the barrier layer, followed by a relatively thin electroless Cu seed layer deposited over the PVD Cu seed layer. The electroless deposited metal or alloy may comprise a material selected from the group consisting of electroless deposited Cu, Au, Ag, Ni, Co, or an alloy comprising one or more of these metals. The thickness of this electroless deposited metal or alloy can be in the range of 10–500 Å, preferably in the range of 20–300 Å, and more preferably be in the range of 25–100 Å.
[0055] Exposure of wafers to the atmosphere during transport from one deposition chamber to another may cause deleterious oxidation and/or contamination of the surface of barrier and/or seed layers. Such exposure should, therefore, be avoided or minimized.
[0056] In accordance with one embodiment of the present invention, conformal and non-conformal seed layers are deposited in an apparatus where the conformal and non-conformal seed layer deposition steps can be carried out without breaking vacuum, or without exposing the wafer to the atmosphere between the deposition steps. In accordance with this embodiment, the apparatus may comprise two or more chambers, at least one chamber for deposition of the conformal seed layer, and at least another chamber for deposition of the non-conformal seed layer. In a preferred embodiment of the present invention, the apparatus further comprises a chamber for deposition of the barrier layer, preferably by a CVD or ALD technique. The barrier layer may be deposited in a separate chamber or it may be deposited in one of the chambers used to deposit either the conformal, or the non-conformal, seed layers.
[0057] FIG. 7 shows apparatus 7000 that is fabricated in accordance with a preferred embodiment of the invention. As shown in FIG. 7 , apparatus 7000 comprises cluster tool 70 which operates in accordance with input from controller 80 in a manner that is well known to those of ordinary skill in the art. As further shown in FIG. 7 , cluster tool 70 includes input loadlock 71 and output loadlock 72. As is well known to those of ordinary skill in the art, loadlocks 71 and 72 enable wafers to be inserted into and removed from cluster tool 70, respectively. Although FIG. 7 shows separate input and output loadlocks, it is also within the spirit and scope of the present invention to use a single loadlock for both input and output of wafers.
[0058] As is well known to those of ordinary skill in the art, once wafer 74 is inserted into transfer chamber 73 of cluster tool 70, it can be transferred between the various processing chambers (for example, processing chambers 75–79) without breaking vacuum, or without exposure to the atmosphere. As is shown in FIG. 7 , cluster tool 70 comprises CVD or ALD barrier layer deposition chamber 76, PVD Cu seed layer deposition chamber 77, and CVD or ALD Cu seed layer deposition chamber 78. In addition, FIG. 7 shows several other processing chambers, for example, processing chambers 75 and 79, which can be used for other processing steps that are well known to those of ordinary skill in the art, such as pre-cleaning, cooling, or as extra deposition chambers. Although FIG. 7 shows separate CVD (or ALD) chambers for depositing a barrier layer and Cu seed layers, it is also within the scope of the invention to deposit both types of layers in the same CVD (or ALD) chamber.
[0059] Controller 80 is an apparatus which is well known to those of ordinary skill in the art, that is used to control the operation of cluster tool 70. As such, controller 80 determines the sequence and duration of movements and stays of wafer 74: (a) to and from loadlocks 71 and 72; and (b) to and from the various processing chambers 75–79. As is also well known to those of ordinary skill in the art, controller 80 controls the specific process sequence and process parameters for operation of the various ones of processing chambers 75–79, sometimes referred to in the art as “recipes.” For example, in PVD Cu seed layer deposition chamber 77, among other things, controller 80 controls the duration of the sputter deposition, the background pressure, the sputtering gas (such as Argon) pressure and flow rate, the cathodic voltage and power, and/or bias voltage applied to the wafer. Lastly, as is also well known to those of ordinary skill in the art, controller 80 performs these functions in accordance with specific recipes which are data structures that dictate the operation of controller 80 software. The data structures are typically stored on computer readable media that are input to controller 80 under the control of operation software, which operation software itself is typically stored on a computer readable medium. In accordance with a preferred embodiment of the present invention, recipes are input to controller 80 to cause it to control cluster tool 70 to process wafers in the manner described above to deposit a barrier layer and Cu seed layers without breaking vacuum or exposing a wafer to the atmosphere.
[0060] In one embodiment of the present invention, the apparatus comprises a chamber in which both conformal and non-conformal seed layers are deposited utilizing: (a) two or more distinct steps, wherein the deposition variables (or conditions or parameters) during the first step are suitable for the deposition of a substantially conformal (or a non-conformal) seed layer, and the deposition conditions during the second step are suitable for the deposition of a substantially non-conformal (or a conformal) seed layer; (b) wherein at least one of the deposition variables is varied (or ramped) continuously or gradually, thereby changing the nature of the seed layer from substantially conformal to substantially non-conformal, or vice versa; or (c) a combination of at least one distinct step of depositing a substantially conformal (or a non-conformal) seed layer and at least one gradual variation (or ramping) of at least one deposition variable towards a substantially non-conformal (or a conformal) seed layer, and vice versa.
[0061] As is well known to those of ordinary skill in the art, the nature of certain deposition techniques, such as ion plating or other PVD techniques, can be made more conformal, or less conformal, by varying the deposition parameters (or variables, or conditions). For example, increasing the (partial) pressure during ion plating and other PVD techniques, tends to increase scattering of the depositing atoms (or ions), thereby making the deposition more isotropic and conformal. Similarly, biasing the substrate has an effect on the nature of the deposit. For example, in ionized metal plasma (IMP), self ionized plasma (SIP), hollow cathode magnetron (HCM), and ion plating deposition techniques, increasing the (negative) bias voltage further accelerates positive ions (of the depositing metal) towards the substrate, thereby improving the filling of small openings. At the same time, the higher (negative) bias also increases the removal rate (or back-sputtering) from the top corners of the openings and the field, thereby rendering the deposition to be more conformal. Conversely, decreasing the negative bias, or even using positive bias, can render the deposition to be less conformal. Deposition rate (or power density) can also affect the nature of the deposition.
[0062] Similarly, as is known to those of ordinary skill in the art, the nature of certain CVD techniques can be made less conformal, or more conformal, by changing the deposition variables. For example, increasing the substrate temperature tends to shift the deposition from a surface-reaction, rate-controlled deposition at low temperature, to a transport, rate-controlled deposition at higher temperature. As a result, increasing the substrate temperature tends to render the deposition to be less conformal. Conversely, decreasing the temperature, tends to render the deposition to be more conformal. Similarly, increasing the precursor and/or the reacting gas partial pressure (or flow rate) tends to shift the deposition to be a more surface-reaction, rate-controlled deposition, thereby tending to render the deposition to be more conformal. Conversely, decreasing the partial pressure and/or flow rate of the precursor and/or a reacting gas, tends to render the deposition to be a more transport, rate-controlled deposition and, therefore, less conformal. The plasma variables in PECVD, such as the power density, may also have significant effects on the nature of the deposition.
[0063] In accordance with one embodiment of the present invention, cluster tool 70 comprises the following chambers: a CVD (preferably ALD) deposition chamber for depositing a barrier layer (for example, Ta, TaNX, Cr, CrNX, Ti, TiNX, W, WNX, TaSiXNY, TiSiXNY, WSiXNY, and other alloys containing one or more of these materials); a PVD deposition chamber for depositing a PVD Cu seed layer; and a CVD (preferably ALD) deposition chamber for depositing a CVD (preferably ALD) Cu seed layer. Single wafers are transferred in-situ in cluster tool 70, from one chamber to another, without exposing the wafers to the atmosphere prior to the deposition of the top Cu seed layer. The CVD (preferably ALD) barrier and the CVD (preferably ALD) Cu seed layers can be deposited in the same CVD (or ALD) chamber by using different gases and chemistries for the respective layers. However, separate CVD (or ALD) chambers for each layer (i.e., the barrier and Cu layers) are preferred in order to minimize cross-contamination. Using cluster tool 70, cluster tool controller 80 would cause a deposition process such as the following to be carried out in accordance with a recipe specified, for example in the form of a data structure or software or program code: (a) (in accordance with a first portion of the data structure or a first portion of the software or computer code) introducing wafer 74 into CVD (preferably ALD) barrier layer deposition chamber 76 and depositing on wafer 74 a CVD (preferably ALD) barrier layer (about 200–400 Å thick) comprising Ta, TaNX, Cr, CrNX, Ti, TiNX, W, WNX, TaSiXNY, TiSiXNY, WSiXNY, and other alloys containing one or more of these materials or; (b) (in accordance with a second portion of the data structure or a first portion of software or computer code) transferring wafer 74 through transfer chamber 73, without exposing wafer 74 to the atmosphere, to PVD Cu seed layer deposition chamber 77 and depositing on wafer 74 a relatively thin (about 100–500 Å) “Flash” PVD Cu layer; (c) (in accordance with a third portion of the data structure or a first portion of software or computer code) transferring wafer 74 through transfer chamber 73, without exposing wafer 74 to the atmosphere, to CVD (or ALD) Cu seed layer deposition chamber 78 and depositing on wafer 74 a CVD (preferably ALD) Cu layer (about 100–500 Å thick); and (d) (in accordance with a fourth portion of the data structure or a first portion of software or computer code) transferring wafer 74 through transfer chamber 73, without exposing it to the atmosphere, to PVD Cu seed layer deposition chamber 77 and depositing on wafer 74 a relatively thick PVD Cu layer (about 500–2,000 Å thick). Other ancillary steps include introducing wafer 74 into and removing wafer 74 from cluster tool 70 through loadlocks 71 and 72, respectively.
[0064] Another embodiment of a two-step combination may include a first deposited CVD (preferably ALD) seed layer, followed by a relatively thick PVD seed layer. Similarly, a three-step combination may include a first deposited CVD (preferably ALD) seed layer, followed by a relatively thick PVD seed layer, and finally followed by a second deposited CVD (preferably ALD) seed layer. Other combinations may comprise even more steps in the deposition of the seed layer. In these embodiments, the two (or more) separately deposited seed layers may comprise the same metal or alloy or they may comprise, for example and without limitation, different materials chosen from Cu, Ag, or alloys comprising one or more of these metals.
[0065] It should be understood that the above-described embodiments can be used to fabricate any number of devices including, and without limitation, metallic interconnects in semiconductor devices, thin film heads, micromachined Microelectromechanical Systems (MEMS) devices, or interconnects in high density integrated circuit packages.
[0066] Although the description of the embodiments above has concentrated on metallic interconnect structures used to fabricate a device such as a semiconductor integrated circuit, these embodiments can also be used in the fabrication of other devices, such as thin film heads, micromachined Microelectromechanical Systems (MEMS) devices, or interconnects in high density integrated circuit packages.
[0067] Also, although some of the embodiments above describe the use of a barrier layer prior to the deposition of the conformal/non-conformal seed layers or prior to the deposition of the non-conformal/conformal seed layers, those skilled in the art will recognize that these descriptions are not intended to limit the invention. In particular, those skilled in the art will recognize that the invention includes any workpiece or substrate (having openings upon its surface) which is ready for the deposition of the inventive seed layers upon its surface and which may, or may not, include a barrier layer.
[0068] Those skilled in the art will recognize that the foregoing description has been presented for the sake of illustration and description only. As such, it is not intended to be exhaustive or to limit the invention to the precise form disclosed.
Claims
I claim:
1. A method for making metallic interconnects, which method is utilized at a stage of processing a substrate having a patterned insulating layer which includes at least one opening and a field surrounding the at least one opening, the field and the at least one opening being ready for depositing one or more seed layers, which method comprises steps of:
depositing by a CVD technique a substantially conformal seed layer over the field and inside surfaces of the at least one opening, wherein said at least one opening has a width of less than about 0.13 μm;
depositing by a PVD technique a second seed layer over the substantially conformal seed layer, wherein the substantially conformal and the second seed layers do not seal the at least one opening; and
electroplating a metallic layer over the second seed layer, wherein the electroplated metallic layer comprises a material selected from a group consisting of Cu, Ag, or alloys comprising one or more of these metals.
2. The method of claim 1 wherein at least one of said the substantially conformal seed layer and the second seed layer comprises one or more materials selected from a group consisting of Cu, Ag, or alloys comprising one or more of these metals.
3. The method of claim 1 wherein at least an initial stage of the depositing by a CVD technique utilizes one or more precursors comprising one or more inorganic copper compounds which do not contain oxygen or carbon atoms.
4. The method of claim 3 wherein the one or more inorganic copper compounds comprise copper halide compounds.
5. The method of claim 1 further comprising a step of depositing a barrier layer on the field and inside surfaces of the at least one opening prior to the step of depositing the substantially conformal seed layer.
6. The method of claim 1 wherein the PVD technique comprises one or more sputtering techniques selected from a group consisting of collimated sputtering, Hollow Cathode Magnetron (HCM) sputtering, Self Ionized Plasma (SIP) sputtering, and Ionized Metal Plasma (IMP) sputtering techniques.
7. The method of claim 1 wherein the substantially conformal seed layer has a thickness in a range of about 20 Å to about 300 Å over the field and the second seed layer has a thickness in a range of about 100 Å to about 2000 Å over the field.
8. The method of claim 1 wherein said at least one opening has a width of less than about 0.10 μm.
9. A method for making metallic interconnects, which method is utilized at a stage of processing a substrate having a patterned insulating layer which includes at least one opening and a field surrounding the at least one opening, the field and the at least one opening being ready for depositing one or more seed layers, which method comprises steps of:
depositing by a PVD technique a first seed layer over the substrate, said first seed layer has a thickness greater than about 250 Å over the field, and wherein said at least one opening has a width of less than about 0.13 μm;
depositing by a CVD technique a substantially conformal seed layer over the first seed layer, said wherein the substantially conformal and the first seed layers do not seal the at least one opening; and
electroplating a metallic layer over the substantially conformal seed layer, wherein the electroplated metallic layer comprises a material selected from a group consisting of Cu, Ag, or alloys comprising one or more of these metals.
10. The method of claim 9 wherein at least one of said first seed layer and the substantially conformal seed layer comprises one or more materials selected from a group consisting of Cu, Ag, or alloys comprising one or more of these metals.
11. The method of claim 9 wherein at least an initial stage of the depositing by a CVD technique utilizes one or more precursors comprising one or more inorganic copper compounds which do not contain oxygen or carbon atoms.
12. The method of claim 1 wherein the one or more inorganic copper compounds comprise copper halide compounds.
13. The method of claim 9 wherein the PVD technique comprises one or more sputtering techniques selected from a group consisting of collimated sputtering, Hollow Cathode Magnetron (HCM) sputtering, Self Ionized Plasma (SIP) sputtering, and Ionized Metal Plasma (IMP) sputtering techniques.
14. The method or claim 9 wherein the first seed layer has a thickness in a range of about 250 Å to about 2,000 Å over the field and the substantially conformal seed layer has a thickness in a range of about 20 Å to about 300 Å over the field.
15. The method of claim 9 wherein said at least one opening has a width of less than about 0.10 μm.
16. A method for making metallic interconnects, which method is utilized at a stage of processing a substrate having a patterned insulating layer which includes at least one opening and a field surrounding the at least one opening, the field and the at least one opening being ready for depositing one or more seed layers, which method comprises steps of:
depositing three or more seed layers over the field and inside surfaces of the at least one opening, wherein at least one seed layer is deposited by a CVD technique and at least one seed layer is deposited by a PVD technique, said three or more seed layers do not seal the at least one opening; and
electroplating a metallic layer over the three or more seed layer, wherein the electroplated metallic layer comprises a material selected from a group consisting of Cu, Ag, or alloys comprising one or more of these metals.
17. The method of claim 16 wherein at least one of the three or more seed layers comprises one or more materials selected from a group consisting of Cu, Ag, or alloys comprising one or more of these metals.
18. The method of claim 16 further comprising a step of depositing a barrier layer on the field and inside surfaces of the at least one opening prior to the steps of depositing the three or more seed layers.
19. The method of claim 16 wherein:
a first seed layer is deposited by a PVD technique over the substrate;
a second seed layer is deposited by a CVD technique over the first seed layer; and
a third seed layer is deposited by a PVD technique over the second seed layer, wherein the third seed layer being thicker than the first or second seed layers over the field, the three seed layers do not seal the at least one opening, and the at least one opening has a width of less than about 0.13 μm.
20. The method of claim 16 wherein at least two of the three or more seed layers are deposited by one or more CVD techniques.
21. The method of claim 19 wherein said first seed layer has a thickness in a range from about 50 Å to about 500 Å over the field, said second seed layer a thickness in a range from about 20 Å to about 300 Å over the field, and said third seed layer has a thickness in a range from about 300 Å to about 2,000 Å over the field.
Patent Citations (72)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US5091209(A) | 1992-02-01 | Claverie et al. | Examiner |
| US5151168(A) | 1992-09-01 | Gilton et al. | Applicant |
| US5173442(A) | 1992-12-01 | Carey | Applicant |
| US5219787(A) | 1993-06-01 | Carey et al. | Applicant |
| US5354712(A) | 1994-10-01 | Ho et al. | Applicant |
| US5403620(A) | 1995-04-01 | Kaesz et al. | Applicant |
| US5549808(A) | 1996-08-01 | Farooq et al. | Applicant |
| US5612254(A) | 1997-03-01 | Mu et al. | Applicant |
| US5693563(A) | 1997-12-01 | Teong | Applicant |
| US5882498(A) | 1999-03-01 | Dubin et al. | Applicant |
| US5897752(A) | 1999-04-01 | Hong et al. | Applicant |
| US5913145(A) | 1999-06-01 | Lu et al. | Applicant |
| US5969422(A) | 1999-10-01 | Ting et al. | Applicant |
| US6037258(A) | 2000-03-01 | Liu et al. | Applicant |
| US6042700(A) | 2000-03-01 | Gopalraja et al. | Applicant |
| US6066892(A) | 2000-05-01 | Ding et al. | Applicant |
| US6069068(A) | 2000-05-01 | Rathore et al. | Applicant |
| US6087711(A) | 2000-07-01 | Givens | Applicant |
| US6110828(A) | 2000-08-01 | Guo et al. | Applicant |
| US6136707(A) | 2000-10-01 | Cohen | Applicant |
| US6139697(A) | 2000-10-01 | Chen et al. | Applicant |
| US6169030(B1) | 2001-01-01 | Naik et al. | Applicant |
| US6174811(B1) | 2001-01-01 | Ding et al. | Applicant |
| US6181012(B1) | 2001-01-01 | Edelstein et al. | Applicant |
| US6184138(B1) | 2001-02-01 | Ho et al. | Applicant |
| US6187670(B1) | 2001-02-01 | Brown et al. | Applicant |
| US6197181(B1) | 2001-03-01 | Chen | Applicant |
| US6221765(B1) | 2001-04-01 | Ueno | Applicant |
| US6225221(B1) | 2001-05-01 | Ho et al. | Applicant |
| US6239021(B1) | 2001-05-01 | Pramanick et al. | Applicant |
| US6242349(B1) | 2001-06-01 | Nogami et al. | Applicant |
| US6249055(B1) | 2001-06-01 | Dubin | Applicant |
| US6251242(B1) | 2001-06-01 | Fu et al. | Applicant |
| US6251528(B1) | 2001-06-01 | Uzoh et al. | Applicant |
| US6251759(B1) | 2001-06-01 | Guo et al. | Applicant |
| US6252304(B1) | 2001-06-01 | Cole et al. | Applicant |
| US6258223(B1) | 2001-07-01 | Cheung et al. | Applicant |
| US6258707(B1) | 2001-07-01 | Uzoh | Applicant |
| US6274008(B1) | 2001-08-01 | Gopalraja et al. | Applicant |
| US6277249(B1) | 2001-08-01 | Gopalraja et al. | Applicant |
| US6281121(B1) | 2001-08-01 | Brown et al. | Applicant |
| US6368954(B1) | 2002-04-01 | Lopatin et al. | Applicant |
| US6374770(B1) | 2002-04-01 | Lee et al. | Applicant |
| US6387800(B1) | 2002-05-01 | Liu et al. | Applicant |
| US6391776(B1) | 2002-05-01 | Hashim et al. | Applicant |
| US6395164(B1) | 2002-05-01 | Andricacos et al. | Applicant |
| US6395642(B1) | 2002-05-01 | Liu et al. | Applicant |
| US6398929(B1) | 2002-06-01 | Chiang et al. | Applicant |
| US6403465(B1) | 2002-06-01 | Liu et al. | Applicant |
| US6433429(B1) | 2002-08-01 | Stamper | Applicant |
| US6440289(B1) | 2002-08-01 | Woo et al. | Applicant |
| US6500762(B1) | 2002-12-01 | Hashim et al. | Applicant |
| US6506668(B1) | 2003-01-01 | Woo et al. | Applicant |
| US6515368(B1) | 2003-02-01 | Lopatin et al. | Applicant |
| US6566259(B1) | 2003-05-01 | Ding et al. | Applicant |
| US6582569(B1) | 2003-06-01 | Chiang et al. | Applicant |
| US6605197(B1) | 2003-08-01 | Ding et al. | Applicant |
| US6627542(B1) | 2003-09-01 | Gandikota et al. | Applicant |
| US6686280(B1) | 2004-02-01 | Shue et al. | Applicant |
| US2002/0029958(A1) | 2002-03-01 | Chiang et al. | Applicant |
| US2003/0057527(A1) | 2003-03-01 | Chung et al. | Applicant |
| US2003/0116427(A1) | 2003-06-01 | Ding et al. | Applicant |
| US2003/0129828(A1) | 2003-07-01 | Cohen | Applicant |
| US2004/0121608(A1) | 2004-06-01 | Shue et al. | Applicant |
| US2004/0140196(A1) | 2004-07-01 | Gopalraja et al. | Applicant |
| US2004/0147104(A1) | 2004-07-01 | Lin et al. | Applicant |
| US2004/0157431(A1) | 2004-08-01 | Lin et al. | Applicant |
| US2004/0188850(A1) | 2004-09-01 | Lee et al. | Applicant |
| US2004/0241321(A1) | 2004-12-01 | Ganguli et al. | Applicant |
| US2005/0045485(A1) | 2005-03-01 | Shih et al. | Applicant |
| US2005/0110147(A1) | 2005-05-01 | Wu et al. | Applicant |
| WO48226 | 2000-08-01 | Applicant |
Non-Patent Literature (42)
- “Biased Directional Sputtering For Barrier And Seed Layers” by S. Mizuno et al., 1999 Proc. 16th Intl VLSI Multilevel Interconn. Conf. (VMIC), Sep. 7-9, 1999, pp. 591-596.Applicant
- “Cooper Barrier Bias-Temperature Stress Tests On Low-k CVD Silicon-Ocide-Based Black Diamond Films” by R. P. Mandal et al., 1999 Proc. 16th Intl VLSI Multilevel Interconn. Conf. (VMIC), Sep. 7-9, 1999, pp. 585-590.Applicant
- “The Influence Of The Underlayer On The CVD Cu Nucleation” by Y. Qian et al., 1999 Proc. 16th Intl VLSI Multilevel Interconn. Conf. (VMIC), Sep. 7-9, 1999, pp. 558-562.Applicant
- “Gap Filling Electro-Chemical Deposition Technology For Copper Damascene Process” by M. Zhu et al. 1999 Proc. 16th Intl VLSI Multilevel Interconn. Conf. (VMIC), Sep. 7-9, 1999, pp. 541-546.Applicant
- “Study of Diffusion Barrier Properties of Ionized Metal Plasma (IMP) Deposited TaN Between Cu and SiO2” by Y. K. Lee et al., 1999 Proc. 16th Intl VLSI Multi. Inter. Conf. (VMIC), Sep. 7-9, 1999, pp. 322-324.Applicant
- “Electromigration Characteristics of Damascene CVD, PVD, and Electroplated Copper Metallization” by H. S. Rathore et al., 1999 Proc. 16th Intl VLSI Multi. Inter. Conf. (VMIC), Sep. 7-9, 1999, pp. 89-92.Applicant
- “Cu Dual Damascene Integration Issues” by S. Kordic et al., 1999 Proc. 16th Intl VLSI Multilevel Interconn. Conf. (VMIC), Sep. 7-9, 1999, pp. 53-62.Applicant
- “Aluminum Persists as Copper Age Dawns” by A. E. Brown, Semi. Intl., Aug. 1999, pp. 58-66.Applicant
- “Implications of damascene topography for electroplated copper interconnects” by M. E. Gross et al., Solid State Tech., Aug. 1999, pp. 47-52.Applicant
- “Copper Electroplating Enters Mainstream Processing” by A. E. Brown, Semi. Intl., Apr. 1999, pp. 58-66.Applicant
- “Barriers for copper interconnections” by C. Ryu et al., Solid State Tech., Apr. 1999, pp. 53-56.Applicant
- “Copper On-Chip Interconnections” by P. C. Andricacos, The Electrochemical Society Interface, Spring 1999, pp. 31-37.Applicant
- “Barrier Capabilities of Selective Chemical Vapor Deposited W Films and WSiN/WSix/W Stacked Layers Against Cu Diffusion” by M. T. Wang et al., J. Electrochemical Soc., vol. 146(2), Feb. 1999, pp. 728-731.Applicant
- “Tantalum Nitride Grown by Inorganic Low Temperature Thermal Chemical Vapor Deposition” by A. E. Kaloyeros et al., J. Electrochemical Soc., vol. 146(1), Jan. 1999, pp. 170-176.Applicant
- “Sputtered Cr and Reactively Sputtered CrNx Serving as Barrier Layers Against Copper Diffusion” by J. C. Chuang et al., J. Electrochemical Soc., vol. 145(12), Dec. 1998, pp. 4290-4296.Applicant
- “Electroplating bath control for copper interconnects” T. Taylor et al., Sol. St. Tec., Nov. 1998, pp. 47-57.Applicant
- “Options for CVD of Dielectrics Include low-k Materials” by J. Baliga, Semi. Intl., Jun. 1998, pp. 139-144.Applicant
- “The Challenges of the Copper CMP Clean” by D. Hymes et al., Semi. Intl, Jun. 1998, pp. 117-122.Applicant
- “The Environment, Health and Safety Side of Copper Metallization” by L. Mendicino and P. T. Brown, Semi. Intl., Jun. 1998, pp. 105-110.Applicant
- “Copper has enormous benefits when compared to aluminum, but its implementation requires some fundamental changes in process technologies” by P. Singer, Semi. Intl., Jun. 1998, pp. 91-98.Applicant
- “Damascene copper electroplating for chip interconnections” by P. C. Andricacos et al., IBM Journal of Research & Development, vol. 42, No. 5, 1998, pp. 567-574.Applicant
- “The Evolution of Interconnection Technology at IBM” by J. G. Ryan et al., IBM Journal of Research & Development, vol. 39, No. 4, 1995.Applicant
- “Sputter Deposition Processes” by R. Parsons, pp. 177-208 in Thin Film Processes II, Edited by J. L. Vosen and W. Kern, Academic Press (1991).Applicant
- “The Catholic Arc Plasma Deposition of Thin Films” by P. C. Johnson, pp. 209-280 in Thin Film Processes II, edited by J. L. Vosen and W. Kern, Academic Press (1991).Applicant
- “Thermal Chemical Vapor Deposition” by K. F. Jensen and W. Kern, pp. 283-368 in Thin Film Processes II, edited by J. L. Vosen and W. Kern, Academic Press (1991).Applicant
- “CVD Cu technology development for advanced Cu interconnect applications” by Cheng-Hong Lee, et al., IEEE 2000 International Interconnect Technology Conference (IITC), Jun. 5-7, 2000, pp. 242-244.Applicant
- “Ultrathin CVD Barrier/Seed for 0.1 μm Dual Damascene Cu Interconnects” by C. Block et al., IEEE 2001 International Interconnect Technology Conference (IITC), Jun. 4-6, 2001, pp. 210-212.Applicant
- “Electroless and Electrolytic Seed Repair Effects on Damascene Feature Fill” by T. Andryuschenko et al., IEEE 2001 International Interconnect Technology Conference (IITC), Jun. 4-6, 2001, pp. 33-35.Applicant
- “Characterization of Electroless Copper as a Seed Layer for sub-0.1 μm Interconnects” by S. Gandikota et al., IEEE 2001 International Interconnect Technology Conference (IITC), Jun. 4-6, 2001, pp. 30-32.Applicant
- “Integration of Electroless Copper for Seed Repair” by C. Witt et al., IEEE 2002 International Interconnect. Technology Conference (IITC), Jun. 3-5, 2002, pp. 259-261.Applicant
- “Atomic Layer Deposition Targets Thin Films” by P. Singer, Semiconductor International, Sep. 1999, p. 40.Applicant
- “Factors Influencing Damascene Feature Fill Using Copper PVD and Electroplating” by J. Reid et al., J. Solid State Technology, pp. 86-103, Jul. 2000.Applicant
- R. Kroger et al., “Properties of Copper Films Prepared by Chemical Vapor Deposition for Advanced Metallization of Microelectronic Devices”, J. Electrochemical Society, 146(9), 3248-3254 (1999).Applicant
- R. Kroger et al., “Nucleation and Growth of CVD Cu Films”, Materials Research Society Symposium Proceedings, vol. 564, pp. 237-241 (1999).Applicant
- P. Martensson and J. O. Carlsson, “Atomic Layer Epitaxy of Copper on Tantalum”, Chemical Vapor Deposition (Advanced Materials), vol. 3(1), pp. 45-50 (1997).Applicant
- J. Huo and R. Solanki, “Characterization of copper films produced via atomic layer deposition”, Journal Materials Research, vol. 17(9), pp. 2394-2398 (Sep. 2002).Applicant
- L. Chen and T. Ritzdorf, “ECD Seed Layer for Inlaid Copper Metallisation”, Semiconductor Fabtech, pp. 267-271, 12th Edition, Jul. 2000.Applicant
- Bakli et al., “Materials and processing for 0.25 μm multilevel Interconnect”, Microelectronic Engineering, 33 (1997) 175-178.Applicant
- Cohen et al., “Sub-0.10 μm Cu Interconnects”, Solid State Technology, p. 61-68, May 2001.Applicant
- V. M. Dubin et al., “Selective and Blanket Electroless Copper Deposition for Ultralarge Scale Integration”, J. Electrochem. Soc., vol. 144(3), pp. 898-908, Mar. 1977.Applicant
- B. Chin et al., “Barrier and seed layers for damascene copper metallization”, Solid State Technology, Jul. 1998, pp. 141-147.Applicant
- B. Chin et al., “Barrier and Seed Technologies for Sub-0.10 μm Copper Chips”, Semiconductor International, May 2001, pp. 107-114.Applicant