Isolated drive circuitry used in switch-mode power converters

[0001] This is a non-provisional application based on provisional application Ser. No. 60/265,714 filed Feb. 1, 2001.

[0002] 1. Field of the Invention

[0003] This invention relates generally to switch-mode power converters and more particularly it provides a simple drive circuit with an enable function providing isolation and having high performance in topologies using synchronous rectification.

[0004] 2. Background Discussion

[0005] A switch-mode power converter is a circuit that uses an inductor, a transformer, or a capacitor, or some combination, as energy storage elements to transfer energy from an input source to an output load in discrete pulses. Additional circuitry is added to maintain a constant voltage within the load limits of the circuit. The basic circuit can be configured to step up (boost), step down (buck), or invert output voltage with respect to input voltage. Using a transformer allows the output voltage to be electrically isolated from the input voltage.

[0006] Switch-mode converters have changed very little over the past 15 years, most using Schottky diodes to rectify their output. However, newer challenges in the industry for dc/dc power supply designers demand lower voltages required by digital circuits, and also higher frequencies. Since converters using Schottky diodes for rectification experience a large forward voltage drop relative to the output voltage, their efficiency is generally relatively low. Lower efficiencies result in more dissipated heat that has to be removed using a heat sink, which takes up space. A dramatic increase in converter efficiency has been realized by replacing the Schottky diodes with “synchronous rectifiers” configured in practice with MOSFET transistors. Synchronous rectifiers are not new, but they have previously been too expensive to justify, primarily due to high ON resistance. However, as costs fall and performance improves, synchronous rectifiers have quickly become a viable component, especially for low voltage converters.

[0007] Using self-driven synchronous rectifiers in various converter topologies is very attractive and popular because there is no need for additional isolation between drive signals. It has the advantage of simplicity. However, it has the disadvantage of cross conduction between synchronous rectifiers and primary side switches, as well as reverse recovery current of the parasitic anti-parallel diode of the MOSFET used for synchronous rectification. In order to minimize these shoot-through currents, an inductance (or saturable inductor) is usually placed in series with the synchronous rectifier. While this may be a solution for lower switching frequencies, for example, 100 kHz-200 kHz, it is not suitable for higher switching frequencies (200 kHz and above). Especially at switching frequencies of 300-400 kHz this is not an optimum solution. The reason for this is that increased inductance in series with a synchronous rectifier reduces the effective duty cycle on the secondary side of the power transformer due to slower di/dt of the secondary current. As a result, more voltage head-room is required in the power transformer implying a smaller effective turns ratio and consequently a lower efficiency. A second reason why self-driven synchronous rectification is not suitable for higher switching frequencies is the potential loss due to reverse recovery current in the body diode of the synchronous rectifiers (MOSFETs) and increased turn-on current in the primary side switches (usually MOSFETs).

[0008] A previous improvement has been to use direct drive for synchronous rectifiers with well controlled timing between drive signals for the main switches (primary side) and synchronous rectifiers (secondary side). This solution thus allows for very efficient operation of the synchronous rectifiers even at high switching frequencies. Yet another benefit of direct driven synchronous rectifiers is that the drive voltage (gate to source) is constant and independent of input voltage, which further improves efficiency over a wide input voltage range.

[0009] An example of the above prior art is set forth in U.S. Pat. No. 5,907,481. However, the invention in this patent provides only signals for drivers for the primary side switches and uses additional logic for delaying drive waveforms (R-C-D networks and logic gates). The '481 apparatus uses an isolation drive transformer for a logic signal only to control operation of the primary switches. It does not use a drive transformer to power the primary switches but rather uses a separate circuit to provide power and delays.

[0010] It is necessary to provide delays between drive signals for primary side switches and secondary side switches (synchronous rectifiers) in order to avoid cross conduction (simultaneous conduction which would result in a short circuit). When power converters are operated at lower switching frequencies (for example, 100 kHz), cross conduction of the switches can be acceptable since the percentage of the time during which cross conduction occurs relative to the switching period is small (typically about 40 ns/10 μs). Also, a transformer designed to operate at lower frequencies will have a larger leakage inductance, which will reduce cross conduction currents. In the case of higher switching frequencies (above 100 kHz), the cross conduction ratio becomes more unacceptable (about 40 ns/2 μs for a 500 kHz switching frequency). Also for higher switching frequencies, the leakage inductance in the transformer as well as in the entire power stage should be minimized for higher efficiency. Consequently, currents due to cross conduction time can become significant and degrade overall converter efficiency and increase heating of the power components significantly.

[0011] According to an embodiment of the invention, one drive transformer is used for providing the proper delays in drive waveforms as well as power for driving primary switches, particularly high side switches in a half-bridge topology. The leakage inductance of the drive transformer is used to delay turn-on of the main switches (primary side) while turn-off is with no significant delay. The number of windings on the drive transformer is minimized and varies from three to four depending on where the switch conduction control circuit is referenced. In a half-bridge converter, having the control circuit (pulse width modulated (PWM) type, for example) referenced to the output of the converter, there are three windings: (1) for the control signal and providing proper waveforms for driving synchronous rectifiers; (2) for driving the bottom primary switch; and (3) for driving the top primary switch. If the control circuit is referenced to the input of the converter there are four windings: (1) for the control signal; (2) for providing proper waveforms for driving synchronous rectifiers; (3) for driving the bottom primary switch; and (4) for driving the top primary switch. It is an additional object of the invention to provide means to enable/disable the module due to a condition sensed on either the primary (input) or secondary (output) side via a controller, which maybe located on either the primary or secondary side.

[0027] With reference now to FIG. 1, there is shown an embodiment of the invention using a half-bridge converter. Primary switches Q₁, Q₂ (also called primary controllable power switches), synchronous rectifiers S₁ and S₂, capacitors C₁, C₂ and C₀, power isolation transformer T₂ and inductor L₀ form a half-bridge dc-to-dc converter. The invention could also be embodied in other topologies including ac-to-dc, dc-to-ac and others. Input voltage V_IN is split with capacitors C₁ and C₂. One side of primary winding N_P of transformer T₂ is connected to the common connection of capacitors C₁ and C₂ while the second end is connected to the common point of switches Q₁ and Q₂. Two secondary windings N_S1 and N_S2 are preferably identical and are connected in series. The common point of these windings N_S1 and N_S2 is connected to one end of output inductor L₀, and the second end of inductor L₀ is connected to capacitor C₀ that is connected across the output of the converter. The second end of winding N_S1 is connected to synchronous rectifier (switch) S₁ while the second end of winding N_S2 is connected to synchronous rectifier (switch) S₂. The polarity of the windings of transformer T₂ is chosen such that when switch Q₁ is on, synchronous rectifier S₁ is on and S₂ is off. In contrast, when switch Q₂ is on, synchronous rectifier S₁ is off and S₂ is on. When both Q₁ and Q₂ are off, S₁ and S₂ are both on. Primary switches Q₁ and Q₂ are both exemplified as MOSFETs, but may also be realized as IGBTs (isolated gate bipolar transistors). This particular embodiment is explained as a hard switching half-bridge converter with split secondary windings. The invention is also applicable to derivatives of a half-bridge converter, such as but not limited to, a half bridge converter with a single secondary winding employing a current doubler on the output.

[0028] Output voltage V_OUT is compared with reference voltage V_R in block 100, which is typically an error amplifier. The output of block 100 is fed into isolation circuit (usually an opto-coupler or isolation transformer) 101 and error signal V_E is fed into block 102. Controller and drive block 102 contains switch conduction control circuitry that comprises a feedback and controller (PWM type, for example), two driver stages generating out-of-phase outputs OUTA and OUTB, and ON/OFF logic. This block can contain additional protection features very often found in converters, but they are not relevant for the purpose of the present description, and are thus omitted. Driver outputs OUTA and OUTB are capable of driving switches Q₁ and Q₂ as well as drive transformer T₁. Note that in FIG. 1, controller 102 and OUTA and OUTB drivers are referenced to —V_IN, and therefore to the input of the converter.

[0029] Drive transformer T₁ has four windings N₁, N₂, N₃ and N₄. Winding N₄ is driven from controller 102 via OUTA and OUTB and capacitor C₃, in series with winding N₄, is a DC blocking capacitor. Winding N₁ is connected at one end to the source of transistor Q₁ and the second end is connected to the gate of Q₁ via series diode D₁. Transistor (also called control switch) Q₃, shown as a p-channel MOSFET, is connected across the gate and source of Q₁ with its gate connected to the anode of diode D₁. Resistor R₁ is used to increase the noise immunity of transistor Q₁ when the voltage across winding N₁ is zero. Similarly, winding N₂ is connected with one end to the source of transistor Q₂ and the second end is connected to gate of transistor Q₂ via series diode D₂. Transistor Q₄, also shown as a p-channel MOSFET, is connected across the gate and source of Q₂ with its gate connected to anode of diode D₂. Resistor R₂ is used to increase the noise immunity of Q₂ when voltage across winding N₂ is zero.

[0030] Winding N₃ is connected to the drive circuitry for synchronous rectifiers S₁ and S₂. The ends of winding N₃ are connected via respective resistors R₂₁ and R₂₂ to the secondary side ground and to one input of two input logic OR gates U₁ and U₃. It is assumed that each input of gates U₁ and U₃ has protection diodes from ground to input and from input to supply voltage V_CCS. If logic gates without these diodes are used, than external diodes need to be added for proper operation of the circuit (as in FIG. 1, external diodes D₃-D₁₀). Supply voltage V_CCS is usually generated from the windings of power transformer T₂ or a separate bias circuit from the primary side with the proper isolation. Drive transformer T₁ can provide the necessary supply voltage V_CCS via winding N₃ and diodes D₅, D₆, D₈ and D₁₀ as is described herein. The second input of logic gate U₁, is connected through resistor R₂₃ to the drain of synchronous rectifier S₁, while the second input of logic gate U₃ is connected through resistor R₂₄ to the drain of synchronous rectifier S₂. These two inputs provide break-before-make turn-on of both synchronous rectifiers S₁ and S₂ as is detailed herein. The voltage on the inputs of logic gates U₁ and U₃ is clamped to V_CCS with diodes D₄ and D₇, respectively. The output of logic gate U₁ is connected to the input of inverting driver U₂, which drives synchronous rectifier S₁, while the output of logic gate U₃ is connected to the input of inverting driver U₄, which drives synchronous rectifier S₂.

[0031] Inductances L₁ and L₂ are the leakage inductances associated with windings N₁ and N₂, respectively, of transformer T₁. These two inductances are carefully designed and made larger than usual in order to delay turn-on of switches Q₁ and Q₂. Adjusting inductances is relatively simple when the transformer windings are formed on a printed circuit board (PCB), especially on multi-layer PCBs. In addition, repeatability and control in manufacturing are excellent. Typical values for these inductances are approximately 100 nH and higher. They are designed so that one-fourth of the period of oscillation caused by the input capacitance of switches Q₁ and Q₂ and leakage inductances of the windings (L₁ and L₂) is longer than the turn-off time of the secondary synchronous rectifying switches S₁ and S₂.

[0032] The leakage inductance L₃ of winding N₃ of the drive transformer is not critical since winding N₃ is loaded with high impedance load, also taking into consideration the input capacitance of logic gates U₁ and U₃ (5 pF-10 pF being typical). Thus inductance L₃ will not have significant impact on the rising and falling edges of the voltage waveforms across winding N₃ and consequently will not add any additional delay in turning off synchronous rectifiers S₁ and S₂.

[0033] The salient waveforms are provided in FIG. 2 for circuit operation understanding. In these waveforms:

• [0034] t_d1—time between turning-off synchronous rectifier S₂ and turning-on switch Q₁. This is determined by the leakage inductance L₁ of drive transformer T₁ and the input capacitance of primary switch Q₁.
• [0035] t_d2—time delay between turning-off switch Q₁ and turning-on synchronous rectifier S₂. The drive voltage (V_GS2) of synchronous rectifier S₂ is applied when the voltage across S₂ (V_S2) is below the threshold of logic gate U₃.

[0036] Resister R₂₄ and the input capacitance of logic gate U₃ provide fine tuning of the delay. During this time the output capacitance of S₂ is discharged with the output inductor current.

• [0037] t_d3—time between turning-off synchronous rectifier S₁ and turning-on switch Q₂. It is determined by the leakage inductance L₂ of drive transformer T₁ and the input capacitance of primary switch Q₂. Usually, td₁≈td₃ in practice.
• [0038] t_d4—time delay between turning-off switch Q₂ and turning-on synchronous rectifier S₁. The drive voltage for synchronous rectifier S₁ (V_GS1) is applied when the voltage across it, V_S1, reaches near zero value (threshold of logic gate U₁). Resistor R₂₃ and the input capacitance of logic gate U₁ provide fine tuning of this delay. The output c rectifier S₁ is discharged by the output inductor current during this time.

[0039] Usually, t_d2≈td₄ in practice.

[0040] At t=0, OUTA becomes high, while OUTB is low. The voltage across the windings of T₁ is positive. Note that the dot next to one end of each winding of T₁ is used for reference and is now positive with respect to other side of the winding. Since the voltage across winding N₃ is positive, the output of U₄ goes high causing turn-off of primary switch S₂ with minimum delay. Note that the end of winding N₃ that is connected to the input of logic gate U₁ is clamped with an internal diode to the negative voltage equal to the forward voltage drop of the diode. The output of inverting driver U₂ is low and synchronous rectifier S₁ is still on. At the same time, positive voltage is applied across winding N₁, diode D₁ becomes forward biased and the input capacitance of transistor Q₁ begins charging in a resonant manner via leakage inductance L₁ of winding N₁. At t=t_d1, gate voltage V_G1 is positive and transistor Q₁ is fully on. Note that positive voltage across winding N₂ keeps transistor Q₂ off. The body diode of inverting driver Q₄ clamps negative voltage on the gate of Q₂ to near zero during time DTs/2 while D₂ is reverse biased. Clamping negative voltage on the gate of Q₂ during the off time is desirable in order to reduce gate drive losses. Positive voltage is applied across all windings of transformer T₂ during the time following t_d1 to the completion of DTS/2. The voltage across synchronous rectifier S₂ is also positive and S₂ is off. The output inductor current is supplied through winding N_S1 and synchronous rectifier S₁. At t=DTs/2, OUTA becomes low (OUTB is still low), winding N₄ is shorted and the voltages across the other three windings of T₁ are near zero. Transistor Q₃ is turned-on, diode D₁ is reverse biased, the input capacitance of transistor Q₁ is discharged very quickly via the ON resistance of Q₃ and gate voltage V_G1 rapidly drops to zero resulting in the turn-off of Q₁. The current through output inductor L₀ splits between synchronous rectifier S₁ and the body diode of S₂, which as a consequence has shorted the windings of transformer T₂. As soon as voltage across synchronous rectifier S₂ drops down to the logic zero threshold of logic gate U₃, the output of U₃ goes low (since the input connected to winding N₃ is zero) and synchronous rectifier S₂ is turned-on via driver U₄ (time interval t_d2). Both synchronous rectifiers S₁ and S₂ are on during the rest of the half of the switching period (Ts/2) and voltages across the windings of transformers T₁ and T₂ are zero (time interval t_x).

[0041] At t=Ts/2, OUTB goes high while OUTA is kept low and the voltage on the windings of T₁ becomes negative. Since the voltage across winding N₃ is negative, the voltage across resistor R₂₁ is positive and the output of logic gate U₁ goes high causing the output of driver U₂ to go low which turns-off synchronous rectifier S₁ with minimum delay. Note that the end of winding N₃ connected to the input of U₃ is clamped with an internal diode to the negative voltage equal to the forward voltage drop of the diode. Since both inputs of logic gate U₃ are at the low logic level, the output of U₃ is low, the output of driver U₄ is high and synchronous rectifier S₂ is still on. At the same time negative voltage is applied across winding N₂ (the end with no dot is more positive than the end with a dot), diode D₂ becomes forward biased and the input capacitance of transistor Q₂ starts to be charged in resonant manner via the leakage inductance L₂ of winding N₂. At t=Ts/2+t_d3, voltage V_G2 is high and transistor Q₂ is fully on. Note that the negative voltage across winding N₁, keeps transistor Q₁ off. The body diode of Q₃ clamps negative voltage across the gate of Q₁ to near zero, while diode D₁ is reverse biased. Clamping negative voltage on the gate of Q₁ during off-time is desirable in order to reduce gate drive losses. Positive voltage is applied across all windings of transformer T₂. The voltage across synchronous rectifier S₁ is also positive. During time T_S/2+DT_S/2 the output inductor current is supplied from the input through winding N_S2 and synchronous rectifier S₂.

[0042] At t=T_S/2+DT_S/2, OUTB becomes low (OUTA is still low), winding N₄ is shorted and the voltages across the other three windings of T₁ are near zero. Transistor Q₄ is turned-on, diode D₂ is reverse biased, the input capacitance of primary switch Q₂ is discharged very quickly via the ON resistance of Q₄ and voltage V_G2 rapidly drops to zero resulting in turn-off of transistor Q₁. The current through output inductor L₀ splits between synchronous rectifier S₂ and the body diode of S₁, which as a consequence has shorted the windings of transformer T₂. As soon as the voltage across S₁ drops down to the logic zero threshold of U₁, the output of U₁ goes low (since the input connected to resistor R₂₁ is zero) and synchronous rectifier S₁ is turned-on via driver U₂. The time interval between turning-off of Q₂ and turning-on S₁ is denoted as t_d4. Synchronous rectifiers S₁ and S₂ are on during the rest of the half of the switching period and the voltages across the windings of transformers T₁ and T₂ are zero (time interval t_y). At the end of time interval t_y, operation of the converter of FIG. 1 repeats.

[0043] The turn-on waveforms of transistor Q₁ are shown in more detail in FIG. 3 for two different values of leakage inductance L₁ (L₁₍₁₎ and L₁₍₂₎) in order to explain the turn-on delay of primary switch Q₁ due to the finite rise time of the current in leakage inductance L₁ of winding N₁. The same consideration applies to primary switch Q₂. The lower value of leakage inductance L₁, denoted L₁₍₂₎, allows a higher peak current for charging input capacitance of transistor Q₁ and consequently a faster turn-on of Q₁ and shorter delay between the turning-off of S₂ and turning-on of Q₁. Note that V_ON in the (C) portion of FIG. 3 represents the voltage level of V_G1 at which Q₁ is fully on, and t_d1 (divided into t_d1(1) and t_d(2)) is the so called “dead-time” and represents the time during which both synchronous rectifier S₂ and primary switch Q₁ are off. This dead-time is necessary in order to avoid cross conduction of synchronous rectifier S₂ and primary switch Q₁ (and S₁ and Q₂). A dead-time that is too long is not desirable since during this time the body diode of S₂ (and equivalently, S₁) is carrying half of the output inductor current, thus decreasing the efficiency of the converter. If the dead-time is too short, that is, Q₁ is on before S₂ is turned-off, there will still be cross-conduction which will result in efficiency drop. Therefore, it is important to have a well controlled dead-time in order to achieve the highest efficiency. With proper design of leakage inductances and repeatability in manufacturing, dead-time is optimized for maximum efficiency.

[0044] The turn-off waveforms for transistor Q₁ (that also apply for Q₂) are shown in further detail in FIG. 4. Since diode D₁ becomes reverse biased when OUTA goes low, the discharging current of the input capacitance of Q₁ goes through transistor Q₃ and is limited, in first approximation, only by the resistance and turn-on characteristics of Q₃ but it is not affected by leakage inductance L₁ of winding N₁. In this manner, a very fast and well-controlled turn-off of Q₁ (as well as of Q₂) can be achieved. By varying the resistance of switch Q₃, the turn-off performance of primary switch Q₁ can be adjusted to a preferred value.

[0045] While the turn-on of primary switches Q₁ and Q₂ are delayed (slowed down) by leakage inductances L₁ and L₂ respectively, turn-off is very fast due to switches Q₃ and Q₄ and their low resistance. By placing switches Q₃ and Q₄ physically close to switches Q₁ and Q₂, maximum speed for turning off switches Q₁ and Q₂ is achieved. Note that the turn-off performance of switches Q₁ and Q₂ is not affected by leakage inductances L₁ and L₂, which allows independent control of turn-on and turn-off transients. Also, it is preferable for EMI (electromagnetic interference) purposes to have the turn-on of switches Q₁ and Q₂ slowed down.

[0046] As an alternative, if the control circuit and the drive circuit are on the secondary side of the converter (referenced to the output of the converter), windings N₃ and N₄ can be merged, thus eliminating one winding from the FIG. 1 embodiment, as shown in FIG. 5. In this case, OUTA and OUTB outputs are directly connected to one input of logic gates U₃ and U₁, respectively. Resistors R₃ and R₄ are in series with the gates of switches Q₃ and Q₄ in order to dampen any undesirable oscillations caused between the input capacitance of Q₃ and Q₄ and the leakage inductance in corresponding windings N₁ and N₂. Resistors R₅ and R₆ are to dampen oscillations on the gates of Q₁ and Q₂, respectively, caused by resonance between the leakage inductance L₁ and the input capacitance of Q₁, and leakage inductance L₂ and input capacitance of Q₂. Resistors R₃ through R₆ are not shown in FIG. 1 for simplicity of circuit description but would be present for practical realization of the circuit. Note that the salient waveforms in FIG. 2 are still applicable for the circuit of FIG. 5. Also for simplicity only block 103 (incorporating a controller, drive and protection circuitry, as well as regulation circuitry) is shown in FIG. 5. Its specific realization is insignificant to the invention. A significant difference of the FIG. 5 embodiment is to configure the output driver stages, OUTA and OUTB, logic gates U₁ and U₃, and drivers U₂ and U₄ as described. The operating principles correspond to those of the FIG. 1 embodiment. The supply voltage for controller 103 and U₁ through U₄ are referenced to the output of the converter and can be generated in different ways that are not relevant for the operation of the drive circuit.

[0047] Illustrated in FIGS. 6, 7 and 8 are partial circuitry embodiments for the possible realization of drivers U₂ and U₄. In FIG. 6, logic gate U₁ (U₃) is a NOR gate instead of an OR gate since driver stage U₂ (U₄) is non-inverting. Both drivers U₂ and U₄ are identical. In FIGS. 7 and 8, driver stage U₂ (U₄) is inverting and logic gate U₁ (U₃) is an OR gate as in FIGS. 1 and 5. In FIG. 8, the driver stage U₂ (U₄) allows synchronous rectifier S₁ (S₂) to be driven with a voltage higher than the supply voltage for logic gate U₁ (U₂). Similarly, driver U₄ functions in the same manner with synchronous rectifier S₂. Practical realizations of drivers U₂ and U₄ different from those in FIGS. 6 through 8 are also possible.

[0048] Even though transistors Q₃ and Q₄ (in FIGS. 1 and 5) are shown as p-channel MOSFETs, it is possible to use n-channel MOSFETs as well as bipolar transistors. The former are more practical than the latter due to easier drive and an integrated body diode, which would be needed as an external component if switches Q₃ and Q₄ were bipolar transistors. An embodiment realization using n-channel MOSFETs as Q₃ and Q₄ from FIGS. 1 and 5 is shown in FIG. 9. When p-n-p bipolar transistors are used for switches Q₃ and Q₄, two additional diodes D₁₁ and D₁₂ would be needed as shown in FIG. 10. Diodes D₁₁ and D₁₂ prevent shorting of windings N₁ and N₂ via the collector-emitter junction of Q₃ and Q₄, respectively. Note that if the circuit of FIG. 10 is used, positive voltage on the gates of transistors Q₁ and Q₂ will be for one diode voltage drop (typically about 0.5V) less than in the original FIG. 1 circuit.

[0049] If the control circuit is on the primary side, as in FIG. 1, it is desirable that there be a means to disable the converter from a condition sensed on the secondary side, for example, in case of output over-voltage or under-voltage conditions. Similarly, if the feedback and control circuit is referenced to the output of the converter, as in FIG. 5, it is desirable that there be a means to disable the converter from a condition sensed on the primary side, for example, in case of input over-voltage or under-voltage conditions or in order to turn the converter off. One solution, which has previously been employed is to use an opto-coupler, which has several disadvantages:

• • [0050] It cannot operate at temperatures above 85° C. (some are limited to 100° C.), and therefore will impose serious limitations on the temperature of the PCB which is also used as a means for cooling semiconductor devices and magnetic devices;
  • [0051] Unless it is fast (digital), the opto-coupler will not provide a fast disable of the control circuit, particularly in the case of output over-voltage condition when the controller is on the primary side and the converter operates at high switching frequency;
  • [0052] Opto-couplers are not available in small, low-profile packages. Thus, it will be the tallest component and will impose a limit on the low-profile design of the converter.

[0053] Another prior art solution has been to have a separate pulse transformer that will be used only for this function. The main drawbacks of this alternative are:

• • [0054] An additional component which needs to meet all safety requirements;
  • [0055] Extra space is required on the PCB, thus imposing limits on the minimum size of the PCB;
  • [0056] If there is no other use of this transformer it is not a practical solution.

[0057] An alternate solution disclosed herein provides, as shown in FIGS. 11A, 11B and 12, a means for disabling the control circuit on the secondary side from a condition sensed on the primary side as described in detail below. The principle idea is to short one of the windings of the drive transformer (FIGS. 11A and 11B), preferably one that is not floating (N₂), detect excessive current in winding N₃ due to a short in winding N₂ and disable the control circuit and drivers OUTA and OUTB resulting in turn-off of the converter. Another alternative solution is to use a separate winding on the drive transformer and short that winding (FIG. 12). Different circuit realizations are possible as is known to one of ordinary skill in the art.

[0058] The primary side protection logic, as shown in FIGS. 11A and 11B, initially senses a fault condition and generates a disable signal that is active (high logic level). Transistor Q₁₀ (FIG. 11A), shown as an n-channel MOSFET as an example, and diode D₃₀, form a voltage bi-directional switch, which means that current can flow only in one direction. Diode D₃₀ is necessary to prevent conduction in the body diode of transistor Q₁₀ when the voltage on winding N₂ is positive (the dot end of the winding is more positive than the opposite end) and therefore prevent shorting of winding N₂ during normal operation of the converter. In response to an active disable signal DSP, transistor Q₁₀ is turned-on and diode D₃₀ becomes forward biased when the voltage on winding N₂ is negative. Winding N₂ is then shorted which results in the turn-off of primary switch Q₁ and an increase in current through winding N₃, causing a voltage drop across resistor R₁₁ connected between supply voltage V_CCS and drivers DRIVER_A and DRIVER_B referenced to the output of the converter. Note that a possible realization for DRIVER_A and DRIVER_B is shown in FIGS. 11A and 11B explicitly as complementary pairs of p-and n-channel MOSFETs. The voltage across resistor R₁₁ is sensed with comparator U₅ that has a threshold set such that in normal operation the voltage drop across resistor R₁₁ will not trip U₅. However, when winding N₂ is shorter, comparator U₅ is activated causing controller 104 to disable the converter by setting both outputs OUTA and OUTB low. Note that transistor Q₁₀ can be connected in parallel with switch Q₄ in which case the gate of primary switch Q₂ will be shorted in response to the active disable signal. As a consequence, winding N₂ will be shorted via Q₁₀ and diode D₂, similarly causing increased current through winding N₂. Diode D₃ (employed in the FIG. 1 embodiment) is not needed in this embodiment. A design characteristic of this solution is that the capacitance of Q₁₀ will affect the turn-on performance of Q₂. In order to achieve similar turn-on characteristics of both Q₁ and Q₂, leakage inductance L₂ is required to be less a L₁, thus resulting in a more complicated drive transformer design. Note that the disable circuit from FIG. 11A has an inherent delay of one switching period since shorting winding N₂ will affect the circuit only during the on-time of transistor Q₁. In most applications this should not be a problem.

[0059] An alternate solution to the FIG. 11A embodiment is shown in FIG. 11B. Two switches, Q₅ and Q₆, are added to short winding N₂ whenever signal DSP is active. Transistor Q₄ is replaced with p-n-p transistor Q₇ and resistor R₅ is added across the base to the collector of Q₇. When the voltage on winding N₂ is negative, diode D₂ and the body diode of Q₆ are forward biased and transistor Q₂ is on with a gate voltage reduced by the voltage drop across the body diode of Q₆ (typically about 0.8V). A feature of this embodiment is that there is a maximum delay of half the switching period and a stronger signal can be generated across resistor R₁₁, thus allowing a higher threshold for U₅ and improved noise immunity. A weakness is a lower gate voltage on primary switch Q₂. By adding a Shottky diode (not shown) across Q₆, the additional voltage drop could be reduced from about 0.8V to about 0.4V with that extra component.

[0060] As an additional embodiment, winding N₄ is added to drive transformer T₁, as shown in FIG. 12, and therefore serves two purposes:

• • [0061] (1) to provide means for disabling the secondary control circuit by shorting winding N₄ with two transistors Q₅ and Q₆; and
  • [0062] (2) to provide regulated bias voltage to the primary control circuit after start-up.

[0063] FIG. 12 is very similar to FIG. 11B, with some additions. Transistors Q₅ and Q₆ are added across winding N₄, instead of winding N₂, in order to short the winding if the DSP signal is high to stop the controller on the secondary side immediately whenever a fault condition on the primary side of the converter is detected. In this configuration, the controller is also on the secondary side and the only communication between the primary and secondary control circuit is via drive transformer T₅. Thus, there is no need for extra components with high voltage isolation (for example, opto-coupler or pulse transformer).

[0064] Resistor R₁₁ (FIG. 12) is now positioned in the return path of DRIVER_A and DRIVER_B as another embodiment and an alternate solution to FIG. 11B. If winding N₄ is shorted by transistors Q₅ and Q₆, excessive current will flow via resistor R₁₁ and comparator U₅ will generate signal DS to stop the controller, thus turning off the entire converter. Note that the disable circuit from FIG. 12 has an inherent delay of one-half of the switching period since shorting winding N₄ affects the circuit during the on-time of both transistors Q₁ and Q₂.

[0065] Winding N₄ has the best coupling with winding N₃, while windings N₂ and N₁ are preferably placed in layers above and below in the PCB. This is the preferred structure because it provides enough leakage between N₃ and N₁ and N₂, and also decouples N₁ and N₂ from N₃ when N₄ is shorted.

[0066] Another embodiment of the invention with the control circuit on the input side of the converter is shown in FIG. 13A in which the disable from the output side is provided by shorting winding N₃. Protection logic 200 (FIG. 13B, referenced to the output of the converter), generates signal DSS whenever the converter needs to be disabled (for example, in case of over-voltage on the output, under-voltage or any other irregular operating condition). Active signal DSS turns-on transistors Q₅ and Q₆ (FIG. 13B), which in turn shorts winding N₃ of drive transformer T₆. The current in winding N₄ is indirectly measured with resistor R₁₂ which is connected in the return path of drivers 60 and 61, which are shown as separate components in FIG. 13A, instead of as internal parts of controller 102 in FIG. 1. Note that drivers 60 and 61, can still be internal parts of controller 105, in which case sensing resistor R₁₂ will measure the total current of the controller and can be placed either in a path to ground or at the+V_IN location. The voltage across resistor R₁₂ is sensed with comparator U₆ with a threshold that is set such that in normal operation the voltage drop across resistor R₁₂ will not trip U₆. However, when winding N₃ is shorted, comparator U₆ is tripped and, in turn, generates signal DSB that disables controller 105, drivers 60 and 61, and consequently the converter.

[0067] It should be understood that the foregoing embodiments are exemplary for the purpose of teaching the inventive aspects of the present invention that are covered solely by the appended claims and encompass all variations not regarded as a departure from the scope of the invention. It is likely that modifications and improvements will occur to those of ordinary skill in the art are intended to be included within the scope of the following claims and their equivalents.