Five-level feed-back digital-to-analog converter for a switched capacitor sigma-delta analog-to-digital converter

[0001] This application claims priority to commonly owned U.S. Provisional Patent Application Ser. No. 60/603,234; filed Aug. 20, 2004; entitled “Five-Level Digital-to-Analog Converter for a Switched Capacitor Sigma-Delta Analog-to-Digital Converter,” by Philippe Deval; which is hereby incorporated by reference herein for all purposes.

[0002] The present disclosure relates to analog-to-digital converters and, more particularly, to a switched capacitor sigma-delta analog-to-digital converter having a five-level feed-back digital-to-analog converter.

[0003] Analog-to-digital converters are in widespread use today in electronics for consumers, industrial applications, etc. Typically, analog-to-digital converters include circuitry for receiving an analog input signal and outputting a digital value proportional to the analog input signal. This digital output value is typically in the form of either a parallel word or a serial digital bit string. There are many types of analog-to-digital conversion schemes such as voltage-to-frequency conversion, charge redistribution, delta modulation, as well as others. Typically, each of these conversion schemes has its advantages and disadvantages. One type of analog-to-digital converter that has seen increasing use is the switched capacitor sigma-delta converter.

[0004] As many analog-to-digital converters, the switched capacitor sigma-delta converter uses a digital-to-analog converter in a feedback loop and cannot be more accurate than the digital-to-analog converter. Therefore a very accurate digital-to-analog converter is required in order to achieve an accurate analog-to digital conversion. However a high resolution is not required for the digital-to-analog converter used in the feedback loop of a sigma-delta converter: The digital-to-analog resolution can be exchanged with the over-sampling ratio at the cost of a longer conversion time.

[0005] A two-level digital-to-analog converter is inherently accurate and thus is not the limiting factor for the accuracy of a sigma-delta converter. Therefore it is the standard approach in a sigma-delta analog-to-digital converter.

[0006] However, what is needed is a reduction in quantization noise, over sampling ratio and power consumption of the sigma-delta analog-to-digital converter. Such a reduction is sometime achieved with a multi-level digital-to-analog converter but with the cost of an expensive trimming or a complicated dynamic element matching technique.

[0007] The invention overcomes the above-identified problems as well as other shortcomings and deficiencies of existing technologies by providing a five-level feed-back digital-to-analog converter (DAC) in a switched capacitor sigma-delta analog-to-digital converter. The five-level feed-back DAC has an improved switching sequence that boosts from two to five the number of quantization levels of the conventional feed-back DAC.

[0008] According to specific exemplary embodiments of the present invention, a switched capacitor sigma-delta converter architecture with an over sampling ratio is used, wherein a five-level feed-back DAC increases the signal to quantization noise ratio of the switched capacitor sigma-delta converter by about 8 dB. The five-level feed-back DAC also increases the stability range of the sigma-delta modulator of the analog-to-digital converter. The new, novel and non-obvious five-level switching sequence for the feed-back DAC may be advantageously utilized in place of the standard two level of DAC switching implementation, and does not require extra phases. Therefore the specific exemplary embodiments may be accomplished with only a few extra digital gates for generating the proper switching sequences for the five-level feed-back DAC.

[0009] Increasing to five the number of levels in the feed-back DAC helps to meet a very stringent signal-to noise ratio and to allow, in first order sigma delta converters, for a gain having a factor of two over sampling ratios used by prior technology two level feed-back DACs. This significantly helps in the integrator design and reduces the overall current consumption of the switched capacitor sigma-delta converter.

[0010] An advantage of the present invention is improved performance and very low-power consumption of a switched capacitor sigma-delta converter.

[0011] Another advantage is improved signal to quantization noise ratio of the switched capacitor sigma-delta converter.

[0012] Still another advantage is improved stability range of the switched capacitor sigma-delta modulator.

[0013] Other features and advantages of the invention will be apparent from the following description of the embodiments, given for the purpose of disclosure and taken in conjunction with the accompanying drawings.

[0017] While the present invention is susceptible to various modifications and alternative forms, specific exemplary embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

[0018] The present invention utilizes an improved switching sequence that boosts the number of levels from two to five of a feed-back digital-to-analog converter (DAC) in a switched capacitor sigma-delta converter. Use of a five level feed-back DAC in a sigma-delta converter is a new, novel and non-obvious application.

[0019] Referring now to the drawings, the details of specific embodiments of the present invention are schematically illustrated. Like elements in the drawings will be represented by like numbers, and similar elements will be represented by like numbers with a different lower case letter suffix.

[0020] Referring to FIG. 1, depicted is a schematic circuit diagram of capacitor switching arrays and a differential amplifier for a five level feed-back digital-to-analog converter (DAC), according to specific exemplary embodiments of the invention. The five-level feed-back DAC, generally represented by the numeral 100, comprises a switching sequence that generates five equally spaced charge quantities during two phases (precharge+transfer) of a differential charge transfer. Thus, the five equally distributed charge levels may be C*VREF, C*VREF/2, 0, −C*VREF/2 and −C*VREF. The reference voltage (VREF=VREFP−VREFM) charging circuit is generally represented by the numeral 102 and comprises transfer reference capacitors 132a and 132b, and switches 112, 114 and 116. The remainder of the specific exemplary embodiment comprises voltage input capacitors 130a and 130b, switches 104, 106, 108 and 110, and differential operational amplifier 150 having feed-back sampling capacitors 134a and 134b. Switches 108a and 108b may relate to common mode operation, and switch 108c may relate to differential signal operation.

[0021] VREFP and VREFM represent voltages at the differential reference input terminals. The reference voltage VREF=VREFP−VREFM. VINP and VINM represent voltages at the differential input signal terminals. The input signal voltage VIN=VINP−VINM. The transfer reference capacitors 132a and 132b may be equal to C/2. The input sampling capacitors 130a and 130b may be equal to A*C/2. The feed-back capacitors 134a and 134b may be equal to C. The input voltage is: VIN=VINP−VINM, and the output voltage is: VOUT=VOUTP−VOUTM. The gain of the circuit shown is A.

[0022] Referring to FIGS. 2a–2e, depicted are timing diagrams for the switching sequences of the switches 104–116 used to obtain the five equally distributed charge levels C*VREF, C*VREF/2, 0, −C*VREF/2 and −C*VREF of the specific exemplary embodiment illustrated in FIG. 1. A “1” logic level depicts the respective switches in the closed position and a “0” logic level depicts the respective switches in the open position. FIGS. 2a–2e further illustrate the non-overlapping delays between the switches 104–116 in order to prevent a short between inputs and to ensure that the switches connected to the summing node always open first. The switches 104–116 are all open (off—logic 0) between time 202 and time 204. Time 202 signifies the end of the charging phase of the transfer reference capacitors 132a and 132b, and the sampled VIN charge on the input capacitors 130a and 130b. Time 204 signifies the beginning of the transfer phase of the charge on the transfer reference capacitors 132a and 132b.

[0023] Referring to FIG. 2a, depicted is the timing diagram for transferring a plus (positive) charge, C*VREF. The transfer reference capacitors 132a and 132b are connected to VREFP and VREFM, respectively, during the precharge phase (before time 202a) and switched to VREFM and VREFP, respectively, during the transfer phase (after time 204a). The charge transferred is equal to C/2*(VREFP−VREFM)−C/2*(VREFM−VREFP)=C*VREF. When summed with the voltage input sample charge, A*C/2*(VINP−VINM)−A*C/2*(VINM−VINP)=A*C*VIN at the summing node of the input of the differential operational amplifier 150, the transferred voltage is A*VIN+VREF at the output of the differential operational amplifier 150.

[0024] Referring to FIG. 2e, depicted is the timing diagram for transferring a minus (negative) charge, C*−VREF. The opposite sequence from that shown in FIG. 2a is performed to achieve a −C*VREF charge to the summing node. When summed with the voltage input sample charge, A*C/2*(VINP−VINM)−A*C/2*(VINM−VINP)=A*C*VIN at the summing node of the input of the differential operational amplifier 150, the transferred voltage is A*VIN−VREF at the output of the differential operational amplifier 150. The charging and transferring sequences of FIGS. 2a and 2e represent a basic two level feed-back DAC of a sigma-delta modulator.

[0025] According to specific exemplary embodiments of the invention, three more charge levels are added to the basic operation of the aforementioned two-level feed-back DAC in order to achieve a five-level DAC. These three additional charge levels are C/2*VREF, 0 and −C/2*VREF.

[0026] Referring to FIG. 2b, in order to achieve a C/2*VREF charge transfer, the transfer reference capacitors 132a and 132b are connected to VREFP and VREFM, respectively, during the precharge phase (before time 202b) and have their input plates short-circuited during the transfer phase (after time 204b). The charge transferred is then equal to C/2*(VREFP−VREFM) −0=C/2*VREF. When summed with the voltage input sample charge, A*C/2*(VINP−VINM) −A*C/2*(VINM−VINP)=A*C*VIN at the summing node of the input of the differential operational amplifier 150, the transferred voltage is A*VIN+VREF/2 at the output of the differential operational amplifier 150.

[0027] Referring to FIG. 2c, in order to achieve a zero charge transfer, the input plates of the transfer reference capacitors 132a and 132b are short-circuited during both the precharge phase (before time 202c) and the transfer phase (after time 204c). When summed with the voltage input sample charge, A*C/2*(VINP−VINM)−A*C/2*(VINM−VINP)=A*C*VIN at the summing node of the input of the differential operational amplifier 150, the transferred voltage is A*VIN+0 at the output of the differential operational amplifier 150.

[0028] Referring to FIG. 2d, In order to achieve a −C/2*VREF charge transfer, the transfer reference capacitors 132a and 132b are connected to VREFM and VREFP, respectively, during the precharge phase (before time 202d) and have their input plates short-circuited during the transfer phase (after time 204d). The charge transferred is then equal to C/2*(VREFM−VREFP) −0=−C/2*VREF. When summed with the voltage input sample charge, A*C/2*(VINP−VINM) −A*C/2*(VINM−VINP)=A*C*VIN at the summing node of the input of the differential operational amplifier 150, the transferred voltage is A*VIN−VREF/2 at the output of the differential operational amplifier 150.

[0029] It is also contemplated and within the scope of the present invention that the intermediate levels C*VREF/2, 0 and −C*VREF/2 can also be achieved through other switching sequences then what are described herein. E.g., short-circuiting the input plates of transfer reference capacitors 132a and 132b during precharge and connecting them to VREFM and VREFP, respectively, generates a C*VREF/2 charge transfer. In a similar fashion, short-circuiting the input plates of transfer reference capacitors 132a and 132b during precharge and connecting them to VREFP and VREFM, respectively, generates a −C*VREF/2 charge transfer. Maintaining connection of the input plates of transfer reference capacitors 132a and 132b to the same potential during the precharge and transfer phases induces a zero charge transfer.

[0030] FIG. 1 depicts a two phase implementation (charge and transfer) where the signal (VINP−VINM) and reference (VREFP−VREFM) are processed in parallel with the signal path having a gain A. It is contemplated and within the scope of the present invention that a four (4) phase scheme may be applied where the signal (VINP−VINM) and reference (VREFP−VREFM) share the same capacitors (capacitors 130 and 132 become the same capacitors) in order to have an accurate gain of one (1) that is matching insensitive. It is contemplated and within the scope of the present invention that any multiphase scheme may be applied as well as rotating capacitor gain techniques or dynamic matching.

[0031] The invention, therefore, is well adapted to carry out the objects and attain the ends and advantages mentioned, as well as others inherent therein. While the invention has been depicted, described, and is defined by reference to specific embodiments of the invention, such references do not imply a limitation on the invention, and no such limitation is to be inferred. The invention is capable of considerable modification, alteration, and equivalents in form and function, as will occur to those ordinarily skilled in the pertinent arts and having the benefit of this disclosure. The depicted and described specific embodiments of the invention are exemplary only, and are not exhaustive of the scope of the invention. Consequently, the invention is intended to be limited only by the spirit and scope of the appended claims, giving full cognizance to equivalents in all respects.