Converter with synchronous rectifier with ZVS

[0001] The present invention relates to switching power supplies and particularly to a method and circuit for controlling synchronous rectifiers used in ZVS DC/DC converter.

[0002] As the same with most power supply products, the development trends of DC/DC converter is towards high efficiency, high power density, high reliability and, low cost. For a conventional ZVS DC/DC converter with the diode rectification, the conduction loss of the diode rectifier is normally about 30%–40% of the total loss of the converter. Obviously, in order to further improve the efficiency of the DC/DC converter, it is a good idea to reduce the conduction loss of the rectifier. Synchronous rectifier, which has the lower conduction loss, may be used in DC/DC converter. Although the employment of the synchronous rectifier can significantly reduce the conduction loss, the driver issue of the synchronous rectifier has to be considered.

[0003] From the point of view of the synchronous rectifier, the ideal operation mode of the driver is: turning on the synchronous rectifier as soon as the body diode conducts, and turning off the synchronous rectifier as soon as the current flows through the synchronous MOSFET crosses to zero. The advantage of the aforementioned mode is that the conduction time of the body diode is nearly zero to avoid the additional conduction loss and the reverse recovery relevant loss.

[0004] Obviously, the control of the synchronous rectifier contains two key points: turning on and turning off. If the synchronous rectifier is turned on before the voltage V_DS decreased to zero and body diode conducted, it will result in the parasitic capacitor discharging loss: P=0.5C_ossV_DS2f_s. If the synchronous rectifier is turned on after the diode conducted by time τ, it will result in the additional conduction loss: P=I_d(V_D−V_MOS) τf_s. If the synchronous rectifier is turned off before the current of MOSFET I_d decreased to zero, it means the body diode conducts current just before it was turned off. It will cause not only the additional conduction loss, but also severe reverse recovery losses. Normally, the higher voltage rating of the MOSFET is, the poorer reverse recovery characteristics of the body diode is. If the synchronous rectifier is turned off after the MOSFET current I_d crossed zero, the direction of the MOSFET current I_d will be changed. As a result, after turning off the MOSFET, the severe voltage overshoot occurs across the drain to source terminal of the MOSFET so that the MOSFET suffers the risk of voltage breakdown.

[0005] Typically, there are two types of the synchronous rectifier driving modes: current driving mode and voltage driving mode. The principle of the current driving mode is very simple. To sense the current flowing through the synchronous rectifier and turn on the synchronous rectifier when the current crosses zero to a positive value, the synchronous rectifier must be turned off when the current crosses zero to negative value. This is the optimum synchronous rectifier driving mode theoretically. This driving mode is able to avoid the conduction of the body diode of the synchronous rectifier and hence to avoid the additional conduction loss and reverse recovery loss. Two optional current sensing methods including the direct sensing method and indirect sensing method can be employed to sense the current of the synchronous rectifier. The indirect sensing method subtracts the magnetizing current from the transformer primary current to get the reflected secondary current of the synchronous rectifier. The disadvantage of the indirect sensing method is the precision level of the sensed current is not so high. The direct sensing method uses the Hall sensor, current transformer or sensing resistor to directly sense the current of the synchronous rectifier. However, the mentioned method may suffer from the high cost, big size or high loss.

[0006] Actually, the voltage driving mode is more popular in most applications. One of the voltage driving modes employs the control signals from the windings (which may be power windings or auxiliary windings) or the circuit node such as the intermediate node of the bridge leg. Another one of the voltage driving modes employs the control signals from the primary MOSFET control signals.

[0007] FIG. 1 shows a part of the typical ZVS DC/DC converter circuit. Different connections to the node A gives the different circuit topologies. If two capacitors are connected from the node A to the positive bus and negative bus, this connection gives the asymmetric controlled half bridge topology shown in FIG. 2. If two MOSFETs are connected from the node A to the positive bus and negative bus, this connection gives the phase shifted ZVS full bridge topology shown in FIG. 3.

[0008] FIG. 4 shows an asymmetric half bridge topology with the synchronous rectifier applied by the prior art. FIG. 5 shows the key waveform timing diagram applying this prior art. From FIG. 5, the synchronous rectifier S1 is turned on after the current transition of the S1 and S2 and is turned off at t_b. Therefore, the conduction time of the body diode has three phases: the current transition phase before the conduction of the synchronous rectifier S1, the primary resonant phase t_b˜t_c after turning off the synchronous rectifier S1, and the current transition phase t_c˜t_d after turning off the synchronous rectifier S1.

[0009] FIG. 6 shows a logic circuit used in phase shift full bridge topology with synchronous rectifiers which was proposed by Vijay Gangadhar Phadke in U.S. Pat. No. 6,504,739. The signals g_Q1˜g_Q4 are the control signals for the primary MOSFET and the signals g_S1˜g_S2 are for the secondary MOSFET. FIG. 7 shows the key waveform timing diagram applying this prior art shown in FIG. 6. From FIG. 7, the conduction time of the body diode has two phases: the primary resonant phase t_a˜t_c after turning off the synchronous rectifier S1, and the current transition phase t_c˜t_d after turning off the synchronous rectifier S1.

[0010] It is the main object of the present invention to provide an improved voltage driving scheme to control the synchronous rectifier. The main feature of the proposed method is that the conduction time of the synchronous rectifier is prolonged and the conduction time of the body diode is minimized at the case of no MOSFET current information.

[0011] The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed descriptions and accompanying drawings, in which:

[0026] The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only; it is not intended to be exhaustive or to be limited to the precise form disclosed.

[0027] To facilitate the explanation of the detailed technique features of the prior art and the proposed driving method, it is necessary to analyze the key current and voltage variation after the turning off of the primary MOSFET. FIG. 10 shows the detailed timing diagram of the proposed control method, which is for the asymmetric controlled half bridge topology shown in FIG. 2.

[0028] Please refer to FIG. 2, the switching power converter includes an input voltage source V_in, a first switching device Q₁ and a second switching device Q₂, a transformer T, a rectifying circuit including a first synchronous rectifier S₂ and a second synchronous rectifier S₁. The first switching device Q₁ is connected with the high end of the input voltage source V_in. The second switching device Q₂ is connected with the low end of the input voltage source V_in. The two switching devices Q₁ and Q₂ are connected in series and in parallel with the input voltage source V_in. For the substantially zero voltage switching asymmetric controlled half bridge converter, there are further two capacitors connected in series between the high end and the low end of the input voltage source V_in and connected with the high end of the primary winding

[0029] The transformer T has a primary winding and a secondary winding. The high end of the primary winding is connected with the input voltage source V_in, and the low end of the primary winding is connected with the two switching devices Q₁ and Q₂ through a resonant inductor L_r (which includes the leakage inductance of the transformer T and the external series inductance).

[0030] The first synchronous rectifier S₁ is connected with the low end of the secondary winding. The second synchronous rectifier S₂ is connected with the high end of the secondary winding.

[0031] The operation mode of the circuit will be analyzed as follows:

[0032] Mode 1 t_a˜t_b: For the asymmetric controlled half bridge topology, the steady state voltage of the node A is: U_A=D_Q1·V_in, where D_Q is the duty cycle of Q₁. Primary MOSFET is turned off at t_a. In this time, the primary current charges the junction capacitor of Q₁ and discharges the junction capacitor of Q₂. Before the voltage of node B falls to U_A, the voltage crossing the transformer is U_B–U_A. In this mode, the secondary MOSFET S₁ conducts, S₂ keeps in off state. The primary current i_p almost keeps the same.

[0033] Mode 2 t_b˜t_c: When the voltage of node B falls to U_A, the secondary MOSFET S₁ and S₂ both conduct and the transformer T is short. In this time, the voltage crossing the resonant inductor L_r is U_B–U_A. In this mode, a series resonance occurs between the resonant inductor L_r, the junction capacitor of S₁ and S₂, and the blocking capacitor C₁. The current of L_r will decrease and the voltage of node B will also fall. When the voltage of node B deceased to zero, ZVS can be achieved to turn on the MOSFET Q₂.

[0034] Mode 3 t_c–t_d: The primary current i_p will decrease linearly by the decreasing rate di_p/dt=U_A/L_r when Q₂ is turned on at t_c. In this mode, the current transition occurs between S₁ and S₂ by the transition rate di_s1/dt=−0.5·N·U_A/L_r, where N is the primary to secondary turn ratio. From the FIG. 2, i_s1+i_s2=i_Lf, when the current of S₂ equals to the current of filter inductor i_Lf at t_d, S₁ was turned off and the voltage crossing the transformer changed to be U_A. This mode is the so-called duty cycle loss period. After this mode, power was delivered from the primary side to the secondary side.

[0035] FIG. 3 shows a phase shift controlled ZVS full bridge topology. The difference between FIG. 2 and FIG. 3 is: the switching power converter of FIG. 3 includes two switching devices Q₃ and Q₄ connected in series between the high end and the low end of the input voltage source V_in and connected with the high end of the primary winding

[0036] Compared with the half bridge topology, because the primary MOSFET S₁ keeps conduction and voltage of the node A keeps Vin after the turning off of the MOSFET Q₃, the aforementioned current transition procedure Mode1 can be ignored for the full bridge topology. And the mode 2 and mode 3 of the full bridge topology are all the same with that of half bridge topology.

[0037] Obviously, the duration time of mode 3 t_d–t_c is the load current dependent. The more load current is, the longer duration time of mode 3 is. When the circuit operated at no load case, the duration time of mode 3 is nearly zero.

[0038] The main technique of the present invention is that the secondary MOSFET S1 is not turned off until the primary MOSFET Q2 is turned on at t_c. If the information of the load current is not available, the proposed voltage driving scheme is almost optimized to cover the whole load range.

[0039] FIG. 8 is a logic diagram of the control circuit for the asymmetric ZVS half bridge converter according to the present invention. It uses a pair of combinations of a diode, a resistor, a capacitor, and a buffer to drive the two synchronous rectifiers S₁ and S₂. The delay time of the time-delay circuit is designed to be t_c–t_b. FIG. 9 is a key wave timing diagram. From FIG. 9, the conduction time of the body diode has only one phase: the current transition phase t_c˜t_d after turning off the synchronous rectifier S₁. Compared with the prior art shown in FIG. 4, the conduction time of the body diode is shortened, therefore, the additional conduction loss is also reduced and the converter efficiency can be improved.

[0040] FIG. 11 is another logic diagram of the control method for the phase shifted ZVS full bridge converter according to the present invention. The g_Q1 to g_Q4 are the control signals for the primary MOSFET and the g_S1˜g_S2 are the control signals for the secondary MOSFET. FIG. 12 is a key wave timing diagram. From FIG. 12, the conduction time of the body diode has only one phase: the current transition phase t_c˜t_d after turning off the synchronous rectifier S₁. Compared with the prior art shown in FIG. 4, the conduction time of the body diode is shortened, therefore, the additional conduction loss is also reduced.

[0041] The synchronous rectifier driving scheme shown in FIG. 8 and FIG. 11 is the typical embodiment of the invention. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention.

[0042] FIG. 13 is another phase shifted full bridge converter with the current doubler synchronous rectifiers according to the present invention. FIG. 14 is another phase shifted full bridge converter with the full bridge synchronous rectifiers according to the present invention. The MOSFET S₁ and S₄ share the same driving signals and The MOSFET S₂ and S₃ share the same driving signals. The control methods presented in FIG. 8 and FIG. 11 can also be utilized in them to shorten the conduction time of the body diode, to reduce the additional conduction loss, and to improve the converter efficiency.

[0043] While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.