Synchronized frequency multiplier for multiple phase PWM control switching regulator without using a phase locked loop

[0001] The present invention relates to power supplies and more specifically to a synchronized frequency multiplier for a multiple phase Pulse Width Modulation (PWM) switching regulator.

[0002] A PWM switching regulator may be configured to provide a regulated output voltage to satisfy power supply and dynamic requirements of today's microprocessors and related communication systems, in response to an input voltage. For improved efficiency and other considerations, the PWM switching power supply may employ multiple phasing. In a multiple phase switching regulator with PWM control, a plurality of clock signals may be employed, which are 360 deg/M out of phase with each other, where M is the total number of employed phases.

[0003] If the switching regulator includes a synchronization capability (i.e. internal clock signals are synchronized with an input clock signal), a Phase Locked Loop (PLL) may be employed. This may result in a synchronized internal clock signal that has a frequency, which is about M-times the frequency input clock signal. This internal clock signal may then be employed using a logic function to extract clock signals for each of the phases of the switching regulator.

[0004] Thus, it is with respect to these considerations and others that the present invention has been made.

[0012] The present invention now will be described more fully hereinafter with reference to the accompanying drawings, which form a part hereof, and which show, by way of illustration, specific exemplary embodiments by which the invention may be practiced. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Among other things, the present invention may be embodied as methods or devices. Accordingly, the present invention may take the form of an entirely hardware embodiment or an embodiment combining software and hardware aspects. The following detailed description is, therefore, not to be taken in a limiting sense.

[0013] Briefly stated, the present invention is related to a method and circuit for synchronizing an input clock signal with a plurality of internal clock signals in a multiple phase Pulse Width Modulation (PWM) switching power supply without using a Phase Locked Loop (PLL). A frequency to voltage converter is arranged to measure the input clock signal. A reference capacitor charged by a constant current source is arranged to generate a reference voltage with a substantially constant slope. A change in the reference voltage across the reference capacitor may be substantially inversely proportional to a frequency of the input clock. By providing the reference voltage to a sample-and-hold module and using an output of the sample-and-hold module to feed a comparator, synchronization may be accomplished. For each internal clock signal that represents a different phase, a different reference capacitor and current source module may be implemented.

[0014] While a preferred embodiment of the present invention may be implemented in a dual phase PWM switching regulator circuit, the invention is not so limited. The described circuit may be employed as part of virtually any multiple-phase PWM switching regulator circuit known to those skilled in the art.

[0015] FIG. 1 illustrates a block diagram of an embodiment of multiple phase PWM circuit 100 in which the present invention may be practiced. PWM circuit 100 may be implemented in a high frequency, high power density regulator circuit employing a multiple phase technique.

[0016] Increases in an amount of current and demand for faster response time by typical loads for PWM switching regulators, such as microprocessors, and the like, have lead to higher switching frequencies. A higher switching frequency provides faster transient response and smaller converter size (high power density) because of the reduction in the magnetic components size and filter. In a single module, however, the switching frequency could reach such a large and impractical value that switching losses may lead to a reduced overall efficiency and provoke excessive heat.

[0017] In response to the foregoing, the multiple phase (interleave) technique provides for connecting multiple PWM switching regulators in parallel with phase shift of their control signals so that the input and output current ripple is naturally canceled while achieving fast response. Inductor currents of the interleaved phases may be added together in a lower ripple input and output current. This results in a switching frequency for each module that is lower than an output voltage ripple frequency. Accordingly, a higher output voltage ripple frequency can be achieved as the number of interleaved phases increases.

[0018] Moreover, an effective output inductance is reduced because of the parallel configuration and the transient response is improved. By increasing the number of paralleled phases, higher current capability may be achieved. Thermal problems may also be easier to handle in a multiple phase converter.

[0019] PWM circuit 100 includes PWM control circuit 111 and PWM comparator 103. PWM control circuit 111 includes timing circuit 101, which includes synchronized frequency multiplier circuit 110, and ramp voltage generator 102. Timing circuit 101 is arranged to receive input clock signal Clk and provide, in response, a plurality of phase-shifted internal clock signals Clk_M, where N is an integer between one and M, a total number of clock signals. A total number of internal clock signals may be predetermined by synchronized frequency multiplier circuit 110. In one embodiment, Timing circuit 101 may provide additional timing signals to other circuitry either generated internally by timing circuit 101 or based on input clock signal Clk.

[0020] Synchronized frequency multiplier circuit 110 is arranged to generate the plurality of phase-shifted internal clock signals Clk_M and synchronize them with input clock signal Clk. As described in more detail below, each phase-shifted internal clock signal may be generated by a separate reference capacitor and a current source module. A number of the reference capacitors and the current source modules in synchronized frequency multiplier circuit 110 may depend on the number of employed internal clock signals.

[0021] Ramp voltage generator 102 is arranged to receive the plurality of phase-shifted internal clock signals Clk_M and to provide, in response to the clock signals, ramp voltage V_rampΦ to PWM comparator 103.

[0022] PWM comparator circuit 103 is arranged to receive V_rampΦ and error voltage V_err from an error amplifier and to provide multi-phase pulse width modulating voltage V_pwmΦ. In one embodiment, V_pwmΦ may be provided to an input of a driver circuit, which comprises parallel arranged driver elements each controlling a voltage converting element or a current converting element of a regulator device.

[0023] FIG. 2 illustrates a block diagram of an embodiment of multiple phase PWM regulator circuit 205 which includes PWM circuit 100 of FIG. 1. PWM regulator circuit 205 further includes driver circuit 204, converter circuit 206, feedback circuit 208, and error amplifier 209.

[0024] As described above, PWM circuit 200 is arranged to receive input clock signal Clk and provide, in response, multi-phase pulse width modulating voltage V_pwmΦ that is in part based on a plurality of phase-shifted internal clock signals Clk_M. The multiple clock signals enable a multi-phase operation of PWM regulator circuit 205 with a total number of phases based on the total number of internal clock signals.

[0025] Driver circuit 204 includes parallel coupled driver elements 204-1 through 204-N, which are arranged to receive individual phase shifted components of V_pwmΦ (V_pwm—1 through V_pwm—N) and to provide drive voltages V_drv—1 through V_drv—N, respectively, to converter circuit 206. Depending on a type of converter circuit 206, driver circuit 204 may include appropriate components to control converter elements 206-1 through 206-N of converter circuit 206.

[0026] Converter circuit 206 is arranged to receive input voltage V_IN and provide phase-shifted regulated voltages to output circuit 207 in response to V_IN and V_drv—1 through V_drv—M. Converter circuit 206 includes converter elements 206-1 through 206-N, each of which is arranged to receive a drive voltage such as V_drv—N and V_IN, and to provide a regulated voltage. Because each converter element is driven by a phase-shifted drive voltage, regulated outputs of converter elements 206-1 through 206-M are phase-shifted by substantially the same amount as V_drv—1 through V_drv—N. In one embodiment, converter circuit 206 may be implemented as a switching converter. Accordingly, converter elements 206-1 through 206-N may comprise MOSFET switch transistors, each driven by a driver element. Such an embodiment of PWM regulator 205 is a PWM switching regulator power supply.

[0027] In another embodiment, converter circuit 206 may include a linear power pass circuit making PWM regulator 205 a PWM linear regulator circuit. Furthermore, Converter circuit 206 may be configured to regulate at least one of a voltage and a current.

[0028] In one implementation of the PWM switching regulator power supply, converter circuit 206 may include two virtually identical step-down-switch-mode power supply (SMPW) circuits. In another implementation, where more than two phases may be employed for multiplexing, more than two converter circuits may be implemented.

[0029] Feedback circuit 208 is arranged to receive V_OUT and provide feedback voltage V_fb based on V_OUT. In one embodiment, feedback circuit 208 may include a resistor circuit, a voltage divider circuit, and the like. Error amplifier 209 is arranged to receive feedback voltage V_fb and provide an error voltage V_err, which is based on V_fb, to PWM circuit 200. V_err may be provided to an input of a PWM comparator within PWM circuit 200 to be compared with V_rampΦ.

[0030] Output circuit 207 is arranged to receive multiple phase voltage from converting elements and provide combined output voltage V_OUT. Output circuit 207 may include an output inductor, an RC filter circuit, and an output capacitor, and the like.

[0031] FIG. 2 shows a particular arrangement of inputs and outputs of the various components. In one embodiment, all of the components of multiple phase PWM regulator circuit 205 may be included in the same chip. Alternatively, one or more of the components may be off-chip.

[0032] FIG. 3 illustrates a schematic block diagram of one embodiment of synchronized frequency multiplier circuit 310. Synchronized frequency multiplier circuit 310 may be implemented as part of multiple phase PWM circuit 100 of FIG. 1. Synchronized frequency multiplier circuit 310 includes one-shot trigger circuit 312, internal clock generation circuits 316 and 318, and buffer 314. Internal clock generation circuit 316 includes switches 322 and 324, current sources I_ref and I₂, capacitors C_ref and C₂, sample-and-hold module 320, and comparator 328. Internal clock generation circuit 318 includes switch 326, current source I_M, capacitor C_M, and comparator 330.

[0033] When synchronized frequency multiplier 310 is in operation, one-shot trigger circuit 312 is arranged to provide a pulse based on input clock signal Clk. First internal clock signal Clk_1 is provided by passing an output of one-shot trigger circuit 312, In_Clk, through buffer 314. Accordingly, Clk_1 is synchronized with Clk and has about the same phase.

[0034] In operation, reference capacitor C_ref is arranged to be charged by a current from reference current source I_ref. Switch 322 is arranged to be closed upon being triggered by In_Clk from one-shot trigger circuit 312 and thereby discharge C_ref. V_ref is a voltage across C_ref that is provided to sample-and-hold module 320. Sample-and-hold module 320 is arranged to sample V_ref in response to a timing signal based on Clk, and hold a peak value of V_ref. Sample-and-hold module 320 then provides the peak value of V_ref to an input of comparator 328.

[0035] Another input of comparator 328 is provided with V(C₂), which is across second capacitor C₂. C₂ may have substantially same capacitance as C_ref and be charged by constant current source I₂. Constant current source I₂ may be arranged to provide a current that has a magnitude two times a magnitude of the current provided by I_ref. This may result in a slope of V(C₂) being twice a slope of V_ref. Similar to the other input of comparator 328, switch 324 is arranged to close based on In_Clk and discharge C₂.

[0036] Comparator 328 may provide a high output every time V(C₂) exceeds the peak of V_ref. Accordingly, Clk_2 may include a pulse with a delay of ½ times a period of Clk (i.e. 180 degree phase shift). A pulse width of Clk_2 is determined by a one-shot circuitry.

[0037] The above described mechanism provides a dual phase internal clock, and may be generalized for a multiple phase circuit by adding as many internal clock generation circuits, such as internal clock generation circuit 318, as needed. In internal clock generation circuit 318, representing additional internal clock generation circuits, switch 326 is controlled by one-shot clock signal In_Clk. Capacitor C_M has about the same capacitance as C_ref, and current source I_M is arranged to provide a current that has a magnitude

[0038] $\frac{M}{M-N+1}$
times the magnitude of the current provided by I_ref, where M represents a total number of internal clock generation circuits, and N is an integer representing the circuit number with a value between one and M. For example, in a triple phase circuit the currents may be

[0039] $I_1=\frac{3}{3}*I_{\mathrm{ref}}=1*I_{\mathrm{ref}};I_2=\frac{3}{2}*I_{\mathrm{ref}}=1.5*I_{\mathrm{ref}};$
and

[0040] $I_3=\frac{3}{1}*I_{\mathrm{ref}}=3*I_{\mathrm{ref}}.$

[0041] This results in a slope of voltage V(CM) across capacitor CM being

[0042] $\frac{M}{M-M+1}$
times the slope of V_ref. Comparator 330 may provide a high value for Clk_M whenever V(C_M) exceeds V_ref. Accordingly, Clk_M has a phase shift of

[0043] $\frac{M-1}{M}*360$
degrees.

[0044] FIG. 4 schematically illustrates one embodiment of dual phase synchronized frequency multiplier circuit 410. Synchronized frequency multiplier circuit 410 may be an N=2 implementation of internal clock generation circuit 316 of FIG. 3. Synchronized frequency multiplier circuit 410 includes inverters 432 and 438, one-shot circuits 412 and 462, current source 444, comparator 460, transistors M446, M448, M450, M452, M454, M456, and M458. Synchronized frequency multiplier circuit 410 further includes capacitors C_ref, C_SH, and C₂. Voltage source 436 represents a source for input clock signal Clk. Voltage source 434 represents a shutdown signal.

[0045] Transistors M452 and M454, and capacitor C_SH are arranged to operate as a sample-and-hold module that samples and provides reference voltage V_ref across C_ref to an inverting input of comparator 460. Comparator 460 is arranged to operate together with one-shot circuit 462. When one input of comparator 460 exceeds another input, comparator 460 provides a voltage to an input of one-shot circuit 462, which in turn transmits a pulse. For example, in case of the dual phase synchronized frequency multiplier circuit, comparator 460 is arranged to receive a peak value of V_ref and V(C₂) at its inputs. Whenever V(C₂) exceeds the peak value of V_ref, one-shot circuit generates a pulse (Clk_2) as explained in conjunction with FIG. 3 above.

[0046] One-shot circuit 412 is arranged to operate as a one-shot trigger circuit such as one-shot trigger circuit 312 of FIG. 3. In operation Clk may be a relatively wide pulse. One-shot circuit 412 is arranged to provide a relatively short pulse that is synchronous to a rising edge of Clk. Current source 444, and transistors M446 and M448 are arranged to operate as a reference current source, and to charge reference capacitor C_ref with a constant current. Current source 444, and transistor M446 together with transistor M456 are arranged to operate as a second constant current source, and to charge second capacitor C₂ with a constant current.

[0047] In one embodiment, a ratio of junction areas of M456 to M448 may be pre-selected such that the constant current provided to C₂ is about twice the current provided to C_ref. This may result, as described above, in a slope of V(C₂) having a slope that is twice a slope of V_ref. The difference in voltage slopes may result in activation of one-shot circuit 462 whenever V(C₂) exceeds the peak value V_ref, which is sampled and held by a sample-and-hold module comprising transistors M452, 454 and capacitor C_SH. Sample transistors M452 and M454 are arranged to be activated by Clk and deactivated by inverted Clk. This enables the sample-and-hold module to sample V_ref during its peak and forward that peak to the inverting input of comparator 460. Transistors M450 and M458 are arranged to operate as switches that enable C_ref and C₂ to be discharged based on In_Clk, respectively.

[0048] Buffer circuit 464 is arranged to receive the signal at node N466 and provide first internal clock signal Clk_1, which is synchronized with Clk, and has about the same phase.

[0049] While internal clock generation circuit 416 is shown employing MOSFET transistors and references to MOSFET technology are made throughout the specification and claims, other technologies such as BiCMOS, HBT, MESFET and BJT may also be implemented without departing from the scope or spirit of the invention. Moreover, the invention is not limited to the exemplary circuit described above. Other implementations of the present invention may be made without departing from the scope and spirit. For example, a four phase PWM regulator may include four internal clock generation circuits.

[0050] FIG. 5 illustrates timing diagram 580 of various waveforms involved in an operation of a synchronized frequency multiplier circuit such as the dual phase synchronized frequency multiplier circuit (416) of FIG. 4.

[0051] Timing diagram 580 includes one-shot clock signal In_Clk (581), which is based on input clock signal Clk, second capacitor voltage V(C₂) (582), reference capacitor voltage V_ref (583), first internal clock signal Clk_1 (584), and second internal clock signal Clk_2 (585).

[0052] As waveform 581 shows, input clock signal In_Clk changes its frequency after four pulses. When the circuit is operating, reference capacitor C_ref generates a sawtooth-shaped reference voltage V_ref, which has about the same period as the input clock signal and reaches its peak at sampled peak value. As described in FIG. 3, C₂ is arranged to have about the same capacitance as C_ref. Because a current charging C₂ has about twice the magnitude of a current charging C_ref, V(C₂) (582) may have a slope that is twice a slope of V_ref, and therefore a peak value that is about twice a peak value of reference voltage V_ref, while having about the same frequency.

[0053] First internal clock signal Clk_1 is synchronized with In_Clk having about the same phase. In a dual phase circuit such as synchronized multiplier circuit 416 of FIG. 3, second internal clock signal Clk_2 is generated whenever V(C₂) exceeds the sampled peak value of V_ref. Because V(C₂) has about twice the slope of V_ref, it is bound to exceed the sample peak value at about half period of In_Clk resulting in 180 degrees phase shift of Clk_2 from Clk_1, as waveforms 584 and 585 shows.

[0054] When the frequency of In_Clk changes, a peak and a frequency of V_ref and V(C₂) change as well. As determined by V_ref and V(C₂), Clk_1 and Clk_2 change their frequency to about the same value as In_Clk maintaining their 180 degree phase difference.

[0055] The above specification, examples and data provide a description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention also resides in the claims hereinafter appended.