Motor control circuit for supplying a controllable driving voltage

[0001] 1. Field of the Invention

[0002] The present invention relates to a motor control circuit and, more particularly, to a motor control circuit for supplying a controlling driving voltage to a motor.

[0003] 2. Description of the Related Art

[0004] Generally speaking, an H-bridge circuit constructed by four switch transistors may supply a driving voltage to a motor, such as DC motor, stepping motor, voice coil motor, and the like, for controlling a rotating direction, a rate of rotation, and other operational characteristics.

[0005] FIG. 1 is a circuit diagram showing a conventional H-bridge circuit 10 for driving a motor M. Referring to FIG. 1, the motor M is coupled between a supply voltage source V_m and a ground potential through the H-bridge circuit 10. Although the motor M is in practice a complex system consisting of a variety of mechanical and electrical components, the driving voltage is essentially applied to a winding of the motor M for generating a magnetic field. Consequently, the term “motor” in this specification primarily refers to the winding of the motor M, which may be reduced to an inductive load for a simpler consideration. The drawing also emphasizes this consideration by illustrating the representative winding of the motor M.

[0006] The H-bridge circuit 10 includes four N-channel MOSFET transistors (NMOS) Q₁ to Q₄. The NMOS transistor Q₁ has a drain electrode coupled to the supply voltage source V_m and a source electrode coupled to a terminal A of the motor M. The NMOS transistor Q₂ has a drain electrode coupled to the supply voltage source V_m and a source electrode coupled to a terminal B of the motor M. The NMOS transistor Q₃ has a drain electrode coupled to the terminal A of the motor A and a source electrode coupled to a ground potential. The NMOS transistor Q₄ has a drain electrode coupled to the terminal B of the motor M and a source electrode coupled to the ground potential.

[0007] Since the NMOS transistors Q₁ to Q₄ have parasitic diodes D₁ to D₄, respectively, the H-bridge circuit 10 needs not to be additionally provided with flywheel diodes. If the four switch transistors of the H-bridge circuit 10 are implemented by bipolar junction transistors, however; the diodes D₁ to D₄ shown in FIG. 1 should be additionally provided.

[0008] The gate electrodes of the NMOS transistors Q₁ to Q₄ are controlled by control signals G₁ to G₄, respectively. When the control signals G₁ and G₄ are at a logic high level and the control signals G₂ and G₃ are at a logic low level, the NMOS transistors Q₁ and Q₄ are turned on and the NMOS transistors Q₂ and Q₃ are turned off such that the terminal A is coupled to the supply voltage source V_m through the conductive NMOS transistor Q₁ and the terminal B is coupled to the ground potential through the conductive NMOS transistor Q₄. As a result, the supply voltage source V_m applies a driving voltage to the motor M, causing a driving current I₁ to flow through the motor M in a direction from the terminal A toward the terminal B. When the control signals G₁ and G₄ are at the logic low level and the control signals G₂ and G₃ are at the logic high level, the NMOS transistors Q₁ and Q₄ are turned off and the transistor Q₂ and Q₃ are turned on such that the terminal B is coupled to the supply voltage source V_m through the conductive NMOS transistor Q₂ and the terminal A is coupled to the ground potential through the conductive NMOS transistor Q₃. As a result, the supply voltage source V_m applies another driving voltage to the motor M, causing another driving current I₂ to flow through the motor M in another direction from the terminal B toward the terminal A.

[0009] Among the various applications of using the motor M, the driving voltage applied between the terminals A and B determines practical operational characteristics of the motor M and therefore needs to satisfy several requirements of application. At first, a polarity and an absolute value of the driving voltage should belong to a controllable quantity because the polarity of the driving voltage determines a direction of the magnetic field generated by the winding of the motor M and the absolute value of the driving voltage determines a strength of the magnetic field generated by the motor M. Especially when the motor M needs to be operated in a constant voltage driving condition, the absolute value of the driving voltage must be kept constant.

[0010] Conventionally, a pulse width modulation (PWM) technique is usually adopted to control the absolute value of the driving voltage applied to the motor. More specifically, in the situation where the NMOS transistor Q₄ is turned on and the NMOS transistors Q₂ and Q₃ are turned off, the control signal G₁ may be implemented by a PWM signal such that the ON time of the NMOS transistor Q₁ is determined by the duty cycle of the PWM control signal G₁, thereby controlling an average value of the driving voltage. However, the PWM technique inevitably induces excessive disturbances in the supply voltage source V_m and the driving voltage applied to the motor M. For the application which requires extremely precise control of the motor, the conventional PWM technique may cause several disadvantageous effects. Therefore, it is desired to provide a control circuit capable of supplying a low noise driving voltage to the motor M.

[0011] An object of the present invention is to provide a motor control circuit capable of controlling a polarity and an absolute value of the driving voltage for a motor.

[0012] Another object of the present invention is to provide a motor control circuit capable of keeping constant an absolute value of a driving voltage for a motor.

[0013] Still another object of the present invention is to provide a motor control circuit capable of suppressing noise of a driving voltage for a motor.

[0014] According to the present invention, a motor control circuit is provided for supplying a driving voltage to a motor. The driving voltage is applied between a first terminal and a second terminal of the motor. The motor control circuit includes: an H-bridge circuit, a voltage detection circuit, an error amplifier, a feedback circuit, and a state control circuit.

[0015] The H-bridge circuit has a first linear unit, a second linear unit, a first switching unit, and a second switching unit. The first linear unit and the first switching unit are together coupled to the first terminal. The second linear unit and the second switching unit are together coupled to the second terminal. The voltage detection circuit generates at least one voltage detection signal representative of the driving voltage of the motor. The error amplifier generates at least one error signal representative of a difference between the at least one voltage detection signal and a command voltage signal. The at least one error signal is electrically separate from the first and the second switching units. The feedback circuit is coupled to the error amplifier for receiving the at least one error signal so as to apply the at least one error signal selectively to the first or the second linear unit. The state control circuit synchronously controls the first and the second switching units and the feedback circuit.

[0016] During a first operational period, the first switching unit is operated in a nonconductive mode, the second switching unit is operated in a conductive mode, the feedback circuit allows one of the at least one error signal to be applied to the first linear unit for operating the first linear unit in a linear mode, and the feedback circuit prevents the at least one error signal from being applied to the second linear unit. Therefore, the driving voltage is controlled to become substantially proportional to the command voltage signal. At this moment, the driving voltage causes a current to flow through the motor in a direction from the first terminal toward the second terminal.

[0017] During a second operational period, the first switching unit is operated in the conductive mode, the second switching unit is operated in the nonconductive mode, the feedback circuit prevents the at least one error signal from being applied to the first linear unit, and the feedback circuit allows another of the at least one error signal to be applied to the second linear unit for operating the second linear unit in the linear mode. Therefore, the driving voltage is controlled to become substantially proportional to the command voltage signal. At this moment, the driving voltage causes a current to flow through the motor in a direction from the second terminal toward the first terminal.

[0018] The voltage detection circuit includes a first voltage divider and a second voltage divider. The first voltage divider is coupled between the first terminal and a ground potential, for outputting a first terminal division voltage signal as the one of the at least one voltage detection signal. The second voltage divider is coupled between the second terminal and the ground potential, for outputting a second terminal division voltage signal as the another of the at least one voltage detection signal.

[0019] The error amplifier includes a first, a second, and a third NMOS transistors, and a first, a second, and a third current mirrors. The first NMOS transistor has a gate electrode controlled by the first terminal division voltage and a source electrode coupled to a constant current source. The second NMOS transistor has a gate electrode controlled by the second terminal division signal and a source electrode coupled to the constant current source. The third NMOS transistor has a gate electrode controlled by the command voltage signal and a source electrode coupled to the constant current source. The first current mirror has an original current branch coupled to a drain electrode of the first NMOS transistor and a drain electrode of the second NMOS transistor. The second current mirror has an original current branch coupled to a drain electrode of the third NMOS transistor. The third current mirror has an original current branch coupled to a mirror current branch of the first current mirror. A first output terminal is coupled to a mirror current branch of the second current mirror and a mirror current branch of the third current mirror, for supplying the one of the at least one error signal.

[0020] The second current mirror further has a parallel mirror current branch coupled in parallel with the mirror current branch of the second current mirror. The third current mirror further has a parallel mirror current branch coupled in parallel with the mirror current branch of the third current mirror. The error amplifier further includes a second output terminal coupled to the parallel mirror current branch of the second current mirror and the parallel mirror current branch of the third current mirror, for supplying the another of the at least one error signal.

[0021] The feedback circuit includes a first and a second switching means. The first switching means is coupled to the first linear unit and controlled by the state control circuit. During the first operational period, the first switching means allows the one of the at least one error signal to be applied to the first linear unit. During the second operational period, the first switching means prevents the at least one error signal from being applied to the first linear unit. The second switching means is coupled to the second linear unit and controlled by the state control circuit. During the first operational period, the second switching means prevents the at least one error signal from being applied to the second linear unit. During the second operational period, the second switching means allows the another of the at least one error signal to be applied to the second linear unit.

[0022] The state control circuit synchronously outputs a first to a fourth state control signals, for controlling the first and the second switching means of the feedback circuit and the first and the second switching units of the H-bridge circuit, respectively. Each of the first to the fourth state control signals is a digital logic signal having a logic high level and a logic low level. During the first operational period, the first and the third state control signals are at the logic low level and the second and the fourth state control signals are at the logic high level. During the second operational period, the first and the third state control signals are at the logic high level and the second and the fourth state control signals are at the logic low level.

[0023] The motor control circuit further includes a brake circuit controlled by the state control circuit. During a third operational period, the brake circuit transforms the at least one error signal to become at least one brake signal. The at least one brake signal is applied through the feedback circuit simultaneously to the first and the second linear units for operating the first and the second linear units in the linear mode. During the third operational period, the state control circuit operates the first and the second switching units in the nonconductive mode.

[0024] The state control circuit further outputs a brake control signal, which is a digital logic signal having a logic high level and a logic low level. The brake control signal is outputted to the brake circuit for transforming the at least one error signal to become the at least one brake signal. During the third operational period, the first to the fourth state control signals are at the logic low level and the brake control signal is at the logic high level.

[0030] The preferred embodiments according to the present invention will be described in detail with reference to the drawings.

[0031] FIG. 2 is a circuit diagram showing an example of a motor control circuit 20 according to the present invention. Referring to FIG. 2, the motor control circuit 20 includes an H-bridge circuit 21, a voltage detection circuit 22, an error amplifier 23, a feedback circuit 24, and a state control circuit 25.

[0032] The H-bridge circuit 21 includes two linear units LQ₁ and LQ₂ and two switching units SQ₁ and SQ₂. The linear units LQ₁ and LQ₂ couple a supply voltage source V_m and a motor M while the switching units SQ₁ and SQ₂ couples the motor M and a ground potential. The linear units LQ₁ and LQ₂ may be operated in a linear mode, a conductive mode, and a nonconductive mode while the switching units SQ₁ and SQ₂ may be operated in the conductive mode and the nonconductive mode. The term “linear mode” refers to an operational state in which an equivalent resistance substantially linearly changes in accordance with a control signal. The term “conductive mode” refers to an operational state in which the equivalent resistance is negligible and therefore considered as a short circuit. The term “nonconductive mode” refers to an operational state in which the equivalent resistance is large enough for being considered as an open circuit.

[0033] The voltage detection circuit 22 is adopted to detect a driving voltage for the motor M, i.e. a voltage applied between terminals A and B of the motor M, and then output to the inverting input terminal (−) of the error amplifier 23 at least one voltage detection signal V_d representative of the motor driving voltage. The non-inverting input terminal (+) of the error amplifier 23 receives a command voltage signal V_com for instructing the motor control circuit 20 according to the present invention to generate a desirable motor driving voltage. The command voltage signal V_com may be set by users, adjusted according to application requirements, or controlled by other circuit components based on the feedback of operational characteristics of the motor. In the error amplifier 23, the at least one voltage detection signal V_d is compared with the command voltage signal V_com, generating at least one error signal V_e representative of a difference between the at least one voltage detection signal V_d and the command voltage signal V_com.

[0034] Based on state control signals S₁ and S₂ generated by the state control circuit 25, the feedback circuit 24 causes the at least one error signal V_e to be selectively applied to the linear unit LQ₁ or LQ₂ More specifically, when the state control signals S₁ and S₂ instructs the feedback circuit 24 that the linear unit LQ₁ is to be operated in the linear mode and the linear unit LQ₂ is to be operated in the nonconductive mode, the feedback circuit 24 allows the at least one error signal V_e to be applied to the linear unit LQ₁ but prevents the at least one error signal V_e from being applied to the linear unit LQ₂. In this case, the equivalent resistance of the linear unit LQ₁ substantially linearly changes in accordance with the at least one error signal V_e. When the state control signals S₁ and S₂ instructs the feedback circuit 24 that the linear LQ₁ is to be operated in the nonconductive mode and the linear unit LQ₂ to be operated in the linear mode, the feedback circuit 24 prevents the at least one error signal V_e from being applied to the linear unit LQ₁ but allows the at least one error signal V_e to be applied to the linear unit LQ₂. In this case, the equivalent resistance of the linear unit LQ₂ substantially linearly changes in accordance with the at least one error signal V_e.

[0035] The state control circuit 25 further generates other two state control signals S₃ and S₄ for controlling the switching units SQ₁ and SQ₂ to be operated in either the conductive mode or the nonconductive mode. The state control signals S₁ to S₄ synchronously generated by the state control circuit 25 are collaborative with respect to each other, thereby achieving the operational state control performed in the motor control circuit 20 according to the present invention.

[0036] More specifically, when the state control signal S₁ causes the feedback circuit 24 to selectively applies the at least one error signal V_e to the linear unit LQ₁, the state control signal S₄ operates the switching unit SQ₂ in the conductive mode. At this moment, the state control signals S₂ and S₃ operate the linear unit LQ₂ and the switching unit SQ₁ in the nonconductive mode, respectively. As a result, the terminal A of the motor M is coupled to the supply voltage source V_m though the linear unit LQ₁ operated in the linear mode while the terminal B of the motor M is connected in short circuit to the ground potential. Since the terminal B is at a substantially zero voltage, the voltage of the terminal A indicates the motor driving voltage. In this case, the driving current flows through the motor M in a direction from the terminal A toward the terminal B. As described above, the variation of the motor driving voltage is fed back to the linear unit LQ₁ through a loop constructed by the voltage detection circuit 22, the error amplifier 23, and the feedback circuit 24, causing the equivalent resistance of the linear unit LQ₁ to correspondingly change for controlling the motor driving voltage to become substantially proportional to the command voltage signal V_com.

[0037] On the other hand, when the state control signal S₂ causes the feedback circuit 24 to selectively apply the at least one error signal V_e to the linear unit LQ₂, the state control signal S₃ operates the switching unit SQ₁ in the conductive mode. At this moment, the state control signals S₁ and S₄ operate the linear unit LQ₁ and the switching unit SQ₂ in the nonconductive mode, respectively. As a result, the terminal B of the motor M is coupled to the supply voltage source V_m though the linear unit LQ₂ operated in the linear mode while the terminal A of the motor M is connected in short circuit to the ground potential. Since the terminal A is at a substantially zero voltage, the voltage of the terminal B indicates the motor driving voltage. In this case, the driving current flows through the motor M in a direction from the terminal B toward the terminal A. As described above, the variation of the motor driving voltage is fed back to the linear unit LQ₂ through a loop constructed by the voltage detection circuit 22, the error amplifier 23, and the feedback circuit 24, causing the equivalent resistance of the linear unit LQ₂ to correspondingly change for controlling the motor driving voltage to become substantially proportional to the command voltage signal V_com.

[0038] Therefore, the motor control circuit 20 according to the present invention is able to control the polarity and absolute value of the driving voltage for the motor. If the command voltage signal V_com is set as a constant, the motor control circuit 20 according to the present invention is able to keep constant the absolute value of the driving voltage for the motor. Because the motor control circuit 20 according to the present invention utilizes the linear modes of the linear units LQ₁ and LQ₂ to achieve the desired motor driving voltage, the noise of the driving voltage is effectively suppressed.

[0039] It should be noted that in the motor control circuit 20 according to the present invention, the switching units SQ₁ and SQ₂ are controlled by the state control signals S₃ and S₄ generated by the state control circuit 25, instead of the at least one error signal V_e. Particularly, the at least one error signal V_e is electrically separate from the switching units SQ₁ and SQ₂. As a primary function, the at least one error signal V_e is selectively fed back to operate the linear unit LQ₁ or LQ₂ in the linear mode.

[0040] In the embodiment shown in FIG. 2, the linear units LQ₁ and LQ₂ may be implemented by NMOS transistors. The linear unit LQ₁ has a drain electrode coupled to the supply voltage source V_m and a source electrode coupled to the terminal A of the motor M. The linear unit LQ₂ has a drain electrode coupled to the supply voltage source V_m and a source electrode coupled to the terminal B of the motor M. The switching units SQ₁ and SQ₂ may be implemented by NMOS transistors. The switching unit SQ₁ has a drain electrode coupled to the terminal A of the motor M and a source electrode coupled to the ground potential. The switching unit SQ₂ has a drain electrode coupled to the terminal B of the motor M and a source electrode coupled to the ground potential.

[0041] It should be noted that the H-bridge circuit 21 shown in FIG. 2 needs not to be additionally provided with flywheel diodes since the NMOS transistors have parasitic diodes D₁ to D₄. If the linear units LQ₁ and LQ₂ and the switching units SQ₁ and SQ₂ of the H-bridge circuit 21 are implemented by bipolar junction transistors, however; the diodes D₁ to D₄ shown in FIG. 2 must be additionally provided.

[0042] The voltage detection circuit 22 may be constructed by two voltage dividers 22₁ and 22₂ for detecting the voltages at the terminals A and B of the motor M, respectively. The voltage divider 22₁ is implemented by resistors R₁ and R₃ series-connected between the terminal A and the ground potential. The voltage detection signal V_d1 is asserted at the coupled point of the resistors R₁ and R₃, having a ratio of R₃/(R₁+R₃) with respect to the voltage at the terminal A. The voltage divider 22₂ is implemented by resistors R₂ and R₄ series-connected between the terminal B and the ground potential. The voltage detection signal V_d2 is asserted at the coupled point of the resistors R₂ and R₄, having a ratio of R₄/(R₂+R₄) with respect to the voltage at the terminal B. The resistors R₁ to R₄ may be designed to satisfy a condition that R₃/(R₁+R₃) is equal to R₄/(R₂+R₄). In the embodiment shown in FIG. 2, the at least one voltage detection signal V_d consists of the voltage detection signals V_d1 and V_d2, representative of the motor driving voltage.

[0043] It should be noted that although in the embodiment shown in FIG. 2 the voltage detection circuit 22 outputs two voltage detection signals V_d1 and V_d2, the present invention is not limited to this and may be applied to a case that the voltage detection circuit 22 further includes an analog comparator for obtaining a difference between the voltages of the terminals A and B to generate a single voltage detection signal V_d representative of the motor driving voltage.

[0044] The error amplifier 23 has two inverting input terminals for receiving the voltage detection signals V_d1 and V_d2, respectively. As described above, when the motor M is operated in the condition that the driving current flows from the terminal A toward the terminal B, the motor driving voltage is substantially equal to the voltage at the terminal A and the terminal B is connected in short circuit to the ground potential, so the voltage detection signal V_d1 is representative of the motor driving voltage and the voltage detection signal V_d2 is substantially zero. As a result, the error amplifier 23 compares in effect the voltage detection signal V_d1 and the command voltage signal V_com. On the other hand, when the motor M is operated in the condition that the driving current flows from the terminal B toward the terminal A, the motor driving voltage is substantially equal to the voltage at the terminal B and the terminal A is connected in short circuit to the ground potential, so the voltage detection signal V_d2 is representative of the motor driving voltage and the voltage detection signal V_d1 is substantially zero. As a result, the error amplifier 23 compares in effect the voltage detection signal V_d2 and the command voltage signal V_com.

[0045] The error amplifier 23 has two identical output terminals O₁ and O₂ for generating two identical error signals V_e1 and V_e2 as the at least one error signal V_e. The output terminal O₁ is coupled to the linear unit LQ₁ while the output terminal O₂ is coupled to the linear unit LQ₂. The feedback circuit 24 is provided with two switching means SW₁ and SW₂. The switching means SW₁ is controlled by the state control signal S₁. When the switching means SW₁ is turned on, the output terminal O₁ is connected in short circuit to the ground potential, preventing the error signal V_e1 from being applied to the linear unit LQ₁ and causing the linear unit LQ₁ to be operated in the nonconductive mode. When the switching means SW₁ is turned off, the error signal V_e1 is applied to the linear unit LQ₁ for operating the linear unit LQ₁ in the linear mode. The switching means SW₂ is controlled by the state control signal S₂. When the switching means SW₂ is turned on, the output terminal O₂ is connected in short circuit to the ground potential, preventing the error signal V_e2 from being applied to the linear unit LQ₂ and causing the linear unit LQ₂ to be operated in the nonconductive mode. When the switching means SW₂ is turned off, the error signal V_e2 is applied to the linear unit LQ₂ for operating the linear unit LQ₂ in the linear mode.

[0046] It should be noted that although in the embodiment shown in FIG. 2 the feedback circuit 24, under the control of the state control circuit 25, independently determines whether the error signal V_e1 is applied to or not to the linear unit LQ₁ and independently determines whether the error signal V_e2 is applied to or not to the linear unit LQ₂, the present invention is not limited to this and may be applied to a case that the error amplifier 23 is provided with only one output terminal for generating a single error signal V_e. In this case, the feedback circuit 24 under the control of the state control circuit 25 causes the single output terminal of the error amplifier 23 to be selectively coupled to the linear unit LQ₁ or LQ₂, thereby achieve selectively applying the single error signal V_e to the linear unit LQ₁ or LQ₂.

[0047] Since the linear units LQ₁ and LQ₂ of the H-bridge circuit 21 are operated in the linear mode, instead of being switched on and off with a high frequency according to the prior art PWM technique, the motor control circuit 20 according to the present invention avoids the induction of excessive disturbances and therefore effectively suppresses the noise of the motor driving voltage. If a greater degree of suppression to the noise of the motor driving voltage is desired, the feedback circuit 24 may further be provided with capacitors C₁ and C₂. The capacitor C₁ is coupled between the gate electrode of the linear unit LQ₁ and the ground potential such that the error signal V_e1 is relatively gradually applied to the gate electrode of the linear unit LQ₁. The capacitor C₂ is coupled between the gate electrode of the linear unit LQ₂ and the ground potential such that the error signal V_e2 is relatively gradually applied to the gate electrode of the linear unit LQ₂.

[0048] The motor control circuit 20 according to the present invention is further provided with a brake circuit 26 for simultaneously operating the linear units LQ₁ and LQ₂ in the conductive mode. More specifically, when the motor control circuit 20 performs the brake control, the state control circuit 25 outputs a brake control signal BRK to the brake circuit 26. In response to the brake control signal BRK, the brake circuit 26 transforms the at least one error signal V_e generated by the error amplifier 23 to become at least one brake signal. Under the control of the state control circuit 25, the switching units SQ₁ and SQ₂ are operated in the nonconductive mode, and the feedback circuit 24 simultaneously applies the at least one brake signal to the linear units LQ₁ and LQ₂ for operating the linear units LQ₁ and LQ₂ in the conductive mode.

[0049] More specifically, in the embodiment shown in FIG. 2, the brake circuit 26 in response to the brake control signal BRK causes the two inverting input terminals of the error amplifier 23 to be connected in short circuit to the ground potential or held at a potential lower than the command voltage signal V_com. As a result, the error signals V_e1 and V_e2 are transformed to become the brake signals having the logic high level, not any more the above-described linear signals for the feedback control. In this case, the state control circuit 25 simultaneously turns off the switching means SW₁ and SW₂ through the state control signals S₁ and S₂ such that the brake signals V_e1 and V_e2 having the logic high level are input to the gate electrodes of the linear units LQ₁ and LQ₂, respectively. The brake signals V_e1 and V_e2 having the logic high level operate the linear units LQ₁ and LQ₂ in the conductive mode, achieving the desired brake control.

[0050] In the brake control, for more rapidly transforming the error signals V_e1 and V_e2 to become the brake signals having the logic high level, the brake circuit 26 may be additionally provided with means for directly controlling the output stages of the error amplifier 23 so as to force the two output terminals O₁ and O₂ to rapidly output the brake signals V_e1 and V_e2 having the logic high level.

[0051] FIG. 3 is a detailed circuit diagram showing an example of the error amplifier 23 and the brake circuit 26 according to the present invention. First of all is described the detailed circuit of one example of the error amplifier 23 according to the present invention. An NMOS transistor N₁ has a gate electrode for receiving the voltage detection signal V_d1, an NMOS transistor N₂ has a gate electrode for receiving the voltage detection signal V_d2, and an NMOS transistor N₃ has a gate electrode for receiving the command voltage signal V_com. Each of the NMOS transistors N₁ to N₃ has a source electrode coupled to a constant current source I_ea. When the voltage detection signal V_d2 is zero, the NMOS transistor N₂ is turned off. In this case, the voltage detection signal V_d1 and the command voltage signal V_com determines a ratio of the current flowing through the NMOS transistors N₁ to the current flowing through the NMOS transistor N₃, on which a differential distribution of the constant current source I_ea depends. When the voltage detection signal V_d1 is zero, the NMOS transistor N₁ is turned off. In this case, the voltage detection signal V_d2 and the command voltage signal V_com determines a ratio of the current flowing through the NMOS transistors N₂ to the current flowing through the NMOS transistor N₃, on which a differential distribution of the constant current source I_ea depends.

[0052] PMOS transistors P₁ and P₃ form a current mirror in which the PMOS transistor P₁ serves as an original current branch and the PMOS transistor P₃ serves as a mirror current branch. The PMOS transistor P₁ is coupled to the NMOS transistors N₁ and N₂ such that the current flowing through the PMOS transistor P₃ corresponds in accordance with the mirror effect to the current flowing through the NMOS transistor N₁ (or N₂), for being representative of the voltage detection signal V_d1 (or V_d2). PMOS transistors P₂ and P₄ form another current mirror in which the PMOS transistor P₂ serves as an original current branch and the PMOS transistor P₄ serves as a mirror current branch. The PMOS transistor P₂ is coupled to the NMOS transistor N₃ such that the current flowing through the PMOS transistor P₄ corresponds in accordance with the mirror effect to the current flowing through the NMOS transistor N₃, for being representative of the command voltage signal V_com.

[0053] NMOS transistors N₄ and N₅ form still another current mirror in which the NMOS transistor N₄ serves as an original current branch and the NMOS transistor N₅ serves as a mirror current branch. The NMOS transistor N₄ is coupled to the PMOS transistor P₃ such that the current flowing through the NMOS transistor N₅ corresponds in accordance with the mirror effect to the current flowing through the NMOS transistor N₁ (or N₂), for being representative of the voltage detection signal V_d1 (or V_d2).

[0054] The output terminal O₁ of the error amplifier 23 is coupled to the PMOS transistor P₄ and the NMOS transistor N₅. When the voltage detection signal V_d1 (or V_d2) is lower than the command voltage signal V_com, the current flowing through the PMOS transistor P₄ is higher than the current flowing through the NMOS transistor N₅, resulting in that a differential current flows out of the output terminal O₁ for current equivalence. When the voltage detection signal V_d1 (or V_d2) is higher than the command voltage signal V_com, the current flowing through the PMOS transistor P₄ is lower than the current flowing through the NMOS transistor N₅, resulting in that a differential current sinks in the output terminal O₁ for current equivalence. Therefore, the error signal V_e1 may be implemented by this differential current.

[0055] PMOS transistor P₅ is coupled in parallel with the PMOS transistor P₄ for serving as a parallel mirror current branch such that the current flowing through the PMOS transistor P₅ is also representative of the command voltage signal V_com. NMOS transistor N₆ is coupled in parallel with the NMOS transistor N₅ for serving as a parallel mirror current branch such that the current flowing through the NMOS transistor N₆ is also representative of the voltage detection signal V_d1 (or V_d2).

[0056] The output terminal O₂ of the error amplifier 23 is coupled to the PMOS transistor P₅ and the NMOS transistor N₆. When the voltage detection signal V_d1 (or V_d2) is lower than the command voltage signal V_com, the current flowing through the PMOS transistor P₅ is higher than the NMOS transistor N₆, resulting in that a differential current flows out of the output terminal O₂. When the voltage detection signal V_d1 (or V_d2) is higher than the command voltage signal V_com, the current flowing through the PMOS transistor P₅ is lower than the NMOS transistor N₆, resulting in that a differential current sinks in the output terminal O₂. Therefore, the error signal V_e2 may be implemented by this differential current.

[0057] The brake circuit 26 includes NMOS transistors N₇ and N₈, which have drain electrodes coupled to the gate electrodes of the NMOS transistors N₁ and N₂, respectively, and have source electrodes together coupled to the ground potential. Gate electrodes of the NMOS transistors N₇ an N₈ are synchronously controlled by the brake control signal BRK. When the brake control signal BRK is at the logic high level, the NMOS transistors N₇ and N₈ are turned on, respectively connecting the gate electrodes of the NMOS transistors N₁ and N₂ in short circuit to the ground potential. As a result, the error signals V_e1 and V_e2 generated by the error amplifier 23 are transformed to become the brake signals having the logic high level. For more rapidly transforming the error signals V_e1 and V_e2 to become the brake signals having the logic high level, the brake circuit 26 is further provided with NMOS transistor N₉ which has a drain electrode coupled to the gate electrode of the NMOS transistor N₅ of the first output stage and the gate electrode of the NMOS transistor N₆ of the second output stage and has a source electrode coupled to the ground potential. A gate electrode of the NMOS transistor N₉ is controlled by the brake control signal BRK. When the brake control signal BRK is at the logic high level, the NMOS transistor N₉ is turned on such that the gate electrodes of the NMOS transistors N₅ and N₆ are connected in short circuit to the ground potential and then immediately become nonconductive. As a result, the error signals V_e1 and V_e2 generated by the error amplifier 23 are rapidly transformed to become the brake signals having the logic high level.

[0058] For more clearly understanding the operations of the motor control circuit 20 according to the present invention, hereinafter are exemplarily described with reference to FIG. 4 three operational situations: (1) a constant voltage driving operation for flowing a current through the motor M from the terminal A toward the terminal B, (2) a braking operation, and (3) a constant voltage driving operation for flowing a current through the motor M from the terminal B toward the terminal A.

[0059] As shown in FIG. 4, during an operational period T₁, the state control signals S₁ and S₃ are at the logic low level, the state control signals S₂ and S₄ are at the logic high level, and the brake control signal BRK are at the logic low level. Consequently, the switching means SW₁ and the switching unit SQ₁ are turned off, the switching means SW₂ and the switching unit SQ₂ are turned on, and the brake circuit 26 is at the disable state. Since the terminal B of the motor M has a substantially zero voltage due to the short circuit connection with the ground potential, the voltage detection signal V_d2 is also zero. The error signal V_e1 is a linear signal, which has a value in the linear region between the logic high level H and the logic low level L and operates the linear unit LQ₁ in the linear mode through the feedback control. The error signal V_e2 is pulled down to the ground potential due to the conductive switching means SW₂. As a result, the voltage detection signal V_d1 is kept substantially equal to the command voltage signal V_com. In other words, the voltage at the terminal A of the motor M is kept substantially proportional to the command voltage signal V_com. Therefore, when the command voltage signal V_com is a constant, the motor control circuit 20 according to the present invention effectively achieves the constant voltage driving operation for flowing the current through the motor M from the terminal A toward the terminal B.

[0060] During an operational period T₂, the state control signals S₁ to S₄ are at the logic low level and the brake control signal BRK is at the logic high level. Consequently, the switching means SW₁ and SW₂ and the switching units SQ₁ and SQ₂ are turned off. The brake circuit 26 transforms the error signals V_e1 and V_e2 to become the brake signals having the logic high level H. The brake signals V_e1 and V_e2 having the logic high level H simultaneously operate the linear units LQ₁ and LQ₂ in the linear mode. Therefore, the motor control circuit 20 according to the present invention effectively achieves the braking operation. Incidentally speaking, the terminals A and B of the motor M at this moment have a voltage substantially equal to the supply voltage source V_m, so the voltage detection signals V_d1 and V_d2 are R₃/(R₁+R₃)*V_m and R₄/(R₂+R₄)*V_m, respectively.

[0061] During an operational period T₃, the state control signals S₁ and S₃ are at the logic high level, the state control signals S₂ and S₄ are at the logic low level, and the brake control signal BRK is at the logic low level. Consequently, the switching means SW₁ and the switching unit SQ₁ are turned on, the switching means SW₂ and the switching unit SQ₂ are turned off, and the brake circuit 26 is at the disable state. Since the terminal A of the motor M has a substantially zero voltage due to the short circuit connection with the ground potential, the voltage detection signal V_d1 is also zero. The error signal V_e1 is pulled down to the ground potential due to the conductive switching means SW₁. The error signal V_e2 is a linear signal, which has a value in the linear region between the logic high level H and the logic low level L and operates the linear unit LQ₂ in the linear mode through the feedback control. As a result, the voltage detection signal V_d2 is kept substantially equal to the command voltage signal V_com. In other words, the voltage at the terminal B of the motor M is kept substantially proportional to the command voltage signal V_com. Therefore, when the command voltage signal V_com is a constant, the motor control circuit 20 according to the present invention effectively achieves the constant voltage driving operation for flowing the current through the motor M from the terminal B to the terminal A.

[0062] It should be noted that although in the embodiment shown in FIG. 2 the linear units LQ₁ and LQ₂ are coupled between the supply voltage source V_m and the motor M and the switching units SQ₁ and SQ₂ are coupled between the motor M and the ground potential, the present invention is not limited to this and may be applied to a case that the linear units LQ₁ and LQ₂ are coupled between the motor M and the ground potential and the switching units SQ₁ and SQ₂ are coupled between the supply voltage source V_m and the motor M. In this case, the terminals A and B of the motor M are connected in short circuit to the supply voltage source V_m, respectively, when the switching units SQ₁ and SQ₂ are turned on. Under the feedback control, the linear units LQ₁ and LQ₂ provide the equivalent resistances between the terminals A and B of the motor M and the ground potential, respectively.

[0063] While the invention has been described by way of examples and in terms of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications.