Switchable linear regulator

[0001] The invention relates to a linear regulator and, in particular, to a linear regulator providing a selectable output voltage.

[0002] FIG. 1 shows a conventional linear regulator commonly used by those skilled in the art. The bandgap reference circuit provides a stable voltage V_bg. Noise of the voltage V_bg is filtered out by a low pass filter typically comprising an on-chip resistor R_bg and an off-chip capacitor C_bp. The filtered signal V_ref is sent to a first input terminal of an error amplifier. In the example shown in FIG. 1, the error amplifier is an operational amplifier and the first input terminal is the negative input of the operational amplifier. A second input, which is the positive input, of the operation amplifier is connected to a first node. A PMOS pass transistor M_A is controlled by an output of the error amplifier. As shown in FIG. 1, a drain of the pass transistor M_A is treated as the output terminal of the linear regulator. In order to guarantee the output stability of the linear regulator, a large external capacitor C_OUT is typically connected to the output terminal. A first feedback resistor R₁ is connected between the drain of the pass transistor M_A and the first node. A second feedback resistor R₂ is connected between the first node and the ground. Based on the virtual short between the input terminals of the error amplifier, an output voltage V_OUT of the regulator can be adjusted by the ratio of the feedback resistors R₁ and R₂. As is known in the art, the output voltage V_OUT is determined according to the voltage signal V_ref, the first and second feedback resistors R₁ and R₂, and is obtained by

[0003] $V_{\mathrm{OUT}}=V_{\mathrm{ref}}\times \left(1+\frac{R_1}{R_2}\right).$

[0004] For some applications, multiple regulator output voltages are needed. FIG. 2 shows a conventional linear regulator which provides multiple output voltages. As shown in FIG. 2, a bandgap reference circuit is shared by two error amplifiers to reduce the required chip area. The external capacitor C_bp is also typically shared such that the number of pins and external components can be minimized. Two sets of error amplifiers (error amplifiers A and B) and pass transistors (M_A and M_B) are used and different feedback resistor ratios are provided to generate different output voltages. According to FIG. 2, the output voltages V_OUTA and V_OUTB can be found to be

[0005] $V_{\mathrm{OUTA}}=V_{\mathrm{ref}}\times \left(1+\frac{R_{\mathrm{A1}}}{R_{\mathrm{A2}}}\right)$
and

[0006] $V_{\mathrm{OUTB}}=V_{\mathrm{ref}}\times \left(1+\frac{R_{\mathrm{B1}}}{R_{\mathrm{B2}}}\right),$
respectively.

[0007] A linear regulator with a selectable output voltage is disclosed in U.S. Pat. No. 6,593,607 by Nicolas Marty et. al. As shown in FIG. 3, the linear regulator comprises a power MOS transistor 2 controlled by a differential amplifier 5. The differential amplifier 5 has an input terminal 8 receiving, via a circuit of resistors R₁, R₂, R₃ switchable by means of MOS control transistors 12 and 14, a voltage proportional to the output voltage V_OUT provided by the regulator. The regulator further includes at least two circuits for generating the control signals CTRL1 and CTRL2 for controlling the respective gates of the control transistors 12 and 14. When the control signals CTRL1 and CTRL2 are respectively at a low and high state, the output voltage V_OUT equals

[0008] $V_{\mathrm{ref}}\times \left(1+\frac{R_1+R_2}{R_3}\right).$
To the contrary, when the signals CTRL1 and CTRL2 are respectively at a high and low state, the output voltage V_OUT equals

[0009] $V_{\mathrm{ref}}\times \left(1+\frac{R_1}{R_2+R_3}\right).$
Theoretically, the desired values of the output voltage V_OUT can always be achieved by arbitrarily setting the values of the resistors R₁, R₂, and R₃. However, in practical, the values of these resistors cannot be arbitrary ones in consideration of layout matching as well as the output voltage accuracy. This fact makes the choice of the resistors become difficult, especially when the desired levels of the output voltage is more than two, in a design based on the one shown in FIG. 3.

[0010] An embodiment of a switchable linear regulator for providing a selectable output voltage comprises a constant voltage source, a differential amplifier, a pass element transistor, a first resistor, a plurality of second resistors and a plurality of switches. The differential amplifier has a first input terminal coupled to the constant voltage source and a second input terminal connected to a first node. The pass element transistor has a first terminal controlled by the differential amplifier and a second terminal connected to a supply voltage. The first resistor is connected between the pass transistor and the first node. Each second resistor comprises one end connected to the first node. Each switch is coupled between the other end of a corresponding second resistor and a fixed voltage.

[0018] FIG. 4 shows a circuit diagram of a switchable linear regulator according to an embodiment of the invention. The switchable linear regulator comprises a constant voltage source CVS, a differential amplifier DA, a pass transistor M_A, a first resistor R_b, two second resistors R₁, R₂, a first switch SW₁, and a second switch SW₂. The constant voltage source CVS provides a constant voltage V_ref to a first input terminal of the differential amplifier DA. A second input terminal of the differential amplifier DA is coupled to a first node A. A first terminal of the pass transistor M_A is controlled by the differential amplifier DA. A second and third terminal of the pass transistor M_A is respectively coupled to a supply voltage V_IN and the second node B. The output terminal V_OUT is coupled to the second node B. Preferably, the pass transistor M_A is a PMOS transistor and the first and second input terminals of the differential amplifier DA are respectively the negative and positive input. A first resistor R_b is connected between the first node A and second node B. Each of the second resistors R₁, R₂ has one end connected to the first node A. The first switch SW₁ is coupled between the other end of the second resistor R₁ and a fixed voltage, and is controlled by a first control signal S1. The second switch SW₂ is coupled between the other end of the second resistor R₂ and the fixed voltage, and is controlled by a second control signal S2. Preferably, the fixed voltage is a ground.

[0019] More specifically, the constant voltage source CVS of the switchable linear regulator comprises a bandgap reference circuit BR coupled to the supply voltage V_IN. Furthermore, the constant voltage source CVS may comprise a RC low pass filter connected between the first input terminal of the differential amplifier DA and the bandgap reference circuit BR. The bandgap reference circuit BR provides a stable voltage V_bg. Noise of the voltage V_bg is filtered out by a low pass filter comprising a resistor R_bg and a capacitor C_bp. The filtered signal V_ref is a constant voltage and sent to the first input terminal of the differential amplifier DA.

[0020] Moreover, the switchable linear regulator may comprise a capacitor C_OUT coupled between the output terminal and the fixed voltage. The capacitor C_OUT improves stability of the output voltage V_OUT of the switchable linear regulator.

[0021] FIG. 5 shows a circuit diagram of a switchable linear regulator derived from the one shown in FIG. 4. The switchable linear regulator further comprises an output switch unit OSU having an input and a plurality of outputs. The output switch unit OSU is controlled by the first and second control signals S1 and S2 for selectively connecting one of the plurality of outputs to the input such that the output terminal of the switchable linear regulator is further selectable according to the control signals S1 and S2. In the example shown in FIG. 5, the output switch unit OSU is employed to make the terminal V_OUTA as the active output terminal of the switchable linear regulator when the first control signal S1 triggers the first switch SW1 to be ON state; and make the terminal V_OUTB as the active output terminal of the switchable linear regulator when the second control signal S2 triggers the second switch SW2 to be ON state. In such an example, the output switch unit OSU contains a first output switch SW′₁ and a second output switch SW′₂ both connected to the input, i.e. the second node B. The first output switch SW′₁ is connected between the second node B and the output terminal V_OUTA, and is controlled by the first control signal S1. The first control signal S1 that triggers the first switch SW1 to be ON state will also trigger the first output switch SW′₁ to be ON state. The second output switch SW′₂ is connected between the second node B and the output terminal V_OUTB. The second control signal S2 that triggers the second switch SW2 to be ON state will also trigger the second output switch SW′₂ to be ON state. Compared with the linear regulator shown in FIG. 2, one differential amplifier and one pass transistor are eliminated in the circuitry of the switchable linear regulator. Thus, the chip area can be reduced and the number of pins and external components is also reduced. When the first control signals S1 triggers the switches SW₁ and SW′₁ to be ON state and the second control signal S2 triggers the switches SW2 and SW′₂ to be OFF state, V_OUT equals

[0022] $V_{\mathrm{ref}}\times \left(1+\frac{R_b}{R_1}\right)$
and the active output terminal of the switchable linear regulator is V_OUTA. On the contrary, when the first control signals S1 triggers the switches SW₁ and SW′₁ to be OFF state and the second control signal S2 triggers the switches SW2 and SW′₂ to be ON state, V_OUT equals

[0023] $V_{\mathrm{ref}}\times \left(1+\frac{R_b}{R_2}\right)$
and the active output terminal of the switchable linear regulator is V_OUTB. In this embodiment, the switchable linear regulator provides a selectable output voltage as well as a selectable output terminal. Meanwhile, the chip area and the number of pins and external components are minimized.

[0024] In order to provide an accurate output voltage, matching of the feedback resistors is typically a major concern in a regulator design. Utilization of unit cells to implement feedback resistors and inter-digitized layout improves matching thereof. In other words, the selected feedback resistor values need to have a reasonable common divisor for convenience of layout. Take a linear regulator with two selectable output voltages as an example. In FIG. 3, the design equations are respectively

[0025] $V_{\mathrm{OUT}}=V_{\mathrm{ref}}\times \left(1+\frac{R_1+R_2}{R_3}\right)$
and

[0026] $V_{\mathrm{OUT}}=V_{\mathrm{ref}}\times \left(1+\frac{R_1}{R_2+R_3}\right).$
Both equations are functions of the same three design variables and closely related to one another. In FIG. 4, however, the design equations are respectively

[0027] $V_{\mathrm{OUT}}=V_{\mathrm{ref}}\times \left(1+\frac{R_b}{R_1}\right)$
and

[0028] $V_{\mathrm{OUT}}=V_{\mathrm{ref}}\times \left(1+\frac{R_b}{R_2}\right).$
As long as the value of resistor R_b is chosen, R₁ and R₂ can be determined according to the output voltage V_OUT and the constant voltage V_ref. Thus, the regulator design is simplified.

[0029] However, when more selectable output voltages are required, the design of the invention is much simplified as compared with the conventional regulators. If three output voltages are required, the regulator in FIG. 3 is expanded to the one shown in FIG. 6. The design equations are shown as follows,

[0030] $\mathrm{CTRL1}=\mathrm{low},\mathrm{CTRL2}=\mathrm{low},\mathrm{CTRL3}=\mathrm{high}\to V_{\mathrm{OUT}}=V_{\mathrm{ref}}\times \left(1+\frac{R_1+R_2+R_3}{R_4}\right)$ $\mathrm{CTRL1}=\mathrm{low},\mathrm{CTRL2}=\mathrm{high},\mathrm{CTRL3}=\mathrm{low}\to V_{\mathrm{OUT}}=V_{\mathrm{ref}}\times \left(1+\frac{R_1+R_2}{R_3+R_4}\right)$ $\mathrm{CTRL1}=\mathrm{high},\mathrm{CTRL2}=\mathrm{low},\mathrm{CTRL3}=\mathrm{low}\to V_{\mathrm{OUT}}=V_{\mathrm{ref}}\times \left(1+\frac{R_1}{R_2+R_3+R_4}\right).$

[0031] When the same output voltages are implemented in the invention, the circuit diagram is shown in FIG. 7. The design equations are shown as follows,

[0032] $\begin{array}{c}\mathrm{S1}=\mathrm{high},\mathrm{S2}=\mathrm{low},\mathrm{S3}=\mathrm{low}\to V_{\mathrm{OUT}}=V_{\mathrm{ref}}\times \left(1+\frac{R_b}{R_1}\right)\\ \mathrm{S1}=\mathrm{low},\mathrm{S2}=\mathrm{high},\mathrm{S3}=\mathrm{low}\to V_{\mathrm{OUT}}=V_{\mathrm{ref}}\times \left(1+\frac{R_b}{R_2}\right)\\ \mathrm{S1}=\mathrm{low},\mathrm{S2}=\mathrm{low},\mathrm{S3}=\mathrm{high}\to V_{\mathrm{OUT}}=V_{\mathrm{ref}}\times \left(1+\frac{R_b}{R_3}\right).\end{array}$

[0033] It is clear that the design equations of the invention are simpler than the conventional regulators. Although only one case is given as an example to demonstrate the advantage of the invention. Its applicability to other circumstances is readily apparent. It is assumed that V_ref=1.2 V and the three output voltages are respectively 2.8 V, 2 V and 1.4 V. According to the invention, it is very easy to obtain a suitable combination of the resistors R_b=40 kΩ, R₁=30 kΩ, R₂=60 kΩ and R₃=240 kΩ.

[0034] A unit cell of 10 kΩ or 20 kΩ can be used to realize the resistor layouts. To the contrary, the design of the conventional regulator is more complicated while practically implementing it. From the design equations, it is found that 5R₃=2R₄, 9R₁=5R₂ and 3R₁=R₄. Thus, a solution of R₁=30 Ω, R₂=54 kΩ, R₃=4 kΩ and R₄=10 kΩ can be derived. Apparently, it is more difficult to find a suitable common divisor as a layout unit cell.

[0035] While the invention has been described by way of examples and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and the advantages would be apparent compared to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications.