Droop amplifier circuit

[0001] This application claims the benefit of U.S. Provisional Application No. 60/552,659 filed on Mar. 11, 2004, which is incorporated by reference herein for all intents and purposes.

[0002] 1. Field of the Invention

[0003] The present invention relates to droop amplifiers, and more particularly to a droop amplifier circuit that allows the use a relatively low performance, simple amplifier device.

[0004] 2. Description of the Related Art

[0005] In some styles of DC/DC regulators, the output voltage is desired to fall (or “droop”) proportional to the load current. A droop circuit is typically provided and configured to sense an output parameter related to the load current and control the amount of droop by providing a corresponding droop voltage. The amount of droop may be specified by the manufacturer of the load receiving power from the DC-DC regulator. The manufacturers of microprocessor typically specify source voltage level for various load levels between low or no load and full load conditions. For example, the source voltage is specified to decrease to a pre-specified voltage level when the microprocessor reaches a predetermined high load level (and usually to droop by a proportional amount in between).

[0006] A conventional droop amplifier circuit included an operational amplifier or the like which had several disadvantages. The amplifier was required to be a high speed device capable of producing high speed current output (di/dt) and fast output voltage responses (dv/dt). Each phase node of a multiphase DC-DC converter has large and fast voltage transitions which are reflected through the corresponding resistors to the inverting input of the droop amplifier. In response to every such transition of each phase node, the output of the droop amplifier had to deliver a large amount of current through a feedback capacitor very quickly to maintain feedback. Thus, the amplifier had to be capable of delivering a very high di/dt at its output. The output voltage also exhibits fast voltage transitions in response to load conditions. For example, the output voltage drops almost instantaneously in response to a large and sudden increase in the load current level. The output of the conventional droop amplifier had to respond as quickly as possible to such output voltage transitions. Thus, the output of the amplifier had to create fast voltage transitions (dv/dt) to maintain the droop voltage.

[0007] It is desired to provide a droop amplifier circuit that significantly relaxes the droop amplifier requirements.

[0008] A droop amplifier circuit according to an embodiment of the present invention is provided for a DC-DC regulator, where the droop amplifier circuit includes an amplifier, at least one first resistive device, a second resistive device, a third resistive device, and a first capacitive device. The DC-DC regulator includes at least one output inductor coupled between a corresponding phase node and an output. Each first resistive device is for coupling between a corresponding output inductor and a non-inverting input of the amplifier. The first capacitive device is for coupling between the DC-DC regulator output and an output of the amplifier. The second resistive device is for coupling between the DC-DC regulator output and an inverting input of the amplifier. The third resistive device is coupled between the inverting input and the output of the amplifier.

[0009] The exemplary droop amplifier circuit allows relaxed requirements of the amplifier. The amplifier may be a low power amplifier. It may exhibit relatively low di/dt and dv/dt responses at its output. It may be a transconductance amplifier having a high output impedance at high frequencies. In general, a relatively small, simple and low performing amplifier is sufficient to achieve the desired results. Circuit area and power are thus reduced. Low input offset voltage for the amplifier is more easily achieved as compared to the amplifier required for a conventional droop amplifier circuit.

[0010] In one embodiment, each of the first resistive devices is for coupling to a corresponding phase node of the DC-DC converter. In this case, a second capacitive device is provided for coupling between the DC-DC regulator output and the non-inverting input of the amplifier. A fourth resistive device may be coupled in parallel with the second capacitive device.

[0011] In another embodiment, the DC-DC regulator includes a current sense resistor coupled between each output inductor and the DC-DC regulator output. In this case, each first resistive device is for coupling to a corresponding current sense node. Also, a fourth resistive device may be provided for coupling between the DC-DC regulator output and the non-inverting input of the amplifier.

[0012] A multiphase DC-DC converter according to an embodiment of the present invention includes multiple switching circuits, control logic, and a droop circuit. Each switching circuit switches an input voltage through a corresponding output inductor via a corresponding phase node based on a corresponding PWM signal to develop an output voltage at an output node. The control logic monitors the output voltage and a droop voltage for developing the PWM signals. The droop circuit includes an amplifier for developing the droop voltage relative to the output node, multiple first resistors, second and third resistors and a first capacitor. Each first resistor is coupled between a corresponding output inductor and the non-inverting input of the amplifier. The first capacitor is coupled between the output node and the output of the amplifier. The second resistor is coupled between the output node and the inverting input of the amplifier. The third resistor is coupled between the inverting input and the output of the amplifier.

[0013] In one embodiment, each of the first resistors may be coupled to a corresponding phase node. In this case, a second capacitor is coupled between the output node and the non-inverting input of the amplifier. A fourth resistor may be included and coupled in parallel with the second capacitor.

[0014] In an alternative embodiment, the multiphase DC-DC converter includes multiple current sense resistors, each coupled between a corresponding output inductor and the output node. In this case, each first resistor may be coupled to a corresponding current sense node rather than to a phase node. Again, a fourth resistor may be provided and coupled between the output node and the non-inverting input of the amplifier.

[0015] A load having an output voltage droop requirement may be coupled to the output node. In a specific configuration, the load is a microprocessor.

[0024] The following description is presented to enable one of ordinary skill in the art to make and use the present invention as provided within the context of a particular application and its requirements. Various modifications to the preferred embodiment will, however, be apparent to one skilled in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described herein, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.

[0025] FIG. 1 is a simplified schematic and block diagram of a multiphase buck-mode pulse width modulation (PWM) DC-DC regulator 100 implemented according to an embodiment of the present invention. The regulator 100 includes a PWM controller or control logic 101 which provides a number “N” of PWM signals PWM1, PWM2, . . . , PWMN to respective N gate drivers GD1, GD2, . . . , GDN forming N channels for the regulator 100. The number N is any positive integer greater than one. For the first channel, the PWM1 signal is provided to the first gate driver GD1, which controls the turn-on and turn-off of a pair of electronic power switching devices or switches Q11 and Q12. In particular, the gate driver GD1 generates an upper gate switching signal UG1 provided to the control terminal (e.g., gate) of the upper (or high side) switch Q11 and generates a lower gate switching signal LG1 provided to the control terminal of the lower (or low side) switch Q12.

[0026] In the particular configuration shown, the switches Q11 and Q12 are depicted as N-channel metal-oxide semiconductor field-effect transistors (MOSFETs) having their drain-source current paths coupled in series between a pair of power supply rails (e.g., VIN and ground (GND)). Other types of electronic switching devices are contemplated. The drain of switch Q11 is coupled to VIN and its source is coupled to the source of switch Q12 at a phase node PH1. The source of Q12 is coupled to GND. The phase node PH1 is coupled to one end of an output inductor L1, having its other end coupled to a common output node VOUT developing the output signal VOUT. A node and the signal it develops are referred to herein with the same name unless otherwise indicated.

[0027] The remaining channels 2–N of the regulator 100 are configured in substantially the same manner as the first channel. The PWM2 (or PWMN) signal is provided to the gate driver GD2 (or GDN), which provides signals UG2 and LG2 (or UGN and LGN) to drive switches Q21 and Q22 (or QN1 and QN2) coupled together at phase node PH2 (or PHN). The phase node PH2 (or PHN) is coupled through output inductor L2 (or LN) to VOUT. The VOUT node is coupled to a load reservoir capacitor 105 and to a load 107 both referenced to a power supply rail (e.g., GND). The load 107 is any type of circuitry or logic, such as a microprocessor (μP) or the like. The VOUT signal is fed back to the control circuit 101 and to a droop circuit 109. The droop circuit 109 develops a droop voltage VDROOP, which is fed back to the control logic 101. The multiple phases or channels of the regulator 100 are coupled in parallel to develop the VOUT signal. The switches of each channel are alternatively activated to develop VOUT, and each phase node PH1–PHN exhibits large and fast transitions. For the multiphase regulator 100, each channel includes a separate phase node and output inductor.

[0028] In some styles of DC/DC regulators, including the DC/DC regulator 100, the output voltage VOUT is desired to fall (or “droop”) proportional to the load current. The droop circuit 109 is configured to sense an output parameter related to the load current and control the amount of droop of VOUT. In this case, the droop circuit 100 is coupled to a current sense (CS) node of each channel, shown collectively as the CSN signals, and develops VDROOP to control the amount of “droop” or decrease of the output voltage VOUT in response to load conditions. In some embodiments, as further described below, the CSN signals are the PH1–PHN signals, although other sensing locations are contemplated depending upon the particular configuration. The amount of droop may be specified by the manufacturer of one or more load components receiving power from the regulator 100. For example, the regulator 100 generates the VOUT signal at a specified voltage level, such as 1 Volt (V), to provide source voltage to a microprocessor under no-load or low-load conditions, such as drawing 10 Amperes (A) or less. The VOUT signal is specified by the manufacturer of the microprocessor to decrease to a pre-specified voltage level when the microprocessor reaches a predetermined high load level (and usually to droop by a proportional amount in between). As an example, it may be specified that VOUT drop to 0.9V when the microprocessor draws a high load current level of 50 A. The droop circuit 109 is intended to control the specified amount of droop under the various load conditions.

[0029] FIG. 2 is a schematic diagram of a conventional droop amplifier circuit 200 implemented according to prior art. The illustrated conventional droop amplifier circuit 200 is implemented for the N-channel case with N phase nodes PH1–PHN and would otherwise be used as the droop circuit 109 to implement a conventional droop method. The phase nodes PH1–PHN are coupled through corresponding resistors R1, R2, . . . , RN, respectively, to the inverting input of an amplifier A1. The amplifier A1 is typically an operational amplifier or the like. A feedback capacitor C is coupled between the inverting input and the output of the amplifier A1 and VOUT is coupled to the non-inverting input of the amplifier A1. In this simplified example, the output of the amplifier A1 provides the positive polarity (+) of the VDROOP signal and VOUT provides the negative polarity (−) of VDROOP.

[0030] The conventional droop amplifier circuit 200 has several disadvantages, particularly associated with the amplifier A1. The amplifier A1 is required to be a high speed device capable of producing high speed current output (di/dt) and fast output voltage responses (dv/dt). Each of the phase nodes PH1–PHN have large and fast voltage transitions which are reflected through the corresponding resistors R1–RN to the inverting input of the amplifier A1. In response to every such transition of the phase nodes, the output of the amplifier A1 must deliver a large amount of current through the feedback capacitor C very quickly to maintain feedback. Thus, the amplifier A1 must be capable of delivering a very high di/dt at the output. VOUT also exhibits fast voltage transitions in response to load conditions. For example, VOUT drops almost instantaneously in response to a large and sudden increase in power consumption of the load, such as from 1V to 0.9V for a concomitant immediate step in load current level. The output of the amplifier A1 must respond as quickly as possible to VOUT transitions. Thus, the output of the amplifier A1 must create fast voltage transitions (dv/dt) to maintain feedback, such as to maintain VDROOP at approximately the same level.

[0031] FIG. 3 is a schematic diagram of a droop amplifier circuit 300 implemented according to an exemplary embodiment of the present invention. In one exemplary embodiment, the droop amplifier circuit 300 is used as the droop circuit 109. In this case, the phase nodes PH1–PHN are coupled through the corresponding resistors R1, R2, . . . , RN, respectively, to the non-inverting input of an amplifier A2. The amplifier A2 is typically a transconductance amplifier or the like with a high output impedance at high frequency. VOUT is coupled to the inverting input of the amplifier A2 through a resistor RA. Alternatively, a node VOUT′ is used for coupling to the output node, further described below. A capacitor CA is coupled between the non-inverting input of the amplifier A2 and VOUT. A feedback resistor RB is coupled between the inverting input and the output of the amplifier A2. A capacitor CB is coupled between VOUT and the output of the amplifier A2. The output of the amplifier A2 provides the positive polarity (+) of the VDROOP signal and VOUT provides the negative polarity (−) of VDROOP.

[0032] The large and fast transitions of the phase nodes PH1–PHN are slowed by the combination of the input resistors R1–RN and the capacitor CA at the non-inverting input of the amplifier A2. Thus, the amplifier A2 does not have to respond with fast current transitions so that the di/dt requirement is substantially reduced. The amplifier A2 has a high output impedance at high frequency. The capacitor CB couples the fast edges of VOUT to the output of the amplifier A2, so that the amplifier A2 does not have to create fast voltage transitions at its output. Thus, the dv/dt requirement at the output of the amplifier A2 is substantially reduced. In this manner, the droop amplifier circuit 300 does not require a fast amplifier, so that a relatively small, simple and low performing amplifier is sufficient to achieve the desired results. Circuit area and power are thus reduced. Low input offset voltage for the amplifier A2 is more easily achieved as compared to the amplifier A1 of the conventional droop amplifier circuit 100.

[0033] FIG. 4 is a schematic diagram of a droop amplifier circuit 400 implemented according to another exemplary embodiment of the present invention, which may also be used as the droop circuit 109. The droop amplifier circuit 400 is substantially similar to the droop amplifier circuit 300 in which similar components assume the same reference numbers, with an additional resistor RC coupled between VOUT (or VOUT′) and the non-inverting input of the amplifier A2.

[0034] FIG. 5 is a schematic diagram of a droop amplifier circuit 500 implemented according to another exemplary embodiment of the present invention, which may also be used as the droop circuit 109. The droop amplifier circuit 500 is substantially similar to the droop amplifier circuit 400 in which similar components assume the same reference numbers, and where the capacitor CA is removed. In this case, the regulator 100 includes additional sense resistors RS1–RSN coupled between the respective output inductors L1–LN and VOUT as shown. The sense resistors RS1–RSN are very small valued resistors, such as on the order of 10 milliohms (mΩ) or the like. The resistors R1–RN are coupled to the junctions between the output inductors L1–LN and the corresponding sense resistors RS1–RSN, where the junctions form the CSN nodes or signals. The resistors R1–RN are relatively high valued resistors, such as on the order of 10 kilohms (kΩ) or the like. The droop amplifier circuit 500 is suitable for some manufacturers in which the sense resistors RS1–RSN are included for sensing the load current through the inductors L1–LN. This enables the resistors R1–RN to be coupled to the intermediate junctions between the output inductors and the sense resistors. Since the transitions of the VOUT (or VOUT′) signal are significantly smaller than the phase node transitions, the capacitor CA may be omitted. Yet the capacitor CB is still provided at the output of the amplifier A2.

[0035] FIG. 6 is a schematic diagram illustrating an alternative embodiment for resistively coupling the droop amplifiers of 300 and 400 to the output node, forming the alternative VOUT′ node. The output inductors L1–LN are each shown coupled between corresponding nodes 601 and 603, each pair representing the physical location or point where the respective output inductor is soldered to the underlying printed circuit board (PCB). Each node 601 is coupled to a respective one of the phase nodes PH1–PHN and the nodes 603 are collectively coupled to VOUT. As previously described, the phase nodes PH1–PHN are coupled through respective resistors R1–RN to the non-inverting input of the amplifier A2. As shown, the resistors R1–RN are each coupled to a corresponding one of the nodes 601 for coupling to the corresponding output inductor. Since the current flowing between each phase node and its corresponding output inductor is relative high, such as on the order of several tens of Amperes, connection of the resistors R1–RN to the specific location at which the corresponding output inductors are soldered to the PCB reduces error. The resistors R1–RN are relatively high valued resistors, such as on the order of 10 kΩ or the like as previously described.

[0036] Another set of resistors RV1–RVN each have one end coupled to a corresponding node 603 of a corresponding one of the output inductors L1–LN and another end coupled to form the VOUT′ node. In this alternative embodiment, the VOUT′ node is coupled instead to the junction between the capacitor CA and the resistor RA and forms the negative voltage reference of VDROOP rather than VOUT. The resistors RV1–RVN reduce or otherwise eliminate any errors of VDROOP that are developed by PCB trace resistance between the output inductors L1–LN and the load 107. The resistors RV1–RVN are relatively small valued resistors, such as on the order of 10 Ω or the like, as compared to the larger resistors R1–RN.

[0037] FIG. 7 is a schematic diagram illustrating an alternative embodiment for resistively coupling the droop amplifier 500 to the output node, forming the alternative VOUT′ node. In this case, the sense resistors RS1–RSN are each coupled to a corresponding one of multiple nodes 701, each representing the physical location or point where the respective sense resistor is soldered to the underlying PCB. Each of the resistors RV1–RVN has one end coupled to a corresponding one of the sense resistors RS1–RSN at a respective one of the nodes 701, and another end forming the alternative VOUT′ node. The VOUT′ node is coupled instead to the resistor RA and forms the negative voltage reference of VDROOP rather than VOUT. The resistors RV1–RVN reduce or otherwise eliminate any errors of VDROOP that are developed by PCB trace resistance between the sense resistors and the load 107. Again, the resistors RV1–RVN are relatively small valued resistors, such as on the order of 10 Ω or the like, although the sense resistors RS1–RSN are even smaller, such as on the order of 10 mΩ or like as previously described.

[0038] Although the present invention has been described in considerable detail with reference to certain preferred versions thereof, other versions and variations are possible and contemplated. For example, although the present invention is illustrated for a multiphase DC-DC regulator, it may also be applied to other types of regulators including single phase DC-DC regulators. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for providing out the same purposes of the present invention without departing from the spirit and scope of the invention as defined by the appended claims.