Temperature compensated on-chip bias circuit for linear RF HBT power amplifiers

[0001] The present disclosure relates generally to electrical circuits, and more particularly to the biasing of an amplifier.

[0002] Integrated Heterojunction Bipolar Transistor (HBT) power amplifier bias circuits are usually realized as current mirrors which typically have a temperature dependence, causing quiescent bias currents in the RF devices to vary. It is possible to configure the bias circuits so that their quiescent bias currents are constant over temperature. However when the quiescent bias currents are fixed at a specific level, high ambient temperature causes the gain in the RF devices to degrade. It is also possible make the quiescent bias current vary linearly with temperature, but linearly changing quiescent bias currents present problems at cold ambient temperature. For example, as the ambient temperature decreases the bias currents in the HBT decreases, causing amplifier linearity to degrade. Because integrated circuits (ICs) used in modern electrical systems operate over a range of temperatures, an HBT that reduces degradation of amplifier linearity would be useful.

[0011] The present disclosure is generally directed towards systems and methods to control the linearity of an amplifier in order to reduce variations in signal quality that are affected by changes in temperature. Multiple bias circuits are utilized, and their outputs combined to produce a variable bias scheme. The present disclosure is better understood with respect to FIGS. 1–7.

[0012] FIG. 1 illustrates in block diagram form a HBT Radio Frequency (RF) Amplifier Module System 90 in accordance with a specific embodiment of the present disclosure. The amplifier module 90 includes a RF Amplifier 100, a Current Bias Mirror Module 110, a Current Bias Mirror Module 120 and a Mode Control Module 130.

[0013] Mode Control Module 130 has an input to receive a control signal labeled V_CONTROL, and a pair of outputs, labeled BN1 and BN2, that provide signals labeled Bias Signal 131 and Bias Signal 132. In operation, Mode Control Module 130 receives signal V_CONTROL, and based upon the value of V_CONTROL provides appropriate output signals for outputs BN1 and BN2.

[0014] Current Bias Mirror Module 110 has an input labeled BN to receive Bias Signal 131 provided by Mode Control Module 130. Current Bias Mirror Module 110 has an input labeled V_REF coupled to receive a reference voltage V_REF, and an input connected to a supply voltage V_CC. V_REF is typically regulated to the range of 2.75–2.85 volts, while V_CC is typically based upon the voltage of a battery of a portable device. An output node of the Current Bias Mirror Module 110 provides a bias current labeled I₁, which may represent either a positive or negative contribution to the current labeled I_BIAS.

[0015] Current Bias Mirror Module 120 has an input labeled BN to receive Bias Signal 132 provided by Mode Control Module 130. Current Bias Mirror Module 120 has an input coupled to receive a reference voltage V_REF, and an input connected to a supply voltage V_CC. An output node of the Current Bias Mirror Module 120 provides a bias current labeled I₂, which may represent either a positive or negative contribution to the current labeled I_BIAS.

[0016] RF Amplifier 100, in the embodiment of FIG. 1, has three inputs and one output. One input node is labeled Bias In and receives the signal labeled I_BIAS, which is the summation of currents I₁ and I₂. Input node labeled RF In receives a signal labeled RF_IN. Another input node is connected to the supply voltage V_CC. RF Amplifier 100 has an output node labeled RF Out that provides a signal labeled RF_OUT.

[0017] In operation, the Mode Control Module 130 is controlled by the signal V_CONTROL, which is supplied from external system 90 of FIG. 1. V_CONTROL indicates to Mode Control Module 130 an operating mode of the HBT RF Amplifier Module System 90. For example, in one embodiment, V_CONTROL is a binary signal indicating whether the System 90 should be in a high-power or low-power state. In other embodiments, more than two modes can be selected. In yet another mode, the signal V_CONTROL can be an analog signal that biases a transistor in its active region. The values of output signals of Mode Control 130, BIAS SIGNAL 131 and BIAS SIGNAL 132, are determined by a value of input V_CONTROL. In turn, signals BIAS SIGNAL 131 and BIAS SIGNAL 132 control the behavior of Current Bias Mirror Modules 110 and 120. More specifically, depending upon the value of V_CONTROL, which controls BIAS SIGNAL 131, Current Bias Mirror Module 110 will supply a specific amount of current I₁ at its output node. In like manner Current Bias Mirror Module 120 will supply a specific amount of current I₂ at its output node based on the value of V_CONTROL. It should be noted that currents I₁ and I₂ are not necessarily, and indeed usually will not be, equal. The magnitude of I₁ and I₂ currents will also vary with temperature in unique manners. It is this different behavior of the currents I₁ and I₂ that, when combined, provide the nonlinear signal I_BIAS. As a result of this non-linearity over temperature of I_BIAS, the signal output of the RF Amplifier has better linearity at low temperatures when compared to prior art amplifiers while maintaining good gain characteristics at elevated temperatures.

[0018] RF Amplifier 100 receives the signal I_BIAS at node Bias In. RF Amplifier 100 also receives the signal RF_IN via node RF In and amplifies it. An amplified representation of RF_IN, labeled RF_OUT, is output via node RF Out. The amplification of signal RF_IN is controlled by the design of RF Amplifier 100, and depends upon the value of I_BIAS. The varying characteristics of signal I_BIAS over temperature allow RF Amplifier 100 to have better linearity and gain across hot and cold temperatures when compared to prior art.

[0019] FIG. 2 shows a more detailed view of HBT Radio Frequency (RF) Amplifier Module System 90. Mode Control Module 130 is illustrated to include four resistors labeled R1, R2, R3, and R4 and transistors Q1 and Q2. Resistor R1 has a first node connected to receive the signal V_CONTROL and a second node connected to base of transistor Q1. Transistor Q1 has an emitter connected to a ground reference and a collector connected to a first node of resistor R3. Resistor R3 has a second node to provide BIAS SIGNAL 131. Resistor R2 has a first node connected to receive the signal V_CONTROL, and a second node connected to the base of transistor Q2. Transistor Q2 has an emitter connected to a ground reference and a collector connected to a first node of resistor R4. Resistor R4 has a second node to provide signal BIAS SIGNAL 132.

[0020] Current Bias Mirror Module 120 is illustrated to comprise a resistor R5 and a transistor Q3. Resistor R5 has a first node connected to voltage reference V_REF and a second node connected to the second node of R4. Transistor Q3 comprises a collector connected to the second node of resistor R5. The base of transistor Q3 is connected to its own collector. The emitter of transistor Q3 is connected to a ground reference.

[0021] Current Bias Mirror Module 10 is illustrated to comprise resistors R6 and R7, transistors Q4 and Q5, capacitor C1 and inductor L1. Resistor R6 has a first node connected to the V_REF voltage reference and a second node connected to the second node of R3. Resistor R7 has a first node connected to the base of transistor Q4 and a second node coupled to the emitter of transistor Q5. Transistor Q4 has an emitter connected to a ground reference, and a collector connected to the second node of resistor R6. Capacitor C1 has a first node connected to the base of transistor Q4 and a second node connected to the collector of Q4. Inductor L1 has a first node connected to the voltage source V_CC and a second node connected to the collector of transistor Q5. The base of transistor Q5 is connected to the second node of resistor R6. The emitter of transistor Q5 is connected to the second node of resistor R7.

[0022] RF Amplifier Module 100 is illustrated to comprise resistor R8, Capacitor C2, Inductors L2 and L3 and RF Device 01. Inductor L3 has a first node connected to voltage reference V_CC and a second node to provide signal RF_OUT. RF Device 101 is a transistor. The collector of RF Device 101 is connected to the second node of Inductor L3, the emitter of RF Device 01 is connected to a ground reference and the based of RF Device 101 is connected to a first node of R8. Capacitor C2 has a first node connected to the base of RF Device 101, and a second node connected to receive signal RF_IN. Resistor R8 has a second node connected to a first node of inductor L2. Inductor L2 has a second node connected to the second node of R7 and to the base of transistor Q3.

[0023] In operation, control signal V_CONTROL is a biasing signal that determines the state (on/off) of transistors Q1 and Q2. These transistors in turn set the voltage level at the collector of Q4 and the collector of Q3 of Current Bias Mirror Modules 10 and 120, respectively, through the use of voltage divider circuitries R6/R3, which control the Current Bias Mirror Module 110, and R5/R4 which control Current Bias Mirror Module 120. Alternatively, V_CONTROL could actively bias a transistor using an analog signal to control the current directly, or through the voltage divider circuits.

[0024] Current Bias Mirror Module 110 is a current mirror with a base current driver. This circuit provides a linear association between the magnitude of I₁, at the node common to Q5 emitter and R7, at the output of Module 110 and temperature. That is, the magnitude of the current I₁ increases as temperature increases. This increased bias current provided by Module 110 helps overcome the degradation in gain that is normally associated with RF devices at high temperatures. (In operation, the base-emitter junction voltage of HBT transistor Q4 decreases as temperature increases, while resistance values of resistors increase with temperature increases. In Module 110, base-emitter junction of Q4 is in series with R7, base-emitter junction of Q5, and R6. The voltage at the collector of transistor Q4 is dominated by Vbe of Q4 & Q5. When temperature increases, the voltage of second note of R6 decreases. As a result, the rate of voltage decrease at the second node of R6 is faster than the rate of resistance increase of R6, so collector current (dV6/dR6) of Q4 has a positive slope over temperature. I₁ is proportional to collector current of Q4. Thus, I₁ also has positive slope over temperature.

[0025] Current Bias Mirror Module 120 is a single rectifier current mirror. The output current I₂ of this circuit decreases as temperature increases above normal room temperature. The transfer function of I₂ is selected so that, when combined with current I₁ of Current Bias Mirror Module 110, the combination of currents which form I_BIAS exhibit less variation at low temperatures while allowing greater variation at high temperatures. The greater variation at high temperatures compensates for gain degradation. The end result on I_BIAS is that the magnitude of I_BIAS decreases at a slower rate as the temperature transitions below normal room temperature. R5 value is selected so that the voltage at second node connected to R5 and R4 is dominated by R5. The collector current of Q3 decreases when temperature increases so that I₂ also decreases. By adjusting the ratio of R5 and R6, the slope of I₂, and thus I_BIAS, can be adjusted over temperature.

[0026] The currents I₁ and I₂ that are output from the Current Bias Mirror Modules 110 and 120 combine to form the signal called I_BIAS. I_BIAS exhibits characteristics of both of its components. For temperatures above normal room temperature, I_BIAS increases as the temperature increases, providing extra bias current to RF Amplifier Module 100 in order to overcome gain degradation at high temperatures. For temperatures below normal room temperature I_BIAS decreases or remains constant as the temperature decreases in a less pronounced manner. That is, the change in current per change in temperature is greater when the temperature is above normal room temperature than when it is below normal room temperature. The Collector Current 102 which flows through RF Device 101 is dependent upon the magnitude of I_BIAS.

[0027] FIG. 3 illustrates a graph of Icq (I₁) vs. temperature, where Icq (I₁) is that portion of collector current 102, in a quiescent state, that is attributed to the I₁ portion of base current I_BIAS. As ambient temperature increases, the magnitude of quiescent current due to I₁, represented by the graph line 212 in FIG. 3, also increases monotonically, thereby providing line 212 with a slope polarity that is positive. The increasing magnitude of graph line 212 as temperature rises acts to overcome the degradation in gain of the RF Amplifier Module 100 which would otherwise occur at elevated temperatures.

[0028] FIG. 4 illustrates a graph of Icq (I₂) vs. temperature, where Icq (I₂) is that portion of collector current 102, in a quiescent state, that is attributed to the I₂ portion of base current I_BIAS. In a similar but opposite manner as I₁ the magnitude of current I₂, represented by the graph line 210 in FIG. 4, decreases monotonically as ambient temperature increases, thereby providing line 210 with a slope polarity that is negative. This serves to moderate the overall change in I_BIAS at lower temperatures.

[0029] FIG. 5 is a graph illustrating the varying slope of the quiescent bias current 102 over the full range of operating temperatures. The quiescent current Icq is based on the base current I_BIAS, which is the summation of currents I₁ and I₂. As illustrated, the current 102 has a greater increase in magnitude per change in unit temperature at elevated temperatures as compared to lower temperatures. In one embodiment, I_BIAS level and slope is set by adjusting R3, R4, R5, and R6. In one embodiment, as FIG. 5 shows, R5 and R6 are set so that the slope of I_BIAS from T₁ (−20° C.) to T₂(20° C.) is about 0.01 mA/° C. and the slope of I_BIAS from T₃ (40° C.) to T₄(80° C.) is about 0.2 mA/° C. when V_CONTROL is setup for high power state. R3 and R4 are further set so that the slope of I_BIAS from T₁ (−20° C.) to T₂ (20° C.) is about 0.01 mA/° C. and the slope of I_BIAS from T₃(40° C.) to T₄(80° C.) is about 0.15 mA/° C. when V_CONTROL is setup for low power state.

[0030] Component values for a specific embodiment are listed in the table below.

[0031]

	R1 =	5	kohms
	R2 =	5	kohms
	R3 =	2.8	kohms
	R4 =	2.6	kohms
	R5 =	1.55	kohms
	R6 =	400	ohms
	R7 =	750	ohms
	R8 =	12.5	ohms
	Transistor 101 =	5400	square microns
	Q1 =	30	square microns
	Q2 =	30	square microns
	Q3 =	45	square microns
	Q4 =	90	square microns
	Q5 =	120	square microns
	L1 =	5	nH
	L2 =	5	nH
	L3 =	5	nH
	Cl =	7	pF
	C2 =	12	pF

[0032] FIG. 6 illustrates a complete RF Amplifier Module 300 incorporating several submodules, some of which include the bias compensation techniques of the present disclosure. RF Amplifier Module 300 contains an input node to receive RF Input signal at a first node of the Input Matching Module 302. Input Matching Module 302 has a second node which connects to a first node of 1^st Stage Power Amplifier with Bias Circuit 304. 1^st Stage Power Amplifier with Bias Circuit 304 has a second node which connects to a first node of Interstage Matching Module 306. Interstage Matching Module 306 has a second node which connects to a first node of 2^nd Stage PA with Bias Circuit 308. 2^nd Stage Power Amplifier with Bias Circuit 308 has a second node which connects to a first node of Output Matching Module 310. Output Matching Module 310 has a second node which connects to an output node to provide a signal labeled RF Output. Stages 304 and 308 can be implemented specifically based on the systems of FIG. 1.

[0033] In operation FIG. 6 receives a low-level RF signal RF Input and amplifies it. The amplified output is produced at the output node as RF Output. 1^st Stage Power Amplifier with Bias Circuit 304 and 2^nd Stage Power Amplifier with Bias Circuit 308 provide the signal amplification, while the remaining modules 302, 304, and 310 provide low-distortion connections between the amplification stages and the input and output. 1^st Stage PA with Bias Circuit 304 and 2^nd Stage PA with Bias Circuit 308 each contain bias circuitry as described in the present disclosure.

[0034] FIG. 7 illustrates a System 350 incorporating a Power Amplifier 300 as described in FIG. 6 with additional modules to comprise a more complete representation of a system such as a mobile or base station transceiver. System 350 comprises an antenna input connected to a first node of RF Amplifier 300. RF Amplifier 300 has a second node which connects to the output node of buffer 352. RF Amplifier 300 has a third node labeled MODE, which functions in a manner similar to the signal V_CONTROL described in FIGS. 1 and 2. Buffer 352 has an input node which connects to a first node of Transmit Control 354. Transmit Control 354 has a second node, labeled MODE, which is connected to the node on RF Amplifier 300 also identified as MODE. The remaining block of System 350 is labeled System Control 356. System Control 356 has a single output node which connects to the MODE inputs of RF Amplifier Module 300 and Transmit Control 354.

[0035] In operation, System 350 controls transmission of RF signals. System Control 356 provides the MODE signal to Transmit Control 354 and RF Amplifier 300 so that the RF output from module 300 to the antenna is amplified to an appropriate, predetermined level. The Transmit Control 354 controls the input power to Amplifier 300 to maintain a desired output power level of power amplifier 300.

[0036] In the preceding detailed description of the preferred embodiments, reference has been made to the accompanying drawings, which form a part thereof, and in which is shown by way of illustration specific preferred embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical and electrical changes may be made without departing from the spirit or scope of the invention. To avoid detail not necessary to enable those skilled in the art to practice the invention, the description may omit certain information known to those skilled in the art. Furthermore, many other varied embodiments that incorporate the teachings of the invention may be easily constructed by those skilled in the art. Accordingly, the present invention is not intended to be limited to the specific form set forth herein, but on the contrary, it is intended to cover such alternatives, modifications, and equivalents, as can be reasonably included within the spirit and scope of the invention. The preceding detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.