Single wire digital interface

[0001] This application claims the benefit of provisional patent application No. 60/502,499 to Tang, filed Sep. 12, 2003.

[0002] 1. Field of the Invention

[0003] This invention relates to the field of digital interfaces, and particularly to single-wire digital interfaces.

[0004] 2. Description of the Related Art

[0005] A digital interface comprises circuitry designed to receive and buffer digital data, which is then made available to other circuitry. A common “3-wire” digital interface employs three inputs: DATA, CLK, and LOAD. The DATA and CLK inputs receive data and clock signals, respectively. The logic value of a data bit entered into the interface is determined by the voltage on the DATA input when the clock signal either rises or falls. The signal received at the LOAD input determines when a data word comprising a group of just-entered data bits is valid.

[0006] In some applications, a single input or “single-wire” digital interface may be desirable, such as when there are limitations on the number of available I/O pins on an integrated circuit (IC), the number of wires available to connect to an IC, or the number of drivers available to drive the interface. A single-wire interface needs to combine the functions of all three wires of a 3-wire interface. One possible single-wire approach is disclosed in U.S. Pat. No. 5,210,846 to Lee. Here, a single wire is used for bidirectional communication between a single host and either a single or multiple slave devices. The host starts communication by pulling the wire low and leaving it low for a short time t1. To write a 0, the host keeps the wire low after time t1. To write a 1, the host pulls the wire high after time t1. To read, the host releases control of the wire after time t1 and allows the slave to pull it low to send a 0, or leave it floating; if the slave leaves it floating then an external resistor pulls the wire high to send a 1. After a minimum predefined time t2 after time t1, the host can pull the wire high to prepare for the next communication bit. A command word at the start of each transfer defines the transfer type.

[0007] However, Lee's system requires a large number of components, and therefore may require an unacceptably large amount of space on an IC die and consume an excessive amount of current.

[0008] A single-wire digital interface is presented which overcomes the problems noted above, employing a concise implementation which is simple to use and requires only a small die area.

[0009] The present single-wire digital interface is suitable for receiving digital data as a stream of pulses, with ‘1’ and ‘0’ logic levels represented with pulses having first and second pulse widths, respectively. The interface includes an input node for receiving the stream of data pulses. A low-pass filter connected to the input node produces an output that increases at a known rate for the duration of a received pulse, and a comparator produces an output that toggles when the low-pass filter output exceeds a predetermined threshold. A clock generator outputs a clock pulse when a received data pulse terminates; the clock and comparator outputs are provided to a latch. The low-pass filter, comparator and latch are arranged such that a ‘1’ logic level is latched when the pulse width of a received pulse is about equal to the first pulse width, and a ‘0’ logic level is latched when a received pulse has a pulse width about equal to the second pulse width. Thus, if first and second pulse widths are defined as, e.g., >50 μs and <10 μs, respectively, a narrow pulse (<10 μs) applied at the input node results in the latching of a logic ‘0’, and a wide pulse (>50 μs) results in the latching of a logic ‘1’.

[0010] The present digital interface is preferably arranged such that a b-bit sequence of data bits is preceded by a predetermined a-bit “start-of-packet” (SOP) bit pattern, and is followed with a predetermined c-bit “end-of-packet” (EOP) bit pattern. When so arranged, the interface also includes a SOP bit pattern detector arranged to compare a sequence of a consecutive latched bits with the predetermined SOP bit pattern to detect the beginning of a sequence of data bits, and an EOP bit pattern detector arranged to compare a sequence of c consecutive latched bits with the predetermined EOP bit pattern to detect the end of a sequence of data bits.

[0011] Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.

[0017] A diagram illustrating the operation of the present single-wire digital interface is shown in FIG. 1a. The interface is arranged to receive digital data as a stream of pulses, with ‘1’ and ‘0’ logic levels represented with pulses having defined “first” and “second” pulse widths, respectively. The interface comprises an input node 10 which receives the digital data pulses. The received pulses are applied to the input of a low-pass filter 12, which produces an output DLPF that increases at a known rate for the duration of a received pulse. Signal DLPH is applied to an input of a comparator 14, the output of which (DOUT) toggles when DLPH exceeds a predetermined threshold (represented here as an external reference V_ref, though an internal reference might also be used). A clock generator 16, here implemented with an inverter A1, is connected to input node 10 and produces a clock signal CLK having an edge when a received pulse terminates. Clock signal CLK and comparator output signal DOUT are provided to the data and clock inputs, respectively, of a latch 18, represented here as a D-type flip-flop, which is arranged to latch a signal at its ‘D’ input upon the occurrence of a rising edge on its ‘CLK’ input. (Note that latch 18 might alternatively be arranged to latch on a falling edge, and clock generator 16 arranged such that CLK has a falling edge when a received pulse terminates).

[0018] A timing diagram illustrating the operation of the present digital interface is shown in FIG. 1b. Clock signal CLK is the inverse of the received input pulse IN. The output DLPF of low-pass filter 12 increases as long as IN is a logic ‘1’. If the duration of the input pulse is wide enough, DLPF will eventually exceed threshold V_ref, causing DOUT to become a logic ‘1’. Then, when input pulse IN terminates (i.e., toggles from ‘1’ to ‘0’ in this example), a rising edge of CLK is applied to the clock input of latch 18, which latches DOUT. Since DOUT is a ‘1’ when CLK goes high, the latch output (Q) becomes a ‘1’.

[0019] Low-pass filter 12, comparator 14 and latch 18 are arranged such that a logic ‘1’ is latched when a received pulse has a duration about equal to the “first” pulse width, and such that a logic ‘0’ is latched when a received pulse has a duration about equal to the “second” pulse width.

[0020] The “first” and “second” pulse widths are preferably defined as respective ranges. For example, the “first” and “second” pulse widths may be defined as being >50 μs and <10 μs, respectively. Low-pass filter 12 and comparator 14 would then be arranged such that a received pulse having a duration of >50 μs causes DLPF to increase enough to make comparator output DOUT high (such that a logic ‘1’ is latched), and such that a received pulse having a duration of <10 μs results in a DLPF too low to make comparator output DOUT toggle (such that a logic ‘0’ is latched).

[0021] Note that it is not essential that a logic ‘0’ be defined as having the narrower pulse width and that a logic ‘1’ have the wider pulse width; the interface would perform equally well if a logic ‘0’ and a logic ‘1’ were defined as the wider and narrower pulse widths, respectively.

[0022] Digital data is often conveyed by way of “data packets”, each of which typically includes a digital word which is preceded by a predetermined start-of-packet (SOP) bit pattern and is followed by a predetermined end-of-packet (EOP) bit pattern. A practical embodiment of the present invention designed for receiving such data packets is shown in FIG. 2a. Here, the digital interface employs a shift register 30 as the invention's latch element, a SOP detect circuit 32, and an EOP detect circuit 34. The interface operates as before, except that comparator output signal DOUT is clocked into shift register 30 at the termination of every input pulse. In this example, the digital interface is defined such that data is conveyed to input node 10 as digital words b bits in length. Each digital word is preceded with a predetermined SOP bit pattern that is a bits in length, and is followed by a predetermined EOP bit pattern that is c bits in length. Thus, the first a bits of the shift register (Q(0) to Q(a−1)) are provided to SOP detect circuit 32, the next b bits of the shift register (Q(a) to Q(a+b−1)) are the digital word's data bits (D(0) to D(b−1)), and the last c bits of the shift register (Q(a+b) to Q(a+b+c−1)) are provided to EOP detect circuit 34. SOP detect circuit 32 compares the first a bits of shift register 30 with the predefined SOP bit pattern, and sets its output (VALID0) “true” when the bits match. Similarly, EOP detect circuit 34 compares the last c bits of shift register 30 with the predefined EOP bit pattern, and sets its output (VALID1) “true” when the bits match. The digital word's b data bits are recognized as valid only when both VALID0 and VALID1 are true.

[0023] A timing diagram illustrating the operation of the digital interface shown in FIG. 2a is shown in FIG. 2b; the contents of shift register 30 are assumed to be unknown initially. In, this example, a logic ‘0’ is defined as a narrow pulse, and a logic ‘1’ is defined as a wide pulse. A ‘0’ pulse 36 causes DLPF to increase, but when pulse 36 terminates and CLK toggles high, DLPF has not increased to V_ref and thus a logic ‘0’ is loaded into shift register 30. The next input pulse 38 is wide, such that DLPF exceeds V_ref by the time the input pulse terminates and CLK toggles high, thereby loading a logic ‘1’ into shift register 30. The interface performs similarly for the next two input pulses: a logic ‘0’ (40) and a logic ‘1’ (42).

[0024] When an IC containing a shift register is powered up, the contents of the shift register are normally undefined. This can lead to undesirable behavior at power-up, since the shift register contents could be recognized as valid SOP and/or EOP bit patterns. To prevent this, a power-on reset circuit (not shown) is preferably used to reset the shift register at power-up. Such circuits are well known.

[0025] The length b of the digital data words must be carefully considered. If b≧a or b≧c, a digital data word might be falsely detected as a SOP or EOP bit pattern. For example, if the SOP bit pattern is the 6-bit word 100001, and an incoming digital data word is an 8-bit sequence 11100001, the last 6 bits of the data word would be incorrectly detected as a SOP bit pattern when loaded into the shift register. For this reason, it is preferred that the length b of the digital data words provided to the present interface be shorter than either the predefined SOP or EOP bit patterns, to prevent a data word from being falsely detected as an SOP or EOP pattern.

[0026] However, if b≧a or b≧c, the incoming digital words can be broken up into smaller data fields, with one or more dummy bits separating the data fields. The dummy bits should be chosen so that no data pattern can be falsely detected as a SOP or EOP bit pattern. The incoming digital data word in the example above could be, for example, split into two 4-bit words with a single dummy bit separator: 1110 1 0001. When so arranged, no data sequence which includes the dummy ‘1’ bit will trigger a SOP bit pattern.

[0027] A preferred embodiment of a low-pass filter and comparator as might be used with the present invention is shown in FIG. 3. A capacitor C1 is connected between a supply voltage VDD and a node 50. A P-type field-effect transistor (FET) MP1 has its drain-source circuit connected between VDD and node 50, and its gate connected to the interface's input node 52. An N-type FET MN1 has its drain-source circuit connected between node 50 and a current source 54, and its gate connected to input node 52. Node 50 is connected to the gate of a P-type FET MP2, the drain-source circuit of which is connected between VDD and a node 56. Node 56 is also connected to a current source 58. Node 56 is preferably connected to the input of an inverter 60, comprising FETs MP3 and MN2. Another inverter 62, comprising FETs MP4 and MN3, inverts the output of inverter 60 to produce output DOUT.

[0028] The low-pass filter and comparator operate as follows: assume that C1 is initially discharged. When an input pulse IN is received at input node 52 (i.e., goes “high”), MN1 is turned on and allows current from current source 54 to charge C1. This causes the voltage at node 50—and thus the gate of MP2—to decrease. If the duration of the input pulse is sufficiently long, MP2 eventually pulls node 56 high enough to cause the output of inverter 60 to go low, and the output (DOUT) of inverter 62 to go high.

[0029] When an input pulse terminates, MP1 is turned on and discharges C1. This causes the voltage at node 50 to increase and turn MP2 off, causing the output of inverter 60 to go high and the output (DOUT) of inverter 62 to go low.

[0030] Current sources 54 and 58 are preferably implemented with respective transistors MN4 and MN5, which mirror a current I1 provided to a diode-connected transistor MN6 to MN1 and node 56, respectively. Current I1 is preferably constant with temperature and supply voltage.

[0031] A number of circuit elements may be manipulated to provide desired definitions for the interface's ‘1’ and ‘0’ logic levels. For example, the size of C1 and the relative sizes of MN1, MN4, MN5 and MP2 each help determine which input pulse widths will be interpreted as a ‘0’ and which will be interpreted as a ‘1’.

[0032] The circuit preferably includes a transistor MP5, which is turned on and provides current to node 56 when the output of inverter 60 goes low. By so doing, MP5 introduces hysteresis to the voltage at node 56, which helps to prevent spurious signals at output node DOUT. A transistor MP6 is preferably connected in series with MP5, to define the current through MP5.

[0033] To give the circuit some insensitivity to temperature, MP2 can be sized such that its gate-source voltage is roughly constant with temperature when the output of inverter 60 trips. Then, the decrease of MP2's threshold voltage with temperature will be roughly balanced by the V_D,sat increase with temperature for the current supplied by MN5.

[0034] The time period for which input pulse IN is low is unimportant; therefore, the size of MP1 is not critical. C1 must be discharged slowly enough so that the shift register of FIG. 2a can load a valid logic signal when IN goes from high to low, but quickly enough so that the time needed for C1 to discharge is not excessive. As an example, the low-pass filter and comparator of FIG. 3 could be designed such that DOUT is high when IN is high for 22 μs or more. If a logic ‘0’ is defined as a pulse having a duration of <10 μs and a logic ‘1’ defined as a pulse having a duration of >50 μs, this gives a margin of 2.2 in either direction for manufacturing and temperature variations.

[0035] Note that, though the low-pass filter and comparator implementation shown in FIG. 3 is preferred, these circuit functions could be implemented in many different ways.

[0036] While particular embodiments of the invention have been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art. Accordingly, it is intended that the invention be limited only in terms of the appended claims.