Method for scalable architectures in stackable three-dimensional integrated circuits and electronics

[0001] This application claims priority from U.S. Application No. 60/365,807 file Mar. 21, 2002.

[0002] Scalable electronic circuit system composed of stacked layers of the same or similar circuitry.

[0003] Traditionally integrated circuits have been built in a planar fashion, with a single layer of transistors. New developments in manufacturing process technology allow wafers to be vertically stacked and fine-grained vertical conductors formed between circuits on adjacent dies [1, 2, 3, 4, 5, 6, 7]; U.S. Pat. No. 5,627,106; U.S. Pat. No. 5,877,034; U.S. Pat. No. 5,998,808; U.S. Pat. No. 6,185,122; U.S. Pat. No. 6,034,882. Alternatively, layers of transistor circuits may be interconnected with coarser grain conductors such as coaxial lines, (C-4) solder pads, solder mounds, solder bumps, wire bounds, wire interconnects or embedded wiring as in U.S. Patent Application No. 20010033030; U.S. Patent Application No. 20010033509; U.S. Patent Aapplication No. 20010005059; U.S. Pat. No. 5,495,397; U.S. Pat. No. 5,544,017; U.S. Pat. No. 5,778,529.

[0004] It can be useful for each die in a three-dimensional stack of dies to serve a unique purpose. Previous designs implemented in vertically stacked integrated circuit processes used individual mask layouts for each die in the stack [1, 5, 3, 4]; U.S. Pat. No. 5,998,808; U.S. Pat. No. 5,138,437. While extending these circuits to three-dimensions has the effect of reducing global interconnect length, they do little to alleviate the design effort and mask costs associated with each die.

[0005] Recent innovations in three-dimensional memories stack separate layers of memory cells on top of a layer of peripheral circuits [7]; U.S. Pat. No. 6,185,122; U.S. Pat. No. 6,034,882; U.S. Pat. No. 5,487,031; U.S. Pat. No. 5,375,085. However, in these designs, both the memory cell layers and the peripheral circuits must be present to provide random access data storage thus requiring at least two sets of layout masks. Furthermore, the three-dimensional techniques described do not apply to digital logic or digital logic coupled with memories.

[0006] Die stacking has the potential to increase processing power, chip integration, operating speed and data storage density in the same planar area while minimizing global interconnect lengths. Reducing the stacking interval (distance between adjacent dies) in these technologies reduces wire lengths even further, resulting in reduced power consumption and increased logic speed. However, self-heating effects, alignment issues and circuit yield impose limits on the stack height. As designs move to three dimensions, new design techniques are required to maximize performance while minimizing design effort.

• [0007] [1] J. A. Burns et al., “Three-dimensional integrated circuits for low-power, high-bandwidth systems on a chip”, in Proc. IEEE Intl. Solid-State Circuits Conf., pp. 268–269, 453, February 2001.
• [0008] [2] J. A. Burns et al., “3D circuit integration technology for multiproject fabrication”, MIT Lincoln Laboratory, May 2001, DARPA PI Meeting.
• [0009] [3] Y. Akasaka, “Three-dimensional IC trends”, Proc. of the IEEE, vol. 74, n. 12, pp. 1703–1714, December 1986.
• [0010] [4] K. Banerjee, S. J. Souri, P. Kapur and K. C. Saraswat, “3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration”, Proc. of the IEEE, vol. 89, n. 5, pp. 602–633, May 2001.

[0011]

TABLE 1
U.S. Patent Documents
Patent No.	Inventor	Date
20010033509	Ahn, Kie Y. et al.	Oct. 25, 2001
20010033030	Leedy, Glenn J.	Oct. 25, 2001
6,185,122	Johnson, et al.	Feb. 6, 2001
6,034,882	Johnson, et al.	Mar. 7, 2000
20010005059	Koyanagi, Mitsumasa; et al.	Jun. 28, 2001
5,998,808	Matsushita	Dec. 7, 1999
5,138,437	Kumamoto	Aug. 11, 1992
5,375,085	Gnade, et al.	Dec. 20, 1994
5,487,031	Gnade, et al.	Jan. 23, 1996
5,495,397	Davidson, et al.	Feb. 27, 1996
5,877,034	Ramm, et al.	Mar. 2, 1999
5,778,529	Beilin, et al.	Jul. 14, 1998
5,627,106	Hsu	May 6, 1997
5,544,017	Beilin, et al.	Aug. 6, 1996

• [0012] [5] K. Kioi et al., “Design and implementation of a 3D-LSI image sensing processor”, IEEE J. Solid-State Circuits, vol. 27, n. 8, pp. 1130–1140, Aug. 1992.
• [0013] [6] V. W. C. Chan, P. C. H. Chan and M. Chan, “Multiple layers of CMOS integrated circuits using recrysrallized silicon film”, IEEE Electron Device Letters, vol. 22, n. 2, pp. 77–79, February 2001.
• [0014] [7] T. H. Lee, “A vertical leap for microchips”, Scientific American, pp. 52–59, January 2002.

[0015] An object of this invention is to provide a method to reuse the same or similar integrated circuit design for each die in a vertically bonded stack of dies, and have the entire stack of dies function as an interconnected system.

[0016] It is a further object of this invention to provide such a method for arranging vertical conductors and terminators for coupling electrical signals between adjacent dies in the stack.

[0017] It is a further object of this invention to provide such a method for offsetting dies for coupling electrical signals between adjacent dies in the stack.

[0018] In light of the fact that electrical signals can communicate among others: data information, control information, addressing information; it is an object of this invention to provide such a method for communicating externally to, externally from or communicating between, dies in the stack.

[0019] It is a further object of this invention to provide such a method for identifying the top die to define a communications boundary in a vertical stack of like dies.

[0020] It is a further object of this invention to provide such a method for identifying the bottom die to define a communications boundary in a vertical stack of like dies.

[0021] It is a further object of this invention to provide such a method for broadcasting electrical signals to all dies in a vertical stack of like dies.

[0022] It is a further object of this invention to provide such a method for assigning each die, in a vertical stack of like dies, a unique address.

[0023] It is a further object of this invention to provide such a method for addressing one die in a vertical stack like of dies.

[0024] It is a further object of this invention to provide such a method for communicating between storage elements on one die to the next storage elements on an adjacent die.

[0025] The methods described enable scalable integrated circuit systems in which circuits on different die, in a vertical three-dimensional stack of dies, are identical. Only one mask set is required for the entire stack. The system scales directly as the level of stacking is increased while incurring no extra design effort as the stack height increases.

[0038] While the patent invention shall now be described with reference to the preferred embodiments shown in the drawings, it should be understood that the intention is not to limit the invention only to the particular embodiments shown but rather to cover all alterations, modifications and equivalent arrangements possible within the scope of appended claims.

[0039] The preferred embodiments of the present invention are illustrated in FIGS. 1 through 6 of the drawings like numerals being used to refer to like and corresponding parts of the various drawings.

[0040] The present invention involves design techniques or methods that enable scalable integrated circuit systems. A single design and mask set is produced for one die, within a vertical three-dimensional stack of dies, and is reused for all dies with little or no design modification.

[0041] The system scales directly as the levels of stacking is increased while incurring no extra design effort as the stack height increases. Furthermore, the presented methods simplifies design verification since only a single layer of circuits needs to be verified instead of multiple layers.

[0042] Thus, the presented methods increase processing power, chip integration and data storage density in the same planar integrated circuit area with small additional design effort for the single design that is reused for all dies in the stack. These methods will significantly reduce the performance/productivity gap inherent with shrinking device geometries and increased system-on-chip integration.

[0043] Vertical conductors or interdie vias 2 are conductors that allow signals on adjacent dies to be coupled together. In the 3D process developed by MIT Lincoln Laboratory based on their 0.18-μm fully-depleted silicon-on-insulator technology, a compact 2.5-μm vertical conductor 2 connects the top metal (M3) of the current die to bottom metal (M1) of the die above as in FIG. 1. In this technology, design rules do not permit vertical conductors 2 to be directly stacked. In all figures except FIG. 1, the top metal M3 is shown on top and the vertical conductors 2 are shown going upwards. The stacking interval, or distance between adjacent stack levels, is approximately 6.0 μm and stack levels are separated by an insulator. Although the connectors and circuits described pertain directly to this technology, the design techniques presented in this invention can be adapted to any stackable integrated circuit technology that allows vertical interconnections between adjacent dies.

[0044] Stacked die architectures that use a repeated design require bi-directional vertical conductors 2 coupled with terminators 4 for those conductors. This structure, or connector 100, consists of a vertical conductor 2 situated equally between two terminators 4 as shown in FIG. 2. An electrical connection 102 can exist between each terminator 4. The conditional connection 104 between the vertical conductor 2 and terminators 4 on the local die is key for implementing various inter-die communication networks. Consider three stacked dies 110, 112, 114 with the connectors 100 aligned, as shown in FIG. 3. Note how the vertical conductor 2 on the middle die 112 aligns with the left terminator 4 of the connector 100 on the die above it 110. This staggered alignment of alternating dies facilitates the connection of signals from the current die to the die above, the die below or both dies. With one mask set and wafer type the wafers are aligned with the necessary offset, d, and then fused together.

[0045] An extension 200 of the connector structure 100 consists of four terminators 4 placed symmetrically around a vertical conductor 2 with an optional connection 104. This structure 200 can be used as elements in an array 210 as in FIG. 4. This facilitates inter-die routing of standard cells which do not have a preferred or fixed orientation and whose orientation could be changed by the computer-aided-design tools used for placement and routing. Furthermore, I/O cells and I/O pads, which may have to be rotated in 90° increments in the I/O pad ring, can use the connector array 210. This is because the connector array 210 can be rotated in 90° increments and maintain same signal connectivity between two adjacent dies.

[0046] Communication networks implemented among adjacent stacked dies need to identify the boundaries of the stack. Identifying whether a die is at the top or bottom of the stack is important when redirecting the flow of information at that boundary. For example, a connector 100 configured to pass data to a lower die should only do so if that die exists. As shown in FIGS. 5 and 6, extreme detectors 220, 230 uniquely identify the top die 110 and bottom die 114. Furthermore, top self-identifier circuit 220 and bottom die self-identifier circuit 230 remove the need for external die identifier signals. One implementation of a top die identifying circuit 220 consists of a connector 100 where the terminators 4 are grounded and the vertical conductor 2 is coupled to a weak pull-up device 222, as shown in FIG. 5. The node 224 connected to the weak pull-up device 222 is amplified by a buffer 226 to provide the top_id for the current die. A similar circuit 230 is constructed to identify the bottom die. Thus any die below another die will have its identifier signal grounded, while the top die's identifier signal is pulled high. For example, in the die identification circuit group 270 in FIG. 6, die 110 will have its top identifier signal top_id asserted and die 114 will have its bottom identifier signal bottom_id asserted. All other top_id and bottom_id signals will remain unasserted. The static power consumed by this self-identifying scheme is very small (in the order of tens of μW per circuit layer). Other implementations of die identifier circuits exist which do not consume static power. These identifier circuits use custom or standard cell library storage elements instead of resistors. However, they require an external control signal.

[0047] A broadcasting circuit 250 sends a signal to all dies within the stack. Examples of broadcast signals include global clocks, addresses, and control signals. A connector 100 with the vertical conductor 2 coupled 104 to its terminators 4 will implement broadcasting, as in FIGS. 3 and 6. All metal layers in FIG. 3 are assumed to be connected with regular vias. A connector array 210 provides a high-density, low-resistance, high current carrying connection 260 and is suitable for routing fixed-potentials between dies.

[0048] Die addressing is the means by which one die is selected within the stack. The die addressing circuit 280, shown in FIG. 7, uses the top die identifier signal top_id from the top die indentifier circuit 220. The top_id signal is used as the select line for the 2-1 multiplexor 282. Individual dies can be assigned unique addresses relative to the top die or bottom die in the stack. If top_id is asserted, the die_addr signal will be zero. Otherwise, die_addr will be equal to the output of the adder 284 that is present on the die above. A comparator 286 compares the die_addr signal with the addr_in signal that is broadcasted to all dies with the broadcasting circuit 250. FIG. 9 is an example of a stack of three dies where the top die 110 has a die_addr of 0, the middle die 112 has a die_addr of 1, and the bottom die 114 has a die_addr of 2. In general, this describes a method of assigning die addresses where the top die sets its address to zero, increments the address by one and passes it down. The next die, because it is not the top die, will make the passed-in address its own, then increment it and pass it down. A die will respond when the input broadcast address addr_in matches the die address die_addr. Die addresses are precomputed allowing the input address to be immediately driven for faster address resolution.

[0049] Communication between multiple dies can be accomplished by an inter-die network as shown in FIGS. 8 and 10. Redirection of data within these networks relies upon the identification of both the top die 110 and bottom die 114 in the stack, to prevent data from flowing past the stack boundaries. Inter-die networks can be used to implement scan chains 290, inter-processor communication or pipelined computation where information is passed from latches or registers 294 on one level of the stack to latches or registers on another level of the stack. Register 294 is clocked by a global signal clk that is broadcasted using a broadcast circuit 250. FIG. 8 shows a one-bit slice of an inter-die scan chain 290. FIG. 10 is an example of a inter-die scan chain 290 across three dies 110, 112 and 114. On the top die 110, shift_in is coupled to in (an external signal) through a tristate buffer 292. This tristate buffer 292 is controlled by the result (top_id) of the top die identifier circuit 220. The shift_out signal is coupled to the die below 112 through a connector 100. For the die in the middle 112, shift_in is coupled to the die above 110 through the connector 100 and shift_out is coupled to the die below 114 through the connector 100. On the bottom die 114, shift_in is coupled to the die above 112 through the connector 100 and shift_out is coupled by a tristate buffer 296 to a broadcasting circuit 250 that conveys the data to the top of the stack 110 and then to a location external to the stack. The tristate buffer 296 is controlled by the bottom_id signal generated by the bottom die identifier circuit 230.

[0050] Thus three-dimensional methods and circuits for using a single design for all dies in vertical stack of dies has been presented.

[0051] The present invention can be adapted to any stackable integrated circuit technology that allows unrestricted or restricted vertical interconnections between adjacent dies.

[0052] Although the present invention pertains to stacked integrated circuits, the method of aligning and connecting together like wafers can be applied to: stacked multi-chip modules, stacked printed circuit boards, three-dimensional systems packaging, stacked system modules, stacked circuit subassemblies or any other stacked three-dimensional array of electronic circuitry where like electronic circuitry is used for each level of the stack.

[0053] From the foregoing description, it will thus be evident that the present invention provides a design method for scalable three-dimensional integrated circuit systems that use a single circuit design, for all dies, in a vertical stack of dies. As various changes can be made in the above embodiments and operating methods without departing from the spirit or scope of the following claims, it is intended that all matter contained in the above description or shown in the accompanying drawings should be interpreted as illustrative and not in a limiting sense.