Low leakage SRAM scheme

[0001] Cross reference is made to commonly assigned patent application Ser. No. 10/337,069 entitled “BIT-LINE CONTROL FOR LOW POWER IN STANDBY” filed Jan. 6, 2003, the teachings of which are incorporated herein by reference.

[0002] The present invention is generally related to memory devices, and more particularly to memory cells and leakage current thereof in a sleep/data retention mode.

[0003] Circuits comprising or associated with a memory include the memory cell array that stores the data, memory periphery circuits that enable access to the memory cell array for READ and for WRITE, and external circuits. The memory cell array is generally arranged in rows and columns. Word lines that control access to the cells run in the row direction. Bit lines that carry data to and from the cell run in the column direction. The memory periphery circuits comprise row periphery that drives the word lines, column periphery that drives or senses the bit lines; address decode circuitry, and control circuitry. Generally, the row periphery includes means for disabling the word lines to avoid the possibility of data corruption during address transitions. The external circuits may interface with the memory but are not a direct part of the memory function and may comprise general logic and I/O buffers.

[0004] Power is supplied to a chip by a high voltage supply generally designated as Vdd, and a low voltage or reference supply generally designated as Vss. Chip power can be reduced by lowering or disconnecting from Vdd or raising or disconnecting from Vss. Some minimum voltage must be maintained for retention of volatile memory such as SRAM, and some minimum voltage must be maintained for logic operation.

[0005] Minimizing SRAM standby power during sleep/data retention mode is critical to many applications, especially in wireless devices and other portable devices. One prior art approach is to reduce the power supply voltage across the whole chip during sleep/data retention mode, such that the leakage current of the whole chip is reduced while the contents of the SRAM(s) on the chip are still retained. With the continued increment in the transistor leakage and the number of transistors on a chip, however, the total chip current leakage using this approach has become completely unacceptable for wireless applications based on state of art semiconductor technologies.

[0006] Another prior art approach that is being used for on-chip power management during sleep/data retention mode is to segment the voltage supply to allow different voltages to be supplied to a memory array versus to the memory periphery circuitry and other circuitry external to the memory. This is illustrated at 10 in FIG. 1. In the reduced power mode, the power supply voltage is reduced across selected SRAM array(s) whose contents need to be retained. Power is shut down to all other circuits (for example, by switches separating the circuitry from VDD and/or from VSS) except (a) the periphery circuitry associated with the selected SRAM array as required for integrity of the retained memory, (b) selected latches, flip-flops, etc. whose contents also need to be retained, and (c) sleep control circuits. Interface circuits are used when necessary along the boundary between different power domains to ensure that the selected SRAM array(s) and/or latches/flip-flops etc. maintain the data during the sleep/data retention mode and that no excessive through currents exist during the slow power down and up transitions. The periphery circuitry associated with the selected SRAM array(s) is powered to ensure that the word lines and bit lines of the selected SRAM array(s) are at determined voltage levels to prevent the contents of the SRAM cells from being corrupted. This is illustrated at 10 in FIG. 1, where the periphery power supplies are kept at the chip VDD/VSS levels, while either the array VDDA is lowered or the array VSSA is raised, or both methods are used to reduce the voltage across the array. In the power-down mode, the interface between the powered periphery circuitry and the external circuitry must be controlled such that the periphery is in a state that maintains the stored data.

[0007] The problem with the above approach is that the periphery leakage becomes significant as compared with the array leakage that is aggressively reduced by using much reduced voltages across the array and other advanced techniques, such as disclosed in the commonly assigned cross referenced patent application, the teaching of which is incorporated herein by reference. Even with the use of longer gate length or higher nwell bias, etc., the periphery current leakage cannot be reduced to significantly below the level of the array leakage in advanced CMOS technologies, since the direct gate tunneling leakage cannot be reduced.

[0008] Another prior art approach that is being used for on-chip power management during sleep/data retention mode is to shut down power to the memory periphery circuits. This approach requires the addition of circuitry to hold the memory in an unaccessed state while the periphery circuits are not powered. The problem with this approach is that the transition of control of the word lines between the periphery circuit word line drivers to the low power mode circuits is critical, and particularly difficult because of the relatively large word line drivers. Further, the circuitry required to hold each word line off may incur significant leakage.

[0009] Thus, there is a need for a low power mode with retained memory that has reduced power for the array and associated periphery and allows full removal of power to selected circuits, with low risk of corrupting the stored data and with low overhead.

[0010] The present invention achieves technical advantage as a memory device whereby at least a portion of the memory periphery circuitry shares the same power supplies VDDA and/or VSSA of the memory array such that during sleep/data retention mode the voltage across both the portion of the periphery circuitry and the memory array of the selected SRAM block is reduced, while all other circuits can be shut down except the sleep control circuits as well as selected latches, flip-flops, etc. whose contents need to be retained.

[0015] According to embodiments of the present invention, as shown at 20, 30, 40 and 50 in FIGS. 2a–FIG. 2d, respectively, the present invention achieves technical advantages whereby at least a portion of the periphery circuitry 24 shares the same power supplies VDDA and/or VSSA of the memory array 22 such that during sleep/data retention mode the voltage across both the commonly powered portion of the periphery circuitry 24 and array of the selected SRAM block 22 is reduced. Advantageously, all other circuits, including other non-commonly powered portions of the periphery circuitry 24 and external circuitry 26 interfacing with the periphery circuitry, can be shut down (for example, by switches separating the periphery circuitry 24 from VDD and/or from Vss) except the sleep control circuits therein as well as selected latches, flip-flops, etc. whose contents need to be retained. Optionally, the supplies VDD and VSS can be set to zero in standby, and additional supplies can be provided for the external circuitry that must be maintained in standby. Optionally, at least a portion of the other circuits not shut down in standby can be powered by VDDA and/or VSSA. The portion of the periphery circuitry powered by VDDA and/or VSSA remains functional, and the associated standby power is significantly reduced due to the exponential voltage dependence of leakage.

[0016] The voltage dependence of the memory array 22 and periphery circuitry 24 on supply voltage is shown the various embodiments in Table 1.

[0017]

TABLE 1
Leakage in standby with 1 Meg retained memory
	Periphery	Array	Periphery
Array Voltage	Voltage	Leakage	Leakage	Total Leakage
(V)	(V)	(uA/Mb)	(uA/Mb)	(uA/Mb)
1.2	1.2	3285	150	3435
0.4	1.2	419	150	569
0.4	0.4	108	8	116

[0018] The memory array 22 and periphery circuitry 24 leakage current numbers in Table 1 show that in the active mode, the periphery circuitry 24 leakage current is small compared to the memory array 24 leakage current. However, if the memory array 22 voltage is reduced and the periphery circuitry 24 voltage is not reduced, the periphery circuitry 24 leakage is significant relative to the reduced memory array 24 leakage. If the periphery circuitry 24 voltage is also reduced in standby the same as the memory array 24 voltage, the periphery circuitry 24 leakage is reduced significantly. Moreover, matching the periphery circuitry 24 voltage to the memory array 22 voltage in standby significantly reduces the memory array 22 voltage. This is a result of the impact on memory array 22 leakage by the word line voltage and bit line voltages that are set by the periphery circuitry 24 voltage. With the periphery circuitry 24 powered, albeit at a reduced voltage, proper control of WL and BL voltages is maintained and achieves substantially lower leakage current.

[0019] Memory array 22 leakage current in standby can be further reduced by application of back gate bias to raise the transistor threshold voltages. For example, the bias of the n-well in the memory array 22 can be raised to lower the p-channel transistor leakage. If back gate bias is used to lower the memory array 22 leakage, periphery circuitry 24 leakage can also be further reduced by applying the same back gate bias in the periphery circuitry as applied in the memory array.

[0020] Optionally, the row/column repair information is also retained in the redundancy latches in the periphery circuitry 24 powered by VDDA and/or VSSA, thus reducing standby power while avoiding excess time delay and power needed to rescan the repair information from the fuse bank every time the SRAM 22 is returned to active mode. Area overhead and design overhead are very small.

[0021] In the first embodiment shown at 20 in FIG. 2a the full memory periphery circuitry 24 is powered with the memory array 22 supplies, VDDA and/or VSSA. Memory control signals in the periphery circuitry 24 are set to have the memory array 22 unaccessed, such that the powered row periphery circuitry maintains all word lines off. Further, the memory control signals are set to have the column periphery circuitry output drivers in tri-state, so that the powered column periphery circuitry does not drive the external circuitry 26 data lines. For transition into the power down mode, the preferred sequence is to first set the control signals in the periphery circuitry 24, followed by transitioning VDDA and/or VSSA to the power down levels and reducing and/or removing power to selected external circuitry 26. For transition from the power down mode to the active mode, the preferred sequence is to restore VDDA and/or VSSA to the active levels and to restore active power to the selected external circuitry 26, followed by enabling access of the periphery circuitry 24 to the memory array 22. In the power down mode, the bit lines may be held by the periphery circuitry 24 at the standard precharge voltage, generally VDDA. Optionally, in the power down mode, the bit lines may be allowed by the periphery circuitry 24 to float or be held at VSSA.

[0022] In the second embodiment shown at 30 in FIG. 2b, the word line drivers in the portion 25 of periphery circuitry 24 are powered with the array supplies VDDA and/or VSSA, and other periphery circuits outside of portion 25 are powered similar to external circuitry 26. Circuits are provided, such as illustrated at 60 in FIG. 3, to ensure that the input to the word line drivers during the power down mode is such to keep the word lines off. It is efficient to have circuitry with the dual function of selectively enabling word lines in the active mode and ensuring the word lines are off in the power down mode. The word line enable circuitry may be immediately before the word line drivers, as in FIG. 3, or there may be additional circuits, such as a buffering inverters, between the word line enable circuits and the word line drivers. The portion 25 of periphery circuitry 24 may include all circuits from the word line enable circuits to and including the word line drivers. For transition into the reduced power mode, a preferred sequence is first to disable access of the periphery circuitry 24 to the memory array 22, then to set control of the input to the word line drivers for the reduced power mode, and then to transition the voltages of VDDA and/or VSSA to the reduced power values and to reduce or remove power to selected external circuits 26 and to portions other than portion 25 of the periphery circuitry 24. For transition out of the reduced power mode, a preferred sequence is first to restore voltages VDDA and/or VSSA to active mode values and restore power to selected external circuits 26 and to portions other than portions 25 of the periphery circuitry 24, then to remove the reduced power mode control of the input to the word line drivers, and then to enable access to the memory array 22.

[0023] In the third embodiment shown at 40 in FIG. 2c a portion 27 of the external circuitry is supplied with VDDA and/or VSSA.

[0024] In the fourth embodiment shown at 50 in FIG. 2d, the portion 28 of the periphery circuitry from that controlled by the word line enable forward to and including the word line drivers is powered with the array supplies VDDA and/or VSSA. Other periphery circuitry is optionally connected to VDD and VSS or to VDDA and/or VSSA or powered otherwise. For transition into the reduced power mode, the preferred sequence is to disable word line, and then transition VDDA and/or VSSA to the power down levels and selectively reduce or remove power to other circuits, optionally including portions of the periphery circuits. For transition out of the reduced power mode, the preferred sequence is to restore VDDA and/or VSSA to active mode values and restore power to selected external circuits and to portions of the periphery circuitry, then to enable word line.

[0025] In order to ensure the proper operation of the SRAM 22, input/output circuitry 26 is advantageously disposed between the SRAM 22 and the external logic 24 and provides proper power-down/wake-up sequence among the SRAM 22 and external logic 24. The SRAM circuitry 26 enables input, clock input, and/or other control inputs to be disabled/frozen before powering down the SRAM 22 and external logic 24, in order to avoid the loss of data due to a logic glitch. Also, the input/output circuitry 26 between the SRAM 22 and the external logic 24 is gated by the sleep control signal to avoid excess through current during the slow power-down/wake-up transitions.

[0026] As shown in FIG. 4, the control signal SLZ is enabled (=VSS) before powering down the SRAM 22 and the external logic 24, assuming the VDD>=VDDA>VSSA>=VSS and that the external logic 24 is shut down from VSS (float up to VDD).

[0027] Advantageously, there is no danger of data loss due to WL going above array Vss or BL going below WL voltage, since WL is solidly held at row periphery Vss (=array Vss) and BL cannot be lower than column periphery Vss (=array Vss). Further, there is no area overhead and no additional complicated timing control, yet the present invention achieves periphery leakage well below the array leakage level (for relatively large array configuration).

[0028] Though the invention has been described with respect to a specific preferred embodiment, many variations and modifications will become apparent to those skilled in the art upon reading the present application. For example, the array voltages VDDA and/or VSSA may be extended to the periphery circuitry through switches rather than by direct connection. Also, the periphery voltages and array voltages may be from separate supplies but controlled to be substantially equal to each other, different from other on-chip voltages in standby. It should also be recognized that because of voltage drops, there may be some variation among nominally equal voltages. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications.