Integrated circuit bond pad structures and methods of making

[0001] This invention relates to integrated circuit structures and, more particularly, to bond pad structures having circuitry associated therewith, and to methods of making the bond pad structures.

[0002] One of the components of an integrated circuit chip is an array of bond pads for electrically connecting the chip to other components of the system in which it is utilized. The bond pad array typically includes multiple bond pads located around the periphery of the integrated circuit chip. Each bond pad is a conductive area used for bonding a connecting wire, the other end of which is connected to a pin of the integrated circuit package. Interface circuitry, such as electrostatic discharge (ESD) protection circuitry and level shifting circuitry, may be associated with the bond pad.

[0003] In a common approach, bond pads and associated circuitry are positioned adjacent to each other on a chip. A top schematic view of a prior art bond pad structure is shown in FIG. 1. A bond pad 10 is located at the periphery of an integrated circuit chip 12. Bond pad 10 may be a conductive metal having a sufficient area for bonding of a connecting wire. An ESD protection circuit 20 is located adjacent to and electrically connected to bond pad 10. ESD protection circuit 20 may include PMOS ESD/buffer transistors 22 located under a power supply bus 24 and NMOS ESD/buffer transistors 26 located under a power return bus 28. An isolation/control logic block 30, located between PMOS transistors 22 and NMOS transistors 26, includes control logic and provides isolation between PMOS transistors 22 and NMOS transistors 26. As is apparent from FIG. 1, the prior art bond pad 10 and ESD protection circuit 20 occupy significant chip area. The required area is multiplied by the number of I/O pins on the chip.

[0004] Integrated circuits have undergone dramatic increases in function and performance, and dramatic decreases in feature sizes. These trends have impacted the requirements for bond pad structures. As device features have become smaller, the ESD pulse that an integrated circuit is required to withstand has remained the same. Although the density of other circuits has increased, the chip area required to dissipate the ESD pulse has remained nearly constant. In addition, the number of bond pads on a chip has increased with increasing circuit complexity. These trends have resulted in bond pads and ESD protection circuitry occupying a significant proportion of the total chip area on state of the art integrated circuits. It is not uncommon for bond pads and related circuitry to occupy 10–15% of the die area in state of the art integrated circuits.

[0005] Various designs for ESD protection circuits and bond pads have been disclosed in the prior art. See, for example, U.S. Pat. No. 5,514,892, issued May 7, 1996 to Countryman et al.; U.S. Pat. No. 5,517,048, issued May 14, 1996 to Kosaka; U.S. Pat. No. 5,751,065, issued May 12, 1998 to Chittipeddi et al.; U.S. Pat. No. 5,901,022, issued May 4, 1999 to Ker; U.S. Pat. No. 6,157,065, issued Dec. 5, 2000 to Huang et al.; U.S. Pat. No. 6,207,547, issued Mar. 27, 2001 to Chittipeddi et al; U.S. Pat. No. 6,384,486, issued May 7, 2002 to Zuniga et al; and W. R. Anderson et al. “ESD Protection Under Wire Bonding Pads”, EOS/ESD Symposium 99–89, pp. 2A.4.1–2A.4.7.

[0006] It has been proposed in the prior art to fabricate ESD protection circuitry underneath bond pads. One of the difficulties in this approach is that the bond pad is subjected to thermal and mechanical stresses during the bonding process. Such stresses may damage or destroy sensitive layers and circuitry located under the bond pad. In addition, prior art methods of fabricating MOS transistors under bond pads have not addressed the latchup reliability issue. This issue is present when large active devices are placed under bond pads and in close proximity to circuitry of neighboring bond pads and/or neighboring circuitry outside the bond pad. Furthermore, the area underneath bond pads is very limited due to the need to minimize bond pad area.

[0007] None of the prior art bond pad structures has been entirely satisfactory with respect to die area and reliability. Accordingly, there is a need for new and improved bond pad structures and methods of making bond pad structures.

[0008] According to a first aspect of the invention, a bond pad structure for an integrated circuit is provided. The bond pad structure comprises first and second active devices formed in a substrate, first and second buses above the first and second active devices, respectively, a bond pad above the first and second buses, first interconnections between the first and second active devices and the bond pad, and second interconnections between the first and second active devices and the first and second buses, respectively.

[0009] The first active device may comprise at least one PMOS transistor, and the second active device may comprise at least one NMOS transistor. In some embodiments, the first active device comprises a plurality of PMOS transistors and the second active device comprises a plurality of NMOS transistors. The first bus may comprise a power supply bus, and the second bus may comprise a power return bus. The first and second buses may connect to multiple bond pad structures on an integrated circuit chip.

[0010] The bond pad structure may further include a guard band region formed in the substrate. The guard band region may include an N+ guard band for isolation of PMOS transistors and a P+ guard band for isolation of NMOS transistors. The N+ guard band may surround the PMOS transistors and may be connected to the power supply bus. The P+ guard band may surround the NMOS transistors and may be connected to the power return bus.

[0011] The PMOS and NMOS transistors may each include source, drain and gate fingers which are elongated in a direction of current flow in the first and second buses and which are narrow perpendicular to the direction of current flow. The PMOS and NMOS transistors may be configured as electrostatic discharge protection devices.

[0012] Conductive islands may be formed in the first and second buses for connection of the bond pad to the PMOS and NMOS transistors. The conductive islands may be elongated in the direction of current flow in the first and second buses and may be narrow perpendicular to the direction of current flow. Each of the first interconnections may comprise a plurality of individual contacts between the bond pad and the conductive islands and between the conductive island and the active devices. The contacts between different levels may be laterally offset.

[0013] According to a second aspect of the invention, a bond pad structure for an integrated circuit is provided. The bond pad structure comprises an active device formed in a substrate, a power bus above the active device, a bond pad above the power bus, a first interconnection between the active device and the bond pad, and a second interconnection between the active device and the power bus.

[0014] The active device may comprise one or more electrostatic discharge protection devices. In some embodiments, the active device comprises at least one MOS transistor. In other embodiments, the active device comprises at least one silicon controlled rectifier.

[0015] According to a third aspect of the invention, a method is provided for fabricating a bond pad structure for an integrated circuit. The method comprises forming first and second active devices in a substrate, forming first and second buses above the first and second active devices, respectively, forming a bond pad above the first and second buses, interconnecting the first and second active devices and the bond pad, and interconnecting the first and second active devices and the first and second buses, respectively.

[0016] According to a fourth aspect of the invention, a method is provided for fabricating a bond pad structure for an integrated circuit. The method comprises forming an active device in a substrate, forming a bus above the active device, forming a bond pad above the bus, interconnecting a first terminal of the active device and the bond pad, and interconnecting a second terminal of the active device and the bus.

[0017] According to a fifth aspect of the invention, a bond pad structure is provided for an integrated circuit. The bond pad structure comprises first and second circuit areas formed in a substrate, a guard band region formed in the substrate, first and second buses above the first and second circuit areas, respectively, a bond pad above the first and second buses, at least one first interconnection between circuitry in one or both of the first and second circuit areas and the bond pad, and at least one second interconnection between circuitry in one or both of the first and second circuit areas and the first and second buses.

[0018] In some embodiments, the bond pad structure further comprises at least one PMOS transistor in the first circuit area and at least one NMOS transistor in the second circuit area. In other embodiments, the bond pad structure further comprises at least one silicon controlled rectifier in the first circuit area, and the second circuit area serves as an isolation area. A guard band region may surround the silicon controlled rectifier. The silicon controlled rectifier may be utilized to protect either the input or the output of a circuit.

[0032] A top schematic view of a bond pad structure 40 in accordance with a first embodiment of the invention is shown in FIG. 2. The bond pad structure 40 is one of an array of bond pad structures on an integrated circuit chip 56. Each of the bond pad structures includes a bond pad and associated circuitry. Bond pads 50, 52 and 54 are positioned side-by-side at the periphery of integrated circuit chip 56. Integrated circuit chip 56 may include any desired number of bond pads. The bond pads are typically located at or near the periphery of integrated circuit chip 56, but may have other locations in particular applications. Each of bond pads 50, 52, and 54 is associated with a bond pad structure. In FIG. 2, bond pad structure 40 is shown by way of example. Other bond pad structures in the bond pad array may have the same or different configurations. In one embodiment, multiple bond pad structures in the bond pad array have the same configuration. As used herein, the phrase “bond pad structure” includes the bond pad itself and circuitry and interconnections associated with the bond pad.

[0033] The bond pad structure 40 includes bond pad 52, a power supply bus 60 and a power return bus 62. Power supply bus 60 and power return bus 62 pass under each of the bond pads 50, 52 and 54. The bond pad structure 40 further includes a first circuit area 70 under power supply bus 60 and a second circuit area 72 under power return bus 62. One or both of circuit areas 70 and 72 may include circuitry, such as ESD protection devices or circuitry which can function as I/O circuitry, as ESD protection circuitry, or both. In the embodiment of FIG. 2, first circuit area 70 includes PMOS ESD/buffer transistors, and second circuit area 72 includes NMOS ESD/buffer transistors. The circuitry in first circuit area 70 may be connected to power supply bus 60 and bond pad 52 as described below. The circuitry in second circuit area 72 may be connected to power return bus 62 and bond pad 52 as described below. The bond pad structure 40 further includes a guard band region 80 as described below. As further shown in FIG. 2, control logic 84 is associated with each bond pad structure. In the embodiment of FIG. 2, control logic 84 is not located under bond pad 52.

[0034] In the embodiment of FIG. 2, the PMOS transistors are located in circuit area 70 adjacent to the outer edge of integrated circuit chip 56, and the NMOS transistors are located in circuit area 72 adjacent to control logic 84. In other embodiments, the locations of the PMOS transistors and the NMOS transistors may be reversed so that the PMOS transistors are located in circuit area 72 and the NMOS transistors are located in circuit area 70. If the locations of the PMOS and NMOS transistors are reversed, the locations of the power supply bus 60 and the power return bus 62 are reversed, and the locations of the guard bands in guard band region 80 are reversed. Furthermore, all interconnected bond pad structures are reversed in the same way.

[0035] Each of bond pads 50, 52, 54 provides a conductive surface for bonding of a connection element, such as a connection wire or a conductive bump material used for connection to another integrated circuit chip or a printed circuit board. In one embodiment, bond pad 52 has dimensions of 70 μm (micrometers) on a side. It will be understood that the bond pads may have larger or smaller dimensions depending on the application and the bonding process being used.

[0036] The bond pad structure 40 is shown in greater detail in FIG. 3. In the embodiment of FIG. 3, first circuit area 70 includes a plurality of PMOS transistors 100, and second circuit area 72 includes a plurality of NMOS transistors 102. As indicated in FIG. 3, PMOS transistors 100 and NMOS transistors 102 are elongated in the direction of current flow in power supply bus 60 and power return bus 62, in order to provide relatively large ESD protection transistors while limiting the negative impact on the current-carrying capacity of power supply bus 60 and power return bus 62, as described below. That is, the bond pad structure shown and described herein provides both large ESD protection transistors and wide power supply and power return buses for effective ESD protection. In the embodiment of FIG. 3, bond pad structure 40 includes twelve PMOS transistors and twelve NMOS transistors. As further shown in FIG. 3, each of the circuit areas may be divided into subareas, each containing a group of transistors. Thus, first circuit area 70 is divided into circuit subareas 70a and 70b, each having six PMOS transistors 100. Similarly, second circuit area 72 is divided into circuit subareas 72a and 72b, each having six NMOS transistors 102. It will be understood that a greater or lesser number of transistors may be provided in each of the circuit areas.

[0037] The guard band region 80 provides isolation of PMOS transistors 100 and NMOS transistors 102. Guard band region 80 may include an N+ guard band 104 for isolation of PMOS transistors 100 and a P+ guard band 106 for isolation of NMOS transistors 102. The N+ guard band 104 may be fabricated in an N-well. Each of the guard bands 104 and 106 is connected by a metal interconnect layer to a reference voltage. The N+ guard band 104 is connected to power supply bus 60, and the P+ guard band 106 is connected to power return bus 62. The N+ guard band 104 may surround circuit area 70, and the guard band 106 may surround circuit area 72. This configuration isolates the PMOS and NMOS transistors from each other and also isolates the PMOS and NMOS transistors from circuitry under neighboring bond pads and from circuitry outside the bond pad. The guard bands 104 and 106 may be continuous through all of the bond pad structures.

[0038] An enlarged top view of circuit subarea 70a of bond pad structure 40 is shown in FIG. 4. As shown, power supply bus 60 is provided with conductive islands 110, 112 and 114 for interconnecting bond pad 52 to the underlying transistors, as described below. Gates 120, 122, 124, 126, 128 and 130 of PMOS transistors 100 are shown in FIG. 4. As shown in FIG. 5 and described below, the gates are located below power supply bus 60 in the bond pad structure. Gates 120, 122, 124, 126, 128 and 130 are elongated in a direction 142 of current flow in power supply bus 60 and are narrow in a direction perpendicular to direction 142. In this embodiment, each conductive island connects to two underlying transistors. Accordingly, conductive island 110 is located between gates 120 and 122; conductive island 112 is located between gates 124 and 126; and conductive island 114 is located between gates 128 and 130.

[0039] Conductive islands 110, 112 and 114 are part of the same metal layer as power supply bus 60. In embodiments where power supply bus 60 includes two or more metal layers, vertically-aligned conductive islands are formed in each of the metal layers, as shown in FIGS. 7A and 7B and described below. Furthermore, conductive islands are formed in any additional metal layers between bond pad 52 and the underlying transistors.

[0040] Each conductive island 110, 112 and 114 has the form of an elongated metal strip that is electrically isolated from power supply bus 60 by a gap 140, which may be filled with an insulating material. It will be understood that power supply bus 60 and islands 110, 112 and 114 are supported by an underlying insulating layer. Conductive islands 110, 112 and 114 are configured to limit the negative impact on the current-carrying capacity of power supply bus 60, while allowing a relatively large current-carrying capacity between the bond pad 52 and the underlying transistors. In particular, each of the conductive islands is elongated in direction 142 of current flow in power supply bus 60 and is relatively narrow in a direction perpendicular to direction 142.

[0041] In one example, power supply bus 60 may have a width of 25 micrometers. Each of the conductive islands 110, 112 and 114 may have a length of approximately 20 micrometers and a width of about 1.1 to 1.5 micrometers, depending on the process technology. It will be understood that these values are given by way of example only and are not limiting as to the scope of the invention.

[0042] The direction of current flow through the conductive islands is not in the direction of elongation, but rather downward or upward through the layers of the bond pad structure, depending on the direction of ESD current flow. Since the current flow is not along the conductive island width or length direction, the conductive island widths can be very small.

[0043] A cross-sectional diagram of a portion of circuit subarea 70a of bond pad structure 40 is shown in FIG. 5. As indicated, bond pad structure 40 has a multilayer configuration. In FIG. 5, transistor structures, metal layers and interconnects are shown. It will be understood that metal layers are separated from transistors and from other metal layers by dielectric layers. The dielectric layers may utilize materials and layer thicknesses that are known to those skilled in the art of integrated circuit fabrication. The dielectric layers may have thicknesses in a range of about 0.3 to 1.0 micrometer, but are not limited to this range. The dielectric material may be selected to withstand the mechanical stress of the bonding process.

[0044] As shown in FIG. 5, PMOS transistors 100 may be fabricated in a silicon substrate 150 using a conventional CMOS process. Silicon substrate 150 may be an undoped silicon wafer or a doped well. If the source/drains of the transistors are P-type, substrate 150 is an N-well. If the source/drains of the transistors are N-type, substrate 150 is a P-well or an undoped wafer. An N-type transistor may also be fabricated in an isolated P-well region within a deep N-well tub. A drain region 152 serves transistors 100c and 100d. A source region 154 serves transistors 100b and 100c, and a source region 156 serves transistors 100d and 100e. For PMOS transistors 100, the source/drain regions are P-type. For NMOS transistors 102, the source/drain regions are N-type. Gates 122, 124, 126 and 128 are fabricated as a gate stack and include at least an insulating layer and a gate electrode, such as polysilicon, as known in the art. Additional details regarding fabrication of PMOS and NMOS transistors are known to those skilled in the art.

[0045] In the embodiment of FIGS. 2–8, the source and drain regions and the gates of the transistors are elongated in the direction of current flow in buses 60 and 62 and are narrow perpendicular to the direction of current flow. The elongated sources, drains and gates of the transistors may be referred to as “fingers” of the transistors. In some embodiments, the transistors in each circuit area may be connected independently. In other embodiments, two or more sets of fingers may be connected together to form a larger transistor having multiple fingers. In a multi-finger transistor, the source fingers are connected, the drain fingers are connected, and the gate fingers are connected.

[0046] Bond pad structure 40 further includes two or more patterned metal layers above circuit areas 70 and 72. The number of metal layers depends on the design of the integrated circuit. In the embodiment of FIG. 5, bond pad 52 includes a first pad layer 160, or top layer of the bond pad structure, and a second pad layer 162 below first pad layer 160. Pad layers 160 and 162 are metal and are interconnected by conductive vias 164. The term “vias” refers to vertical connections or contacts between different levels of the multilayer structure. The two-layer structure enhances the mechanical integrity and current-carrying capability of bond pad 52. It will be understood that bond pad 52 may be a single metal layer or two or more metal layers interconnected by vias. When a single metal layer is utilized, the single layer may be relatively thick and may be connected directly to the conductive islands. A single bond pad layer may have a thickness of 3 micrometers or greater, for example, and may be utilized in place of pad layers 160 and 162.

[0047] Power supply bus 60 may include a first bus layer 170 and a second bus layer 172 interconnected by conductive vias 174. In the embodiment of FIG. 5, first bus layer 170 is continuous through each of the bond pad structures, except for the conductive islands, such as conductive islands 110, 112 and 114, as shown in FIG. 4 and described above. Second bus layer 172 is patterned in each of the bond pad structures, as shown in FIG. 8 and described below. Power supply bus 60 may further include an optional third bus layer 176 interconnected to first bus layer 170 by conductive vias 178. Bus layers 170, 172 and 176 are metal. The number of metal layers depends, at least in part, on the desired current-carrying capacity of power supply bus 60.

[0048] Second bus layer 172 is patterned to form a first source contact 180 interconnected to source region 154 by conductive vias 182 and a second source contact 184 interconnected to source region 156 by conductive vias 186. The gates 120, 122, 124, 126, 128 and 130 of the PMOS transistors 100 may be interconnected to each other and to other circuitry, such as control logic 84 by an additional metal layer (not shown) between second bus layer 172 and transistors 100.

[0049] As further shown in FIG. 5, first bus layer 170 includes conductive island 112, second bus layer 172 includes a conductive island 190 and optional third bus layer 176, if present, includes a conductive island 192. Conductive islands 112, 190 and 192 are vertically aligned and are interconnected by conductive vias to provide an electrical connection between bond pad 52 and drain region 152 of each of the PMOS transistors.

[0050] Details of the interconnection between bond pad 52 and drain region 152 of the PMOS transistors are shown in FIGS. 6, 7A and 7B. Conductive island 112 is shown in FIG. 6 with conductive vias at different levels superimposed. In FIG. 6, square symbols represent conductive vias 200 between island 192 and island 112; diamond symbols represent conductive vias 202 between island 112 and island 190; and circle symbols represent conductive vias 204 between island 190 and drain region 152. FIG. 7A is a cross-section of conductive island 112 taken along the line 7A—7A of FIG. 6; and FIG. 7B is a cross-section of conductive island 112 taken along the line 7B—7B of FIG. 6. As shown in FIG. 6, conductive vias 200 (represented by square symbols) and conductive vias 202 (represented by diamond symbols) alternate along opposing edges of conductive island 112. Conductive vias 204 (represented by circle symbols) are arranged in a line along the center of conductive island 112 between vias 200 and 202. As best shown in FIGS. 7A and 7B, conductive vias 200 between islands 192 and 112 are laterally offset with respect to conductive vias 202 between islands 112 and 190. That is, vias between adjacent pairs of conductive islands are laterally offset. The lateral offset of conductive vias between adjacent pairs of conductive islands is apparent from the arrangement of vias shown in FIGS. 6, 7A and 7B. This arrangement avoids direct transfer of mechanical stress, applied during bonding, from bond pad 52 to underlying structures and thus reduces the risk of damage to underlying structures during the bonding process.

[0051] A top schematic view of circuit subarea 70a, which illustrates source contacts 180 and 184, is shown in FIG. 8. Subarea 70a also includes a source contact 220 adjacent to island 110 and a source contact 224 adjacent to island 114. As shown in FIGS. 5 and 8, source contacts 180, 184, 220 and 224 have relatively large areas and extend over the respective transistor gates to provide low resistance contacts to source regions 154, 156, etc. Source contacts 180, 184, 220 and 224 are formed in second bus layer 172 (FIG. 5). The large area source contacts at least partially restore to the power supply and power return buses the current-carry capability which is lost by fabricating the conductive islands and associated metal openings.

[0052] Circuit subarea 70a has been described above in connection FIGS. 4–8. It will be understood that circuit subarea 70b may have the same configuration. Furthermore, circuit subareas 72a and 72b may have a similar configuration, except that subareas 72a and 72b may include NMOS transistors rather than PMOS transistors. Furthermore, power return bus 62 passes through circuit subareas 72a and 72b. However, the geometry of the NMOS transistors and the configuration of the metal layers and interconnects may be as described above in connection with circuit subarea 70a, with appropriate changes of conductivity type.

[0053] A top schematic view of a second prior art bond pad structure is shown in FIG. 9. A bond pad 300 is located at the periphery of an integrated circuit chip 302. An ESD protection circuit 310 is located adjacent to and electrically connected to bond pad 300. ESD protection circuit 310 includes at least one SCR (silicon controlled rectifier) 320 surrounded by a guard band region 322. The SCR 320 is connected to input gate transistors 330. In prior art configurations, SCR 320 was used only for protection of inputs to integrated circuit chip 302. As in the prior art configuration of FIG. 1, bond pad 300 and ESD protection circuit 310 occupy significant chip area. The required area is multiplied by the number of I/O pins on the chip.

[0054] A top schematic view of a bond pad structure 340 in accordance with a second embodiment of the invention is shown in FIG. 10. The bond pad structure 340 is one of an array of bond pad structures on an integrated circuit chip 342. The bond pad structure 340 includes a bond pad 350, a power supply bus 360 and a power return bus 362. Power supply bus 360 and power return 362 pass under bond pad 350 and may be parallel. The bond pad structure further includes a first circuit area 370 under power supply bus 360 and a second circuit area 372 under power return bus 362. In the embodiment of FIG. 10, first circuit area 370 includes at least one SCR 380, and second circuit area 372 does not contain circuitry. Instead, second circuit area 372 serves as an isolation area. The SCR 380 may be connected to power supply bus 360 and bond pad 350 using the interconnection techniques described above in connection with FIGS. 2–8.

[0055] The bond pad structure 340 further includes a guard band region 382 located between first circuit area 370 and second circuit area 372. The guard band region 382 is provided with a branch 384 so that SCR 380 is fully surrounded by guard band region 382.

[0056] SCR 380 is connected to and provides ESD protection for a circuit 390. Circuit 390 may include input circuitry or output buffer transistors, depending on whether bond pad 350 is functioning as an input or an output. The embodiment of FIG. 10 provides a high degree of isolation between SCR 380 and circuit 390. SCR 380 is spaced from circuit 390 by first circuit area 370. Furthermore guard band region 382 completely surrounds SCR 380 and provides isolation. As a result, the guard band structure 340 can be used for ESD protection of both input circuitry and output buffer transistors.

[0057] A partial cross-sectional view of a bond pad structure in accordance with a third embodiment of the invention is shown in FIG. 11. Like elements FIG. 2-11 have the same reference numerals. In the embodiment of FIG. 11, a bond pad structure 400 includes a bond pad 410 having a first pad layer 420 spaced from a second pad layer 422. A passivation layer 430 defines a passivation opening 432 for bonding of a wire or other connection element. First pad layer 420 is connected to second pad layer 422 through vias 440 and 442, and an optional conductive island 450. Conductive island 450 may be utilized in an embodiment where a metal layer 452 is present between first pad layer 420 and second pad layer 422. It will be understood that, except for conductive island 450, metal layer 452 is not electrically connected to first pad layer 420 or second pad layer 422. The connection between pad layers 420 and 422, including vias 440 and 442 and conductive island 450, may be located outside passivation opening 432 and under passivation layer 430. The configuration of FIG. 11 may provide reduced capacitance for enhanced operation at high frequencies, including RF frequencies.

[0058] According to another feature, it may be noted that source contacts 180 and 184 are narrower in the embodiment of FIG. 11 than in the embodiment of FIG. 5 and do not extend over gates 124 and 126. Nonetheless, source contacts 180 and 184 are relatively wide to enhance the current-carrying capability between sources 154 and 156 and power supply bus 60. In other respects, the bond pad structure may be fabricated as described above in connection with FIGS. 2–8.

[0059] Having thus described the inventive concepts and a number of exemplary embodiments, it will be apparent to those skilled in the art that the invention may be implemented in various ways, and that modifications and improvements will readily occur to such persons. Thus, the examples given are not intended to be limiting, and are provided by way of example only. The invention is limited only as required by the following claims and equivalents thereto.