Method and apparatus for generating narrow pulse width monocycles

[0001] This application benefits from the priority of a provisional application Ser. No. 60/316,285, filed Sep. 4, 2001 and entitled “Monocycle Generator,” the disclosure of which is incorporated herein.

[0002] The present invention relates to circuits for use in an ultra-wideband communication system.

[0003] Monocycle pulses have applications in a variety of engineering disciplines. They have been proposed for use in ultra-wideband communications applications because they spread signal energy over frequency and time and may be modulated to carry information. In synchronous oscillators, monocycles may simplify designs of such oscillators and lower the frequency of driving clocks thereto. Monocycles are also used in radar applications to measure environmental impulse reflections.

[0004] Almost uniformly, it is desirable to generate monocycles having the shortest duration possible. To extend useful battery life when deployed in mobile hardware, it is desirable to generate the monocycles with low power consumption. Additionally, it is desirable to generate monocycles using circuitry that operates uniformly even when fabricated into integrated circuits from variable manufacturing processes and when operated over a variety of temperatures. The inventors are unaware of any circuits or systems that adequately harmonize these design interests.

[0005] Accordingly, with the current invention, monocycle generating circuits and systems are provided that generate monocycles having short widths, the circuits and systems consuming low power, using a reduced number of components and operating at high speed.

[0022] Embodiments of the present invention provide a monocycle forming network for ultra-wideband transmission. The network may include a monocycle generator, up and down pulse generators, data modulators and clock generation and timing circuits.

[0023] FIGS. 1A and 1B are circuit diagrams of a monocycle generators 100A and 100B according to embodiments of the present invention. The monocycle generators 100A arid 100B may each include a pair of input terminals 110, 120 for respective “down pulse” signals and “up pulse” signals. The circuits 100A and 100B may also include an output terminal 130 for the monocycle pulse to be generated by the circuits 100a and 100b.

[0024] The monocycle generators 100A and 100B may include a first transistor 140 coupling the output terminal 130 to a first voltage source (V_dd) and a second transistor 150 coupling the output terminal 130 to a second voltage source (ground). The first transistor 140 may be controlled by the down pulse signal, becoming conductive when the down pulse signal is active (low). The second transistor 150 may be controlled by the up pulse signal, becoming conductive when the up pulse signal is active (high). In this regard, the monocycle generators 100A and 100B cause the output terminal to charge toward V_dd under the influence of the down pulse signal and to discharge toward ground under the influence of the up pulse signal.

[0025] The monocycle generators 100A and 100B may each include a voltage divider formed by a pair of resistors 160, 170. The resistors 160, 170 may couple the output terminal 130 to V_dd and to ground respectively. During periods where the first and second transistors 140, 150 are non-conductive, a potential drop across the resistors 160, 170 may place the output terminal 130 at an intermediate potential (say, ½ V_dd, when the resistors have the same impedance).

[0026] FIG. 2 is a simplified diagram illustrating operation of the monoeycle generator 100A, 100B of FIGS. 1A and 1B under the influence of idealized up pulse and down pulse signals. FIG. 2(a) illustrates a down pulse applied to the monocycle generator 100A, 100B at time T₁ and removed at time T₂. FIG. 2(b) illustrates an up pulse applied to the circuit at time T₂ and removed at time T₃. FIG. 2(c) illustrates response of the output terminal 130 under inputs illustrated in FIGS. 2(a) and (b).

[0027] Prior to activation of the down pulse at time T₁, the potential at the output terminal 130 is determined by the voltage divider formed by the resistors 160, 170. It may be maintained at ½ V_dd. When the down pulse is applied at time T₁, the transistor 140 becomes conductive, driving the potential of the output terminal 130 toward V_dd. The potential of the output terminal 130 is maintained at V_dd until time T₂ when the down pulse concludes and the up pulse begins. At time T₂, the first transistor 140 becomes non-conductive but the second transistor 150 becomes conductive. The output terminal 130 may discharge toward ground and be maintained at ground until the up pulse concludes at time T₃. Thereafter, both transistors 140, 150 become non-conductive and the output terminal 130 may return to the intermediate potential under influence of the voltage divider 160, 170.

[0028] The foregoing discussion of FIGS. 2(a)–(c) present an idealized circuit response that ignores switching times of the transistors 140,150 and other sources of impedance. While such diagrams are useful to explain the circuit response to the reader, these sources of impedance may cause the circuit response to deviate from the response illustrated in FIG. 2(c).

[0029] Simulations suggest that, under real conditions, the circuit's response may correspond more closely to the waveform illustrated in FIG. 2(d).

[0030] Additionally, so as to minimize contention between the first and second transistors, a slight delay may be provided between the termination of a down pulse and the onset of a low pulse. FIGS. 2(f) and (g), therefore, illustrate a down pulse extending from time T₅ to T₆ and an up pulse beginning some time T₇ thereafter and concluding at time T₈. The timing relationships shown in FIGS. 2(f) and (g) may be employed in an embodiment of the present invention.

[0031] As shown in FIG. 1B, the monocycle generator 100B includes third and fourth transistors 180, 190 to regulate current across the voltage divider 160, 170. When a transistor 140, 150 is rendered conductive, driving the output terminal 130 to either V_dd or ground, current flow trough the voltage divider 160, 170 can reduce the speed at which the output terminal 130 charges or discharges. Accordingly, third and fourth transistors 180, 190 disable current flow through respective resistors 160, 170 in response to the up pulse and down pulse, each becoming non-conductive when its respective input becomes active.

[0032] In this embodiment, the third transistor 180 couples the resistor 160 to V_dd. An input of the third transistor 180 may be coupled to terminal 120 and rendered non-conductive when the up pulse becomes active. Similarly, the fourth transistor 190 couples the resistor 170 to ground.

[0033] An input of the fourth transistor 190 is coupled to terminal 110 and rendered non-conductive when the down pulse becomes active. In this regard, the third and fourth transistors 180, 190 prevent current from flowing through their respective resistors when they would interfere otherwise with the switching of the output terminal 130. By reducing current flow through the voltage divider 160, 170, the third and fourth transistors 180, 190 also conserve power consumed by the circuit 100.

[0034] The monocycle obtained from the monocycle generator 100A, 100B may be output to an antenna (not shown) or other transmission structure. According to an embodiment, the monocycle may be modulated to carry information. To carry data, the timing of the up pulse and the down pulse may be modulated. In FIG. 2, the down pulse is illustrated as preceding the up pulse. This sequence may represent the first binary value (say, 1). Alternatively, the up pulse could precede the down pulse to represent a second binary value (say, −1); In this case, the circuit response may invert the monocycle of FIG. 2(d) (Shown in FIG. 2(e)). By modulating these sequences, monocycles can be made to carry information. For example, the orientation of a monocycle many be assigned to a binary value such as 1 or 0 or, alternatively, the time between successive monocycles may be used to carry information. A variety of different signaling formats become available.

[0035] The monocycle generator 100A of FIG. 1A or the monocycle 100B of FIG. 1B may be fabricated within an integrated circuit according to any number of conventional processes, including CMOS (complimentary metal oxide semiconductor) process and BJT (bipolar junction transistor) processes with complementary PNP. In a CMOS embodiment, the first and fourth transistors 140, 190 may be provided as PMOS transistors to become conductive when the signals input thereto are low. The second and third transistors 150, 180 may be provided as NMOS transistors to become conductive when the signals input thereto are high.

[0036] FIG. 3 illustrates a down pulse generator 300 according to an embodiment of the present invention. In this embodiment, the down pulse generator 300 may include an inverter 310 and a NAND gate 320. Inputs of the inverter 310 and the NAND gate 320 are coupled to a common clock source CLK. A second input of the NAND gate 320 is coupled to an output of the inverter 310. The NAND gate 320 may be constructed according to any of the known architectures for such gates.

[0037] As is known, an inverter 310 not only inverts an input signal but also imposes an incremental delay to the propagation of logical transitions in the input signal. Thus, the signal input to the NAND gate 320 is labeled as “{overscore (CLK_d)}” to illustrate differences in value and the relative skew between the two signals input to the NAND gate 320. In response to these two signals, the NAND gate 320 generates an output pulse that is logically high (V_dd) at all times except at the falling edge of the CLK signal. A transition in the CLK signal from low to high may cause a corresponding transition in the output of the NAND gate 320 (to ground). This down pulse may have a duration that is defined by the delay induced by elements of the inverter 310 and the NAND gate 320.

[0038] In an embodiment, the single inverter 310 actually may be provided as a cascaded chain of inverters (multiple inverters 310.1–310.N are shown in phantom), possibly including transmission gates (not shown). Thus, the delay of the {overscore (CLK_d)} signal with respect to the source signal CLK may be tuned to fit individual applications. As described above, this delay may determine the width of the down pulse generated therefrom.

[0039] The NAND gate 320 may be provisioned according to any of the traditional circuit architectures for such gates. Many of these known architectures have charge paths and discharge paths (paths from the output terminal 330 to either V_dd or ground) that traverse multiple switching transistors. The multiple switching transistors can determine a maximum rate at which the output terminal 130 can charge toward V_dd or discharge toward ground. Longer switching times of the NAND gate 320 cause down pulses of longer duration which, in turn, can cause monocycles output by the pulse generator 100 (FIG. 1) to have a longer duration. In many applications, it is desirable to minimize the duration of the monocycle, often measured by the peak-to-peak transition time (shown as t_pp in FIG. 2), and therefore a down pulse generator having a faster switching time may be used.

[0040] FIG. 4 is a block diagram of a down pulse generator 400 according to another embodiment of the present invention. The embodiment of FIG. 4 may include four transistors 410–440 and a transmission gate 450. First and second transistors 410, 420 may couple an output terminal 460 to V_dd. The first transistor may be controlled by a delayed inverted clock signal {overscore (CLK_d)}. The second transistor 420 may be controlled by a clock signal CLK. A third transistor 430 may couple the output terminal 460 to ground. Thus, charging paths (from the output terminal 460 to V_dd) and discharging paths (from the output terminal 460 to ground) traverse at most one switching transistor in this embodiment.

[0041] The fourth transistor 440 may bridge between ground and an input of the third transistor 430 (node 470). The fourth transistor 440 may be controlled by a delayed clock signal CLK_d. The gate 450 may bridge the input 470 of the third transistor 430 to a source of the clock signal CLK. The gate 450 itself may be controlled by the delayed inverted clock signal {overscore (CLK_d)}.

[0042] The down pulse generator 400 of FIG. 4 may be advantageous for use in certain applications because charging paths (from the output terminal 460 to V_dd) and discharging paths (from the output terminal 460 to ground) traverse at most one switching transistor 410, 420 or 430. Two transistors 410 and 420 are provided between the output terminal 460 and V_dd, providing independent, parallel conductive paths to V_dd. A single transistor 430 is provided between the output terminal 460 and ground. The “at most one” property of this embodiment can lead to faster charging and discharging of the output terminal 460 than would be provided by generators that employ traditional NAND gates and, therefore, can lead to a shorter peak-to-peak time (t_pp).

[0043] FIG. 5 is a timing diagram illustrating exemplary clock signals CLK, CLK_d and {overscore (CLK_d)} input to the down pulse generator 400 of FIG. 4. In this embodiment, complementary clock signals CLK and {overscore (CLK)} are provided without skew between them. Delayed clock signals CLK_d and {overscore (CLK_d)} may be delayed relative to the source clock signals CLK and {overscore (CLK)} by some predetermined delay. Table 1 below illustrates these input clock signals and the response of the down pulse generator 400 therefrom.

[0044]

	TABLE 1
	T10	T11	T12	T13	T14	T15	T16
CLK	Low	High	High	Low	Low	High	High
{overscore (CLK)}	High	Low	Low	High	High	Low	Low
CLKd	Low	Low	High	High	Low	Low	High
{overscore (CLKd)}	High	High	Low	Low	High	High	Low
Transistor 410	Off	Off	On	On	Off	Off	On
Transistor 420	On	Off	Off	On	On	Off	Off
Transistor 440	Off	Off	On	On	Off	Off	On
Gate 450	Open	Open	Shut	Shut	Open	Open	Shut
Node 470	Low	High	Low	Low	Low	High	Low
Transistor 430	Off	On	Off	Off	Off	On	Off
Output 460	High	Low	High	High	High	Low	High

[0045] During the period defined by T₁₀, the output terminal 460 is driven to V_dd under the influence of transistor 420. The transistor 430 is non-conductive under the influence of the CLK signal that is passed by the open gate 450. Thereafter, the clock signals CLK and {overscore (CLK)} change state.

[0046] At time T₁₁, transistor 420 becomes non-conductive and the transistor 430 becomes conductive, both under the influence of the CLK signal. The transistor 420 no longer pulls the output terminal high. Instead, under influence of the conducting transistor 430, the output terminal 460 is driven toward ground. The switching speed of transistor 430 should be fast because the transistor 440 is fully non-conductive and the gate 450 is fully open. The down pulse begins.

[0047] At time T₁₂, the delayed clock signals CLK_d and {overscore (CLK_d)} change state. The gate 450 may close under the influence of the {overscore (CLK_d)} signal, cutting off the transistor input 470 from the CLK_d signal. Also, the fourth transistor 440 becomes conductive under the influence of the CLK_d signal, pulling the input terminal 470 of the third transistor 430 toward ground. The third transistor 430 becomes non-conductive, thereby releasing the driving effect formerly applied to the output terminal 460. Additionally, the first transistor 410 becomes conductive under the influence of the {overscore (CLK_d)} signal. Thus, the output terminal 460 is driven to V_dd via the conductive path established by the first transistor 410. The active state of the down pulse may conclude.

[0048] At time T₁₃, the CLK and {overscore (CLK)} clocks change state. The second transistor 420 becomes conductive. The output terminal 460 continues to be maintained at V_dd, this time under the influence of the first and second transistors 410 and 420.

[0049] At time T₁₄, the CLK_d and {overscore (CLK_d)} clock signals change state. The gate 450 opens and the fourth transistor 440 ceases to conduct. However, because the CLK signal is low, the response of the third transistor 430 need not change. The charging path between the output terminal 460 and V_dd through first transistor 410 ceases because the first transistor 410 becomes non-conductive. However, the output terminal 460 continues to be maintained at V_dd under the influence of the charging path established by the second transistor 420, which remains conductive under the influence of the CLK signal.

[0050] Thereafter, the clock cycles repeat. The circuit response at times T₁₅ and T₁₆ are the same as the circuit response at times T₁₁ and T₁₂. The down pulse output from the down pulse generator 400 transitions low momentarily but returns to a high level thereafter. As can be seen, the width of the down pulse signal may be determined by the relative delay between the edges of the CLK/{overscore (CLK)} clocks and the edges of the CLK_d/{overscore (CLK_d)} clocks.

[0051] In an alternate embodiment, the circuit structure of FIG. 4 may be employed as an up pulse generator. In this embodiment, transistors 410 and 420 may couple the output terminal 460 to V_dd rather than ground as claimed. Similarly, sources of the transistors 430 and 440 may be coupled to ground rather than V_dd as shown. All other circuit connections may remain unchanged. In this embodiment, the output terminal 460 is maintained at ground at all times except the period between times T₁₁ and T₁₂, when it charges toward V_dd.

[0052] As with the monocycle generator, the down pulse generators may be fabricated in an integrated circuit using any of a number of conventional processes, including CMOS and BJT processes with complementary PNP. In a CMOS embodiment, the first and second transistors 410, 420 in the embodiment of FIG. 4 may be provided as PMOS transistors, becoming conductive when input signals are at a low logical level. The third and fourth transistors 430, 440 may be provided as NMOS transistors, becoming conductive when input signals are at a high logical level.

[0053] FIG. 6 illustrates an up pulse generator 600 according to an embodiment of the present invention. The up pulse generator 600 may include an inverter 610 and a NOR gate 620. The inverter 610 and the NOR gate 620 each may be coupled to a source clock signal CLK. A second input of the NOR gate 620 may be coupled to an output of the inverter 610. The up pulse generator 600 generates an output at ground except for a transition toward V_dd that may occur once per clock cycle.

[0054] As noted, the inverter buffer 610 typically imposes a propagation delay upon an input clock signal. Thus, the signal input to the NOR gate 620 is a delayed inverted signal (labeled “{overscore (CLK_d)}”) with respect to the source signal CLK. In response to these two signals, the NOR gate 620 generates an up pulse that is logically low at all times except at the falling edge of the CLK signal. A transition in the CLK signal from high to low may cause a corresponding transition in the output of the NOR gate 620 (to high). This up pulse may have a duration that is defined by the delay induced by the inverter 610 and the NOR gate 620.

[0055] In an embodiment, the single inverter 610 actually may be provided as a cascaded chain of inverters (multiple inverters 610.1–610.N are shown in phantom). Thus, the delay of the {overscore (CLK_d)} signal with respect to the source signal CLK may be tuned as desired.

[0056] The NOR gate may be provisioned according to any of the known architectures for such gates. Many of these known architectures have charge paths and discharge paths (paths from the output terminal to either V_dd or ground) that traverse multiple switching transistors. The multiple switching transistors can determine a maximum rate at which the monocycle can charge toward V_dd or discharge toward ground. Again, because it is desirable in many applications to minimize the peak-to-peak time of the monocycle, faster up pulse generators may be desirable.

[0057] FIG. 7 is a circuit diagram of an up pulse generator 700 according to an embodiment of the present invention. The embodiment of FIG. 7 may include four transistors 710–740 and a transmission gate 750. First and second transistors 710, 720 may couple an output terminal 760 to ground. The first transistor 710 may be controlled by a delayed inverted clock signal {overscore (CLK_d)}. The second transistor 720 may be controlled by the clock signal CLK. A third transistor 730 may bridge the output terminal 760 to V_dd. Thus, charging paths (from the output terminal 760 to V_dd) and discharging paths (from the output terminal 760 to ground) traverse at most one switching transistor in this embodiment.

[0058] The fourth transistor 740 may bridge between V_dd and an input of the third transistor 730. The fourth transistor 740 may be controlled by a delayed clock signal CLK_d. The gate 750 may bridge the input of the third transistor 730 to a source of the clock signal CLK. The gate 750 itself may be controlled by the delayed clock signal CLK_d.

[0059] FIG. 8 is a timing diagram illustrating exemplary clock signals CLK, CLK_d and {overscore (CLK_d)} that may be input to the down pulse generator 700 of FIG. 7. Table 2 below illustrates the response of the circuit 700 from the input clock signals shown.

[0060]

	TABLE 2
	T20	T21	T22	T23	T24	T25	T26
CLK	High	Low	Low	High	High	Low	Low
{overscore (CLK)}	Low	High	High	Low	Low	High	High
CLKd	High	High	Low	Low	High	High	Low
{overscore (CLKd)}	Low	Low	High	High	Low	Low	High
Transistor 710	Off	Off	On	On	Off	Off	On
Transistor 720	On	Off	Off	On	On	Off	Off
Transistor 740	Off	Off	On	On	Off	Off	On
Gate 750	Open	Open	Shut	Shut	Open	Open	Shut
Node 770	High	Low	High	High	High	Low	High
Transistor 730	Off	On	Off	Off	Off	On	Off
Output 760	Low	High	Low	Low	Low	High	Low

[0061] During the period defined by T₂₀, the output terminal 760 is maintained at ground under the influence of the second transistor 720. The third transistor 730 is non-conductive under the influence of the CLK signal that is passed by the open gate 750.

[0062] At time T₂₁, the clock signals CLK and {overscore (CLK)} change state. Transistor 720 becomes non-conductive and transistor 730 becomes conductive, both under the influence of the CLK signal. The output terminal 760 may charge toward V_dd. The up pulse begins.

[0063] At time T₂₂, the clock signals CLK_d and {overscore (CLK_d)} change state. The changing state of CLK_d causes the gate 750 to close, thereby cutting off the transistor input 770 from the CLK source. The CLK_d signal also causes the fourth transistor 740 to become conductive, thereby driving the input of the third transistor 730 toward V_dd. This renders the third transistor 730 non-conductive. Also at this time, the {overscore (CLK_d)} signal renders the first transistor 710 conductive. The first transistor 710 drives the output terminal 760 toward ground and terminates the up pulse.

[0064] At time T₂₃, the clock signals CLK and {overscore (CLK)} change state again. The second transistor 720 becomes conductive, establishing a second independent discharging path between the output terminal 760 and ground. At time T₂₄, when the clock signals CLK_d and {overscore (CLK_d)} change state, the CLK_d signal opens gate 750 and renders the fourth transistor 740 non-conductive. Although the gate 750 open and passes the CLK signal to the transistor input 770, the CLK signal does not cause the third transistor 730 to become conductive. Under the {overscore (CLK_d)} signal, the first transistor 710 ceases to be conductive. The discharging path of the second transistor 720, however, is not disturbed.

[0065] At times T₂₅ and T₂₆, the pattern repeats. The inputs shown at time T₂₅ duplicate those of time T₂₁. Another up pulse begins. The inputs at time T₂₆ duplicate those of time T₂₂. The up pulse concludes. Thus, the up pulse generator 700 generates an up pulse in each clock cycle having a duration determined by the relative delays between the CLK/{overscore (CLK)} clocks and the CLK_d/{overscore (CLK_d)} clocks.

[0066] In an alternate embodiment, the circuit structure of FIG. 7 may be employed as a down pulse generator. In this embodiment, transistors 710 and 720 may couple the output terminal 760 to ground rather than V_dd as shown. Similarly, sources of the transistors 730 and 740 may be coupled to V_dd rather than ground as shown. All other circuit connections may remain unchanged. In this embodiment, the output terminal 760 is maintained at V_dd at all times except the period between times T₁₁ and T₁₂, when it charges toward ground.

[0067] The signals shown in FIGS. 5 and 8 are idealized representations. Depending upon switching times of the transistors and relative skew between the CLK/{overscore (CLK)} clocks and the CLK_d/{overscore (CLK_d)} clocks, the signals used in an actual circuit may deviate from the representations shown in the figures. Such deviations are entirely consistent with the purpose and intent of the present inventions.

[0068] As with the monocycle generator, the up pulse generators may be fabricated in an integrated circuit using any of a number of conventional processes, including CMOS processes and BJT processes with complementary PNP. In a CMOS embodiment, the first and second transistors 710, 720 in the embodiment of FIG. 7 may be provided as NMOS transistors, becoming conductive when input signals are at a high logical level. The third and fourth transistors 730, 740 may be provided as PMOS transistors, becoming conductive when input signals are at a low logical level.

[0069] FIG. 9 illustrates a system 900 for generating the CLK, {overscore (CLK)}, CLK_d and {overscore (CLK_d)} clocks signals from a source clock CLK_src according to an embodiment of the present invention. This system may include a differential clock generator 910 and a pair of delay blocks 920, 930. The differential clock generator 910 may include a transmission gate 912.1 and an inverter 914.1, each coupled to the source clock CLK_src. The inverter 914.1, as its name implies, inverts the source clock CLK_src and generates a {overscore (CLK)} signal. The transmission gate 912.1 propagates the source clock CLK_src without a change in state. In an alternate embodiment, rather than provide a single inverter 914.1 and a single transmission gate 912.1, the differential clock generator 910 may include multiple transmission gates 912.1–912.N and inverters 914.1–914.N.

[0070] As explained above, a typical inverter 914.1 not only inverts the state of an input signal but it also incrementally delays propagation of the signal. Thus, edges of the {overscore (CLK)} signal may be expected to be delayed incrementally with respect to the source clock CLK_src. Typical transmission gates 912.1 also incrementally delay input signals even though they do not change state. Thus, provided there are an equal number of transmission gates 912.1–912.N and inverters 914.1–914.N, there should be substantially no skew between the CLK and {overscore (CLK)} clocks. In an alternate embodiment, transmission gates may be provided for all but one inverter 914.1–914.N.

[0071] The delay blocks 920, 930, in an embodiment, each may be populated by a cascaded series of inverters 920.1–920.M, 930.1–930.M. In an embodiment, the number of inverters and sizing of transistors within the inverters 920.1–920.M, 930.1–930.M may provisioned similarly between the two delay blocks 920, 930 so as to minimize skew between the CLK_d and {overscore (CLK_d)} outputs. In an embodiment where an even number of inverters are provided in the delay blocks 920, 930, the CLK_d clock may be derived from the CLK input clock and the {overscore (CLK_d)} clock may be derived from the {overscore (CLK)} clock. Alternatively, in an embodiment where an odd number of inverters are provided in the delay blocks 920, 930, the CLK_d clock may be derived from the {overscore (CLK)} clock and the {overscore (CLK_d)} clock may be derived from the CLK clock. The number of inverters and their sizing may be tuned to meet individual design applications for which the up pulse generators and down pulse generators are to be used.

[0072] The foregoing embodiments of up pulse generators and down pulse generators, if operative from the same clock signals, generate up pulses and down pulses that are separated by half a clock cycle. For example, as shown in FIG. 5, the downpulse is synchronized to the rising edge of the CLK signal but, as shown in FIG. 8, the up pulse is synchronized to the falling edge of the same CLK signal. In an embodiment, it may be desirable to synchronize up pulses and down pulses to the same event.

[0073] In one embodiment, to synchronize the pulses, it is sufficient to reverse the polarities of all clocking inputs to one of the pulse generators except the control input of the transmission gate. With reference to FIG. 7, for example, the {overscore (CLK)} signal may be input to the transistor 720 and the transmission gate 750, the CLK_d signal may be input to the transistor 710 and the {overscore (CLK_d)} signal may be input to the transistor 740. The control input of the transmission gate 750 may be coupled to the CLK_d input. Circuit response of this embodiment is provided below in Table 3:

[0074]

	TABLE 3
	T20	T21	T22	T23	T24	T25	T26
CLK	High	Low	Low	High	High	Low	Low
{overscore (CLK)}	Low	High	High	Low	Low	High	High
CLKd	High	High	Low	Low	High	High	Low
{overscore (CLKd)}	Low	Low	High	High	Low	Low	High
Transistor 710	On	On	Off	Off	On	On	Off
Transistor 720	Off	On	On	Off	Off	On	On
Transistor 740	On	On	Off	Off	On	On	Off
Gate 750	Shut	Shut	Open	Open	Shut	Shut	Open
Transistor 730	Off	Off	Off	On	Off	Off	Off
Node 770	High	High	High	Low	High	High	High
Output 760	Low	Low	Low	High	Low	Low	Low

Thus, this embodiment provides an up pulse that is synchronized to the rising edge of the CLK signal. A similar inversion of inputs to the down pulse generator 400 may cause a half-cycle shift in the activation of the down pulse.

[0075] Alternatively, one of the pulse generators (the up pulse generator 700 or the down pulse generator 400) may include a delay element to impose a half-cycle delay upon the output of a respective pulse. Half-cycle delay elements 480 (FIG. 4) and 780 (FIG. 7) are shown in phantom for this purpose. A similar delay block also may be provided for the up pulse generator 600 or down pulse generator 300 of FIGS. 6 and 3.

[0076] FIG. 10 is an embodiment of a monocycle generator 1000 according to another embodiment of the present invention. In this embodiment, the monocycle generator 1000 may include a pair of input terminals 1005, 1010 for respective down pulse and up pulse inputs and an output terminal 1015 for the monocycle pulse. The monocycle generator 1000 may include a first pair of transistors 1020, 1025 bridging the output terminal 1030 to V_dd and ground respectively. The first transistor 1020 may be controlled by the down pulse and the second transistor 1025 may be controlled by the up pulse. The behavior of the two transistors 1020, 1025 is similar to that of the two transistors 140, 150 from the pulse generator 100 of FIG. 1.

[0077] In this embodiment, a voltage regulator 1030 may substitute for the voltage divider of FIG. 1. The voltage regulator 1030 may reduce the amount of current flow between the second V_dd-to-ground path, the path that returns the output terminal 1015 to the intermediate potential after the monocycle is generated. The monocycle generator 1000 also may include optional cut off transistors 1035, 1040, coupling the voltage regulator 1030 to V_dd and ground respectively. The cut off transistors 1035, 1040 may be rendered nonconductive in response to respective up pulses or down pulses in a manner similar to the transistors 180, 190 of FIG. 1.

[0078] Voltage regulators are known per se. The voltage regulator 1030 of FIG. 10 may be implemented according to any of the architectures known in the art. One such architecture is shown in FIG. 10. In this embodiment, the voltage regulator 1030 includes a pair of transistors 1045,1050 bridging between V_dd and ground (or, if the current cut off transistors 1035, 1040 are provided, between these current cut off transistors). The output terminal 1015 is coupled to a node between the transistors 1045, 1050. These transistors 1045, 1050 form a first current path in the voltage regulator 1030.

[0079] The voltage regulator 1030 also includes a current source 1055 and second pair of transistors 1060, 1065 bridging between V_dd and ground. The current source 1055 and the transistors 1060, 1065 form a second current path in the voltage regulator 1030. Each of the second pair of transistors 1060, 1065 have an input coupled to a respective operational amplifier (colloquially, “op amp”) 1070, 1075. Inputs of each of the first pair of transistors 1045, 1050 also may be coupled to one of the op amps 1070, 1075. A first input to each of the op amps 1070, 1075 is coupled to a node between the second pair of transistors 1060, 1065. A second input to the op amps 1070, 1075 is coupled to a reference potential source (V_ref) 1080. The reference potential may be set to ½ V_dd.

[0080] Operation of voltage regulators is well known and need not be repeated here. As is known, the ratio of current through the first and second current paths may be determined by relative sizes of transistors through the path. Thus, to maintain a desired current flow through the first current path, the current flow through the second current path may be regulated correspondingly. For example, using a 3-to-1 ratio between the first pair of transistors 1045, 1050 and the second pair of transistors 1060, 1065, a 100 μA current through the second pair of transistors induces a 300 μA current through the first pair of transistors 1045, 1050 (when cut off transistors 1035, 1040, if any, are conductive).

[0081] The embodiment of FIG. 10 returns the potential of the output terminal 1015 to the reference potential (½ V_dd) at transition speeds that rival the voltage divider of FIG. 1. This may occur with a current flow as low as 900 μA through the first current path and as low as 300 μA through the second current path (1200 μA total). By contrast, resistors 160, 170 in the voltage divider of FIG. 1 typically match impedances of antennae or other transmitting equipment (not shown). Their resistance may be tuned to some predetermined value (say, between 50–100 ohms each). Using a hypothetical V_dd of 1.8 volts, current flow through the voltage divider will be:

[0082] $I=\frac{V}{R}=\frac{1.8V}{200\Omega }=9000\mathrm{\mu A}$
Thus, the voltage regulator 1030 can yield significant current conservation over the embodiment of FIG. 1.

[0083] FIG. 11 illustrates another embodiment of a monocycle generator 1100, one that generates a pair of monocycle pulses at a pair of differential output terminals 1110, 1115. This embodiment yields monocycle pulses having twice the output voltage as in the foregoing embodiments. It also eliminates current drain from V_dd to ground when the monocycle generator is inactive (when the output of the generator is maintained at ½ V_dd).

[0084] The monocycle generator 1100 may include a pair of pull up transistors 1120, 1125, each coupling a respective output terminal 1110, 1115 to V_dd. The monocycle generator 1100 also may include a pair of pull down transistors 1130, 1135, each coupling a respective output terminal 1110, 1115 to ground. The pull up transistors 1120, 1125 each may be controlled by respective down pulses at their inputs. The pull down transistors 1130, 1135 may be controlled by respective up pulses at their inputs.

[0085] The monocycle generator 1100 also may include a voltage divider network, populated by a pair of resistors 1140, 1145 may bridge between the output terminals 1110, 1115. A reference voltage source 1150 may maintain a node between the two resistors 1140, 1145 at a reference potential (say, ½ V_dd).

[0086] FIG. 12 illustrates response of the monocycle generator 1100 in response to exemplary input signals at the four transistors. Throughout a period labeled T₃₀, input signals to the four transistors maintain all the transistors in a non-conductive state. The reference voltage source 1150 maintains the potential of both output terminals 1110, 1115 at the reference potential (½ V_dd). At time T₃₁, a down pulse is input to the first pull up transistor 1120 and an up pulse is input to the second pull down transistor 1135. Both become conductive in response to these signals. Thus the first output terminal 1110 charges toward V_dd and the second output terminal discharges toward ground. The transistors 1120, 1135 remain conductive until time T₃₂ when the activation pulses to the transistors 1120, 1135 terminate.

[0087] At time T₃₂, new activation pulses are applied to the second pull up transistor 1125 and the first pull down transistor 1130. They become conductive. Thus, the first output terminal 1110, which had been charged to V_dd by the first pull up transistor 1110, discharges to ground via the first pull down transistor 1130. Similarly, the second output terminal 1115, which had discharged to ground via transistor 1135, charges to V_dd via the second pull up transistor 1125. The transistors 1125, 1130 may remain conductive until time T₃₃ when the activation pulses to transistors 1125, 1130 terminate.

[0088] After time T₃₃, when the four transistors cease to conduct, the two output terminals return to the intermediate potential under the influence of the reference voltage source 1150.

[0089] FIG. 12 illustrates operation of the monocycle generator 1100 in response to a single set of activation pulses. Of course, activation pulses may be applied to transistors 1125, 1130 first and to transistors 1120, 1135 thereafter. In this event, the orientation of the monocycles shown in FIG. 12 would be inverted. As in the prior embodiment, the monocycle pulses may be made to carry information by varying their orientation.

[0090] As in the prior embodiments, the monocycle generator 1100 may be fabricated in an integrated circuit using any of a number of conventional processes, including CMOS processes and BJT processes with complementary PNP. In a CMOS embodiment, the pull up transistors 1110, 1115 may be provided as PMOS transistors, becoming conductive when input signals are at a low logical level. The pull down transistors 1120, 1125 may be provided as NMOS transistors, becoming conductive when inputs signals are at a high logical level.

[0091] FIG. 13 illustrates another embodiment of a monocycle generator 1300. This embodiment also generates a differential pair of monocycles on output terminals 1310, 1315 at twice the output voltage as in the embodiment of FIG. 1. Additionally, the monocycle generator 1300 eliminates current flow from V_dd to ground when the monocycle generator 1300 is inactive, when the output terminals each are maintained at the intermediate potential.

[0092] The monocycle generator 1300 may include a pair of pull up transistors 1320, 1325, each coupling a respective output terminal 1310, 1315 to V_dd. The monocycle generator 1300 also may include a pair of pull down transistors 1330, 1335, each coupling a respective output terminal 1310, 1315 to ground. The pull up transistors 1320, 1325 each may be controlled by respective down pulses at their inputs. The pull down transistors 1330, 1335 may be controlled by respective up pulses at their inputs.

[0093] The monocycle generator 1300 also may include a voltage divider network, populated by a pair of transistor 1340, 1345, that bridges between the output terminals 1310, 1315. A reference voltage source 1350 may maintain a node between the two transistors 1340, 1345 at a reference potential (say, ½ V_dd).

[0094] The circuit response illustrated in FIG. 12 also applies to the monocycle generator of FIG. 13. FIG. 12 illustrates additional input signals IN₅ and IN₆ that may be input to the transistors 1340, 1345. These input signals IN₅ and IN₆ may maintain the bridging transistors 1340, 1345 in a conductive state at all times except the period extending from time T₃₁ to T₃₃. Thus, the bridging transistors 1340, 1345 may be non-conductive when the pull up and pull down transistors 1320–1335 are conductive and vice versa.

[0095] The embodiment of FIG. 13 may be useful in applications where it may be useful to match the impedance of the monocycle generator 1300 with other external elements such as antennae. FIG. 13 illustrates in phantom a 50 ohm antenna coupled to each of the output terminals 1310, 1315 of the monocycle generator 1300. If the monocycle generator 1100 of FIG. 11 were used in this application, the resistors 1140, 1145 also would be 50 ohms to create an impedance match with the antennae load. This sizing would cause effective loads of 25 ohms at the pull up transistors 1120, 1125 and the pull down transistors 1130, 1135, requiring these elements to be relatively larger than corresponding elements in the embodiment of FIG. 13.

[0096] The monocycle generator 1300 of FIG. 13, however, permits provision of smaller pull up and pull down transistors 1320–1335 but to have an impedance that matches the effective load at the output terminals (say, 50 ohms to match the antenna load). The bridging transistors 1340, 1345 are conductive only when the pull up and pull down transistors 1320–1335 are non-conductive. Thus, when the bridging transistors 1340, 1345 are conductive, there is an impedance match between the bridging transistors and the load. But, at other times, the pull up and pull down transistors “see” only the impedance of the load itself. Accordingly, this embodiment may find use in applications where the monocycle generator 1300 may be expected to drive an external load.

[0097] As in the prior embodiments, the monocycle generator 1300 may be fabricated in an integrated circuit using any of a number of conventional processes, including CMOS processes and BJT processes with complementary PNP. In a CMOS embodiment, the pull up transistors 1310, 1315 may be provided as PMOS transistors, becoming conductive when input signals are at a low logical level. The pull down transistors 1320, 1325 may be provided as NMOS transistors, becoming conductive when inputs signals are at a high logical level.

[0098] FIG. 14 is a block diagram of a transmitter 1400 according to an embodiment of the present invention. The transmitter 1400 may include a monocycle generator 1405, a down pulse generator 1410 and an up pulse generator 1415 provisioned according to any of the foregoing embodiments. The transmitter 1400 also may include a pair of data modulators 1420, 1425 coupled to a clock source CLK. A first data modulator 1420 may be responsive to an input DATA signal when the signal is a first binary value (say, logical “1”), the second data modulator 1425 may be responsive to the input DATA signal when the signal is a second binary value (say, logical “0”).

[0099] The first data modulator 1420 may include a fast path 1430 and a slow path 1435 for an input clock signal CLK. The slow path 1435 may include a delay block 1440 to delay propagation of the clock signal CLK with respect to the fast path 1430. Both paths 1430, 1435 may include control logic 1445, 1450 to disable propagation of the clock signal CLK unless the data signal is of a predetermined value (say, logical “1”).

[0100] The second data modulator 1425 may have a structure similar to the first data modulator 1420. It may include fast and slow paths 1455, 1460, with a delay block 1465 provided along the slow path 1460. The second data modulator 1425 also may include control logic 1480, 1475 to disable propagation of the clock signal CLK unless the data signal if of a predetermined value (say, logical “0”). The control logic 1445, 1450, 1480, 1475 among the two data modulators 1420, 1425 may be provisioned in complementary fashion so that only one data modulator 1420, 1425 is responsive to each value of the data signal.

[0101] In an embodiment, the delay blocks 1440, 1465 may impose a predetermined delay upon the propagation of the clock signals. The delay blocks 1440, 1465 may be provisioned as a cascaded series of inverters. The delay characteristic of the delay blocks 1440,1465 may be tuned for the application for which the data modulators 1420,1425 are to be used.

[0102] According to an embodiment, outputs from the data modulators 1420, 1425 may be coupled to CLK inputs of the down pulse and up pulse generators 1410, 1415 in complementary fashion. The fast path from a first data modulator (say, path 1430 from modulator 1420 ) and the slow path from a second data modulator (say, path 1460 from modulator 1425 ) may be coupled to the down pulse generator 1410. The fast path 1455 from the second modulator 1425 and the slow path 1435 from the first modulator 1420 may be coupled to the CLK input of the up pulse generator 1415.

[0103] In this fashion, the data modulators 1420, 1425 may modulate the timing with clock signals are input to the down pulse and up pulse generators 1410, 1415. When the data signal is a logical “1,” for example, the first data modulator 1420 is enabled. Via the fast path 1430, the clock signal CLK may propagate without delay to the down pulse generator 1410, causing a down pulse to be applied to the monocycle generator 1405. After some period of time, the clock signal CLK propagates through the delay block 1440 to the up pulse generator 1415, causing an up pulse to be applied to the monocycle generator 1405. As explained with respect to FIG. 2, the down pulse-up pulse progression may cause the monocycle generator 1405 to produce a monocycle pulse having a predetermined orientation, such as the pulse of FIG. 2(d).

[0104] When the data signal is a logical “0,” however, the second data modulator 1425 may be enabled. Via its fast path 1445, the clock signal CLK may propagate without delay to the up pulse generator 1415, causing an up pulse to be applied to the monocycle generator 1405. After some period of time, the clock signal CLK propagates through the delay block 1465 to the down pulse generator 1410, causing a down pulse to be applied to the monocycle generator 1405. As explained with respect to FIG. 2, the up pulse-down pulse progression may cause the monocycle generator 1405 to produce a monocycle pulse having a predetermined orientation, such as the pulse of FIG. 2(e).

[0105] In an embodiment where the down pulse and/or up pulse generators 1410, 1415 are provided according to FIGS. 4 or 7, the transmitter 1400 may include a differential clock generator and delay blocks as shown in FIG. 9. Outputs from the data modulators 1420, 1425 would be input to respective differential clock generators. Outputs from the respective sets of differential clock generators and delay blocks would be input to the pulse generators as described above. This embodiment is not shown in FIG. 14 so as to maintain clarity of the presentation.

[0106] FIG. 15 is a block diagram of a transmitter 1500 according to another embodiment of the present invention. In this embodiment, the transmitter 1500 may include a monocycle generator 1510, a down pulse generator 1520, an up pulse generator 1530 and a single data modulator 1540. The data modulator 1540 may include a fast path and a slow path having a delay block 1550. The fast path may be coupled to the up pulse generator 1530 and down pulse generator 1520 by respective transmission gates 1560, 1570. The slow path may be coupled to the up pulse generator 1530 and down pulse generator 1520 by a second set of transmission gates 1580, 1590. The transmission gates 1560,1590 may open in response to a first state of a data signal (say, logical “1”); transmission gates 1570, 1580 may open in response to a complementary state of the data signal (logical “0”).

[0107] The embodiment of FIG. 15 modulates the delivery of clock signals to the up pulse and down pulse generators 1530, 1520 in response to the state of the data signal. Accordingly, the data signal may control delivery of activation pulses to the monocycle generator 1510 and, therefore, causes the monocycles to carry digital data.

[0108] In an embodiment where the down pulse and/or up pulse generators 1530, 1520 are provided according to FIGS. 4 or 7, the transmitter 1500 may include a differential clock generator and delay blocks as shown in FIG. 9. Outputs from the data modulator 1540 would be input to respective differential clock generators. Outputs from the respective sets of differential clock generators and delay blocks would be input to the pulse generators as described above. This embodiment is not shown in FIG. 15 so as to maintain clarity of the presentation.

[0109] As shown in the embodiments of FIGS. 14 and 15, the clock signals output from the data modulators may be used as the clock signals input to the down pulse generators 1410/1520 and up pulse generators 1415/1530.

[0110] The foregoing embodiments present monocycle generators in which pull up transistors and pull down transistors, such as transistors 140, 150 of FIG. 1, have complementary device types (e.g., PMOS for one, NMOS for the other) and are responsive to respective down pulse and up pulse activation signals. The principles of the present invention, however, are not so limited. They may find application in embodiments where the pull up and pull down transistors both are of a single device type. For example, with reference to FIG. 1, the transistors 140 and 150 both could be provided as PMOS transistors to be responsive to respective downpulse activation signals. In this embodiment, timing between the respective down pulse signals may be modulated to cause orientation of the monocycles generated therefrom to reflect digital data. Similarly, the transistors 140, 150 both could be provided as NMOS transistors and responsive to staggered up pulse activation signals whose timing is modulated to reflect information. Any of the monocycle generators presented above could be so provisioned.

[0111] Based on current process techniques, it is expected that embodiments where pull up and pull down transistors 140, 150 are provisioned as like kind device types may not perform as well as embodiments where the device types differ between the two transistors. In a CMOS implementation, for example, provision of like kind device types may cause a monocycle to exhibit asymmetry. Consider an example where the two transistors 140, 150 of FIG. 1 both are provided as NMOS transistors. The pull down transistor 150 may pull an output terminal 130 fully to ground when it is rendered conductive. However, an NMOS pull up transistor 140 may not pull the output terminal fully to V_dd. More likely, it will pull the output terminal 130 to within about ½ a volt of V_dd but no more. Thus, a monocycle generated from this circuit would be “lopsided.” The like-kind embodiments are suited for applications where asymmetrical monocycles do not affect system performance. And, of course, when new process technologies become available in which a single device can pull to ground and to V_dd equally as well, the like-kind embodiments becomes suited for all applications.

[0112] The foregoing discussion has presented pulse generators and driving circuits therefore that build timing relationships based upon the switching responses of the transistors and other elements that populate these circuits. That the timing relationships are determined by the switching responses of these elements raises an interesting consequence for these circuit architectures—as the processes and materials used in integrated circuits improve, so will the speeds of the monocycles generated by these circuits. Currently, these circuits are foreseen for implementation in integrated circuit manufactured from a standard 0.18 μm CMOS process, yielding a 80 picosecond peak-to-peak monocycle pulse. Of course, the circuit architectures described above may be applied using a variety of transistor structures including, for example, bipolar junction transistors. Hypothetically, if the circuit architectures were applied using transistor structures that have switching speeds that double those achieved by the 0.18 μm CMOS process, the monocycle pulse duration would reduce by 50%. A shorter duration would yield improved communication efficiency. Thus, the circuit architectures may “ride along” with improvements in manufacturing processes and yield higher communications efficiencies with such improvements.

[0113] Although the circuit architectures presented above can yield a 80 picosecond monocycle pulse width, variations in manufacturing processes, variations in operating temperatures and other errata can alter this pulse width and lower performance. To minimize variations in the pulse width, it may be advantageous to control power supplied to the monocycle generator.

[0114] FIG. 16 is a block diagram of a skew controller 1600 according to an embodiment of the present invention. The skew controller 1600 may include a phase detector 1610, a charge pump 1620 and a delay block 1630. The phase detector 1610 may accept two inputs, an externally-supplied clock signal CLK_ext and a delayed version of the CLK_ext signal (labeled CLK_del). Based on a detected difference between the two clock signals, the phase detector 1610 may generate a control signal to the charge pump 1620, causing it to raise or lower the voltage output therefrom. The output of the charge pump 1620 may be distributed to the monocycle generator and other circuits described above as a source of the V_dd signal via a buffer 1640. The output of the charge pump 1620 may be filtered prior to being input to the buffer 1640 (box 1650).

[0115] The delay block 1630 may be a one-cycle delay element. In one embodiment, it may include a series of cascaded inverters (not shown) provided in sufficient number to delay the CLK_ext signal a complete clock cycle. Thus, under ideal operating conditions and at steady state, the two clock signals would be identical to each other when input to the phase detector 1610. But, depending upon the process used to fabricate the skew controller 1600 or the temperature at which it operates, the delay imposed by the block 1630 may not be perfectly one cycle in duration. The phase detector 1610 and the charge pump 1620 may modify the output voltage (V_dd) in response to this skew. By modifying the output voltage, the phase detector 1610 and the charge pump 1620 may alter the switching delays imposed by transistors within the delay block 1630, thereby reducing and eventually eliminating the skew. Thus, the effects of process and temperature variations may be minimized by a skew controller 1600 as shown in FIG. 16.

[0116] When fabricated in an integrated circuit, the monocycle generator, the skew controller 1600 and the other circuit may be provided in the same integrated circuit (colloquially, “chip”). Thus, although manufacturing processes and operating temperatures can vary widely from chip to chip, these variables can be expected to be uniform within a chip. In an embodiment, the same types of transistors may be used throughout the skew controller 1600, the monocycle generator 100 and the other circuits. This structure helps to maintain the monocycle pulse width (t_pp) constant despite variations in process and operating temperature.

[0117] Although FIG. 16 illustrates an exemplary skew controller 1600 that may be used with the monocycle generator and other circuits shown hereinabove, their use is by no means restricted to systems that employ such a skew controller. Other methods and techniques are known in the art for regulating circuit performance in view of process and temperature variations; the monocycle generator and other circuits may be used with such techniques without restriction. Indeed, the monocycle generator and other circuits, in some applications, may be used without such ameliorative techniques. A selection among these techniques may be determined by the applications for which the monocycle generator is to be used.

[0118] Many of the foregoing embodiments have described techniques that may be used to tailor response of the monocycle generator to communications applications. However, it should be remembered that the monocycle generators described hereinabove may find utility in other applications and are not so confined. To apply the monocycle generator to use with the synchronous oscillators or in radar applications, for example, it may be desirable to generate monocycle pulses having a predetermined orientation and timing. In such embodiments, rather than modulate timing relationships among the activation pulses, it may be preferred to apply activation pulses to the monocycle generators according to some predetermining timing scheme. Such applications also are envisioned for the monocycle generators described above.

[0119] Several embodiments of the present invention are specifically illustrated and described herein. However, it will be appreciated that modifications and variations of the present invention are covered by the above teachings and within the purview of the appended claims without departing from the spirit and intended scope of the invention.