Wide lock range phase locked loop and method of operation

[0001] 1. Field of the Invention

[0002] The present invention relates to a wide lock range phase locked loop (PLL) type frequency synthesizer including a plurality of voltage controlled oscillators and its method for selecting an oscillation frequency.

[0003] 2. Description of the Related Art

[0004] Generally, in a mobile telephone apparatus, a wide lock range PLL type frequency synthesizer having a plurality of voltage controlled oscillators is mounted as a local oscillator to cope with different frequencies.

[0005] In a prior art wide lock range PLL type frequency synthesizer (see: JP-A-10-200406) including a PLL circuit having a phase/frequency comparator, a charge pump circuit, a loop filter, a voltage controlled oscillator block formed by a plurality of voltage controlled oscillators and a plurality of switches connected to the voltage controlled oscillators, and a 1/N frequency divider where N is a positive integer, an unlock control circuit is provided. The unlock control circuit has an unlocked state detecting circuit, an up/down counter, and a selector for selecting one of the switches in accordance with the output signals of the up/down counter. In this case, the up/down counter is connected to the phase/frequency comparator. That is, in an unlocked state, the unlocked state detecting circuit passes the output signals of the phase/frequency comparator to the up/down counter. As a result, when the phase/frequency comparator generates a leading signal, the up/down counter is counted up. Therefore, when the value of the up/down counter reaches its maximum value, the up/down counter generates an overflow carry signal, so that the selector selects another switch. Contrary to this, when the phase/frequency comparator generates a lagging signal, the up/down counter is counted down. Therefore, when the value of the up/down counter reaches its minimum value, the up/down counter generates an underflow carry signal, so that the selector selects another switch. Thus, as the oscillation frequency of the voltage control oscillator block fluctuates due to a temperature fluctuation or power supply voltage fluctuation, the up/down counter and the selector and are operated to quickly move a phase unlocked state to a phase locked loop stage. This will be explained later in detail.

[0006] In the above-described prior art PLL type frequency synthesizer, however, since the up/down counter is operated by the output signals of the phase/frequency comparator, when the precision of the phase/frequency comparator is enhanced, the precision of the up/down counter also has to be enhanced. As a result, the switching from a phase unlocked state to a phase locked state is delayed which increases the lockup time.

[0007] Also, in the above-described prior art PLL type frequency synthesizer, since all the voltage controlled oscillators are always operated, the power consumption would be increased.

[0008] It is an object of the present invention to provide a wide lock range PLL type frequency synthesizer capable of enhancing the precision of a phase/frequency comparator without decreasing the lockup time.

[0009] Another object is to provide a wide lock range PLL type frequency synthesizer capable of suppressing power consumption.

[0010] A further object is to provide a method for selecting an oscillation frequency in a wide lock range PLL type frequency synthesizer.

[0011] According to the present invention, in a phase locked loop type frequency synthesizer including a phase/frequency comparator for receiving an input signal, a charge pump circuit, a loop filter for generating a control voltage, a voltage control oscillator block including a plurality of voltage controlled oscillators controlled by the control voltage, and a frequency divider formed by a fixed frequency divider and a programmable frequency divider, a selecting circuit selects and actuates only one of the voltage controlled oscillators, and counts a number of output pulses of the first frequency divider within a predetermined number of output pulses of the input signal while applying a bias voltage to the loop filter. Thus, one of the voltage controlled oscillators is selected so that the number of the output pulses of the first frequency divide is brought close to an optimum value.

[0020] Before the description of the preferred embodiment, a prior art wide lock range PLL type frequency synthesizer will be explained with reference to FIG. 1 (see: JP-A-10-200406).

[0021] In FIG. 1, the frequency synthesizer receives an input signal IN having a frequency f_r to generate an output signal OUT having a frequency of N·f_r where N is a variable positive integer supplied from a programmable terminal P.

[0022] A phased-lock loop circuit is constructed by a phase/frequency comparator 1, a charge pump circuit 2, a loop filter 3, a voltage controlled oscillator block 4 and a 1/N frequency divider 5.

[0023] The phase/frequency comparator 1 compares the phase of the input signal IN with that of an output signal of the 1/N frequency divider 5 to generate a leading signal UP and a lagging signal DN. As a result, the charge pump circuit 2 charges the loop filter 3 in accordance with the leading signal UP and discharges the loop filter 3 in accordance with the lagging signal DN, so that the loop filter 3 generates a control voltage V_C. The control voltage V_C is supplied to the voltage controlled oscillator block 4, thus controlling the oscillation frequency f_vco of the voltage controlled oscillator block 4, i.e., the frequency of the output signal OUT. This output signal OUT is also supplied via the 1/N frequency divider 5 to the phase/frequency comparator 1. Therefore, in a phase locked state, the frequency f_vco/N of the 1/N frequency divider 5 is brought close to the frequency f_r of the input signal IN, i.e.,
f_r≈f_vco/N
∴f_vco≈N·f_r

[0024] The voltage controlled oscillator block 4 is constructed by a plurality of voltage controlled oscillators 41-0, 41-1, 41-2, . . . , 41-(m−1) where m is a positive integer larger than 1, and switches 42-0, 42-1, 42-2, . . . , 42-(m−1). In this case, the oscillation frequency characteristics of the voltage controlled oscillators 41-0, 41-1, 41-2, . . . , 41-(m−1) dependent upon the control voltage V_C are different from each other, thus realizing a wide lock range. Also, the selectors 42-0, 42-1, 42-2, . . . , 42-(m−1) select output signals of the voltage controlled oscillators 41-0, 41-1, 41-2, . . . , 41-(m−1), respectively, In this case, only one of the switches 42-0, 42-1, 42-2, . . . , 42-(m−1) is turned ON while the other switches are turned OFF. Thus, different oscillation frequencies can be realized by selecting the switches 42-0, 42-1, 42-2, . . . , 42-(m−1).

[0025] Also, an unlock control circuit having an unlocked state detecting circuit 6, an up/down counter 7 and a selector 8 is provided. The selector 8 generates one selection signal SEL(0), SEL(1), SEL(2), . . . , SEL(m−1) for selecting the switches 42-0, 42-1, 42-3, . . . , or 42-(m−1). That is, in a phase locked state, one of the switches 42-0, 42-1, 42-2, . . . , 42-(m−1) is selected by the selector 8 and is fixed. On the other hand, in a phase unlocked state, the unlocked state detecting circuit 6 detects such a phase unlocked state to pass the output signals of the phase/frequency comparator 1 to the up/down counter 7.

[0026] The unlocked state detecting circuit 6 operates to change the state of the selector 8 using the output signals of the phase/frequency comparator 1. In more detail, when the phase/frequency comparator 1 generates a leading signal UP, the up/down counter 7 is counted up. As a result, when the value of the up/down counter 7 reaches its maximum value, the up/down counter 7 generates an overflow carry signal, so that the selector 8 selects the switch 42-(i+1) provided that the switch 42-i is currently selected. Contrary to this, when the phase/frequency comparator 1 generates a lagging signal DN, the up/down counter 7 is counted down. As a result, when the value of the up/down counter 7 reaches its minimum value, the up/down counter 7 generates an underflow carry signal, so that the selector 8 selects the switch 42-(i−1) provided that the switch 42-i is currently selected.

[0027] Note that the operation speed of the selector 8 is generally higher than the operation speed of the loop filter 3, so that the phase unlocked state can quickly return to a phase locked state. Therefore, as the oscillation frequency of the voltage control oscillator block 4 fluctuates due to the temperature fluctuation or the power supply voltage fluctuation, the unlocked state detecting circuit 6, the up/down counter 7 and the selector 8 are operated to quickly move a phase unlocked state to a phase locked state.

[0028] In the PLL type frequency synthesizer of FIG. 1, however, since the up/down counter 7 is operated by the output signals of the phase/frequency comparator 1, when the precision of the phase/frequency comparator 1 is enhanced, the precision of the up/down counter 7 also has to be enhanced. As a result, the switching from a phase unlocked state to a phase locked state is delayed which increases the lockup time.

[0029] Also, since all of the voltage controlled oscillators 41-0, 41-1, 41-2, . . . , 41-(m−1) are always operated, the power consumption is increased.

[0030] In FIG. 2, which illustrates an embodiment of the wide lock range PLL type frequency synthesizer according to the present invention, the voltage controlled oscillator block 4 and the 1/V frequency divider 5 of FIG. 1 are modified to a voltage controlled oscillator block 4′ and 1/N frequency divider 5′, respectively. Also, the unlocked state detecting circuit 6 of FIG. 1 is deleted. Further, the up/down counter 7 and the selector 8 of FIG. 1 are replaced by a control circuit 7′ and a decoder 8′, respectively. Further, switches 11A, 11B and 11C and a bias voltage source 12 are added to the elements of FIG. 1.

[0031] The voltage control oscillator block 4′ is constructed by a plurality of voltage controlled oscillators 41′-0, 41′-1, 41′-2, . . . , 41′-(m−1) and switches 42′-0, 42′-1, 42′-2, . . . , 42′-(m−1). In this case, the voltage controlled oscillators 41′-0, 41′-1, 41′-2, . . . , 41′-(m−1) have similar oscillation frequency characteristics to those of the voltage controlled oscillators 41-0, 41-1, 41-2, . . . , 41-(m−1) as shown in FIG. 3. However, the switches 42′-0, 42′-1, 42′-2, . . . , 42′-(m−1) do not select output signals of the voltage controlled oscillators 41′-0, 41′-1, 41′-2, . . . , 41′-(m−1), but activate the voltage controlled oscillators 41′-0, 41′-1, 41′-2, . . . , 41′-(m−1), respectively.

[0032] For example, as illustrated in FIG. 4A which illustrates a first example of the voltage controlled oscillator block 4′ of FIG. 2, the voltage controlled oscillator block 4′ is constructed by a fixed inductor L, a variable capacitor C_V controlled by the control voltage V_C, fixed capacitors C₀, C₁, C₂, . . . , C_m−1, and a fixed resistor (−G). The voltage controlled oscillator 41′-0 is formed by the fixed inductor L, the variable capacitor C_V, the fixed capacitor C₀ and the resistor (−G). The voltage controlled oscillator 41′-1 is formed by the fixed inductor L, the variable capacitor C_V, the fixed capacitor C₁ and the resistor (−G). The voltage controlled oscillator 41′-2 is formed by the fixed inductor L, the variable capacitor C_V, the fixed capacitor C₂ and the resistor (−G). Similarly, the voltage controlled oscillator 41′-(m−1) is formed by the fixed inductor L, the variable capacitor C_V, the fixed capacitor C_m−1 and the resistor (−G).

[0033] On the other hand, as illustrated in FIG. 4B, which illustrates a second example of the voltage controlled oscillator block 4′ of FIG. 2, the voltage controlled oscillator block 4′ is constructed by oscillator units OSC₀, OSC₁, OSC₂, . . . , OSC_m, controlled by the control voltage V_C and reference current sources I_ref0, I_ref1, I_ref2, . . . , I_refm−1, connected to the oscillator units OSC₀, OSC₁, OSC₂, . . . , OSC_m−1, respectively. That is, the reference current sources I_ref0, I_ref1, I_ref2, . . . , I_refm−1 are turned ON and OFF by the switches 42′-0, 42′-1, 42′-2, . . . , 42′-(m−1), respectively.

[0034] The 1/N frequency divider 5′ is constructed by a prescaler, i.e., an 1/L frequency divider 51′ where L is a fixed positive integer larger than 1 and a 1/M frequency divider 52′ where M is a variable positive integer supplied from the programmable terminal P. In this case,
N=L·M

[0035] The control circuit 7′ may be constructed by a microcomputer including a central processing unit (CPU), a read-only memory (ROM) for storing programs and constants, a random access memory (RAM) for storing temporary data, and the like.

[0036] The decoder 8′ receives selection data SELD from the control circuit 7′ to generate one selection signal SEL(0), SEL(1), SEL(2), . . . , or SEL(m−1) for selecting the switches 42′-0, 42′-1, 42′-2, . . . , or 42′-(m−1).

[0037] The bias voltage source 12 generates a bias voltage V_B which is a predetermined value such as a center value of the control voltage V_C as shown in FIG. 3. When the bias voltage V_B is applied via the switch 11A to the loop filter 3, the control voltage V_C is equal to the bias voltage V_B.

[0038] In a phase locked state the control circuit 7′ generates no enable signal EN, i.e., EN=“0”, so that the switches 11A, 11B and 11C are activated toward their lower sides. As a result, a phase locked loop is formed by the phase/frequency comparator 1, the charge pump circuit 2, the loop filter 3, the voltage control oscillator block 4′ and the 1/N frequency divider 5′.

[0039] On the other hand, in a phase unlocked state or in an initial state where an optimum value S_opt is set, an enable signal EN is supplied from an enable signal generating circuit (not shown) to the control circuit 7′ which generates a frequency switching signal UPSEL, i.e., UPSEL=“1”, so that the switches 11A, 11B and 11C are activated at their upper sides. As a result, the input signal IN having the frequency f_r is supplied to an interrupt terminal INT1 of the control circuit 7′, and the output signal of the prescaler 51′ having a frequency f_vco/L is supplied to an interrupt terminal INT2 of the control circuit 7′. Thus, the switching operation of the oscillation frequency is carried out by the control circuit 7′ using flowcharts as illustrated in FIGS. 5, 6 and 7.

[0040] The interrupt routine of FIG. 5 is carried out every time each pulse of the input signal IN is supplied to the interrupt terminal INT1 of the control circuit 7′.

[0041] First, at step 501, a counter value R is counted up by +1. Note that, when the frequency switching signal UPSEL is changed as shown in FIG. 8A, the input signal IN(f_r) at the interrupt terminal INT1 is as shown in FIG. 8B, and the counter value R is changed as shown in FIG. 8C.

[0042] Next, at step 502, it is determined whether or not the counter value R is larger than a predetermined value R0. As a result, only when R>R0, does the control proceed to an oscillation frequency switching step 503. Otherwise, the control proceeds directly to step 504. The oscillation frequency switching step 503 will be explained in detail later with reference to FIG. 7.

[0043] The interrupt routine of FIG. 6 is carried out every time each pulse of the output signal of the prescaler 51′ is supplied to the interrupt terminal INT2 of the control circuit 7′.

[0044] First, at step 601, a counter value S is counted up by +1. Note that, when the frequency switching signal UPSEL is changed as shown in FIG. 8B, the output signal f_vco/L of the prescaler 51′ is as shown in FIG. 8D, and the counter value S is changed as shown in FIG. 8E.

[0045] Then, the routine of FIG. 6 is completed by step 602.

[0046] The oscillation frequency switching step 503 of FIG. 5 is explained next with reference to FIG. 7.

[0047] First, at step 701, the counter value S is defined as a final counter value S_f.

[0048] Next, at step 702, it is determined whether or not the final counter value S_f is within an optimum range defined by S_opt−Δ and S_opt+Δ, where S_opt is the optimum value of the final counter value S_f and Δ is a definite positive value. As a result, when S_f<S_opt−Δ, the control proceeds to step 703, while, when S_f>S_opt+Δ, the control proceeds to step 706. Also, when S_opt−Δ≦S_f≦S_opt+Δ, the control proceeds directly to step 712.

[0049] At step 703, the selection data SELD is increased by +1, i.e., SELD←SELD+1, so that the current selection signal SEL(i) is changed to a selection signal SEL(i+1). In this case, the selection data SELD is guarded by its maximum value m−1 using steps 704 and 705.

[0050] At step 706, the selection data SELD is decreased by 1, i.e., SELD←SELD−1, so that the current selection signal SEL(i) is changed to a selection signal SEL(i−1). In this case, the selection data SELD is guarded by its minimum value 0 using steps 707 and 708.

[0051] At steps 709 and 710, the counter values R and S are cleared to prepare for the next processing.

[0052] Then, the routine of FIG. 7 returns by step 711 to step 504 of FIG. 5.

[0053] On the other hand, at step 712, the control circuit 7′ resets the frequency switching signal UPSEL, i.e., UPSEL=“0”.

[0054] Then, the routine of FIG. 7 is completed by step 713.

[0055] Thus, the operations as illustrated in FIGS. 5, 6 and 7 are repeated until the frequency switching signal UPSEL becomes “0”, i.e., a phase locked state is established.

[0056] At steps 703 or 706 of FIG. 7, the selection data SELD is changed by 1; however, the selection data SELD can be changed by another value such as 2, 3, . . .

[0057] A modification of the oscillation frequency switching routine of FIG. 7 is illustrated in FIG. 9. In FIG. 9, the value i is initialized at 0 by an initialization routine (not shown).

[0058] First, at step 901, the counter value S is defined as a final counter value S_f.

[0059] Next, at step 902, an absolute value Δi is calculated by
Δi←|S_f−S_opt|

[0060] where S_opt is an optimum value of the final counter value S_f.

[0061] Next, at step 903, the value i is counted up by +1, i.e.,
i←i+1

[0062] Next, at step 904, it is determined whether or not the value i is beyond its maximum, i.e., whether or not i>m−1 is satisfied. As a result, when i≦m−1, the control proceeds to step 905, while, when i>m−1, the control proceeds to step 909.

[0063] At step 905, the selection data SELD is caused to be i, and at steps 906 and 907, the counter values R and S are cleared, thus preparing for the next processing.

[0064] Then, the routine of FIG. 9 returns by step 908 to step 504 of FIG. 5.

[0065] On the other hand, at step 909, a minimum value MIN is selected from the absolute value Δ0, Δ1, Δ2, . . . , Δ(m−1), and at step 910, the selection data SELD is caused to be MIN. As a result, the decoder 8′ generates a selection signal SEL(MIN), so that the switch 42′-MIN is turned ON and the other switches are turned OFF.

[0066] Next, at step 911, 912, and 913, the counter values R and S and the value i are cleared, thus preparing for the next processing.

[0067] Then, the routine of FIG. 9 is completed by step 914.

[0068] Thus, the operations as illustrated in FIGS. 5, 6 and 9 are also repeated until the frequency switching signal UPSEL becomes “0”.

[0069] In the above-described embodiment, as illustrated in FIG. 3, since the carrier power to noise power (C/N) characteristics of each of the voltage controlled oscillators 41′-1, 41′-1, 41′-2, . . . , 41′-(m−1) depends upon the modulation sensitivity K_V, an optimum modulation sensitivity K_V can be determined by selecting an optimum one of the voltage controlled oscillators. Thus, a lock range of the voltage controlled oscillator block 4′ can be widened without the C/N characteristics.

[0070] As explained hereinabove, according to the present invention, since the up/down counter of the prior art is unnecessary, even when the precision of the phase/frequency comparator is enhanced, the switching from a phase unlocked state to a phase locked state is not delayed to decrease the lockup time. Also, since only one voltage controlled oscillator is activated, the power consumption can be decreased.