Method and structures for measuring gate tunneling leakage parameters of field effect transistors

[0001] The present invention relates to the field of semiconductor transistors; more specifically, it relates to a silicon-on-insulator field effect transistor and a structure and method for measuring gate-tunnel leakage parameters of field effect transistors.

[0002] Silicon-on-insulator (SOI) technology employs a layer of mono-crystalline silicon overlaying an insulation layer on a supporting bulk silicon wafer. Field effect transistors (FETs) are fabricated in the silicon layer. SOI technology makes possible certain performance advantages, such as a reduction in parasitic junction capacitance, useful in the semiconductor industry.

[0003] To accurately model SOI FET behavior, gate tunneling current from the gate to the body of the FET in the channel region must be accurately determined. This current is difficult to measure because construction of body-contacted SOI FETs utilize relatively large areas of non-channel region dielectric which adds parasitic leakage current from the gate to non-channel regions of the FET. The parasitic leakage current can exceed the channel region leakage current, making accurate modeling impossible.

[0004] Therefore, there is a need for a silicon-on-insulator field effect transistor with reduced non-channel gate to body leakage and a structure and method for measuring tunnel leakage current of a silicon-on-insulator field effect transistors.

[0005] The present invention utilizes SOI FETs having both thin and thick dielectric regions under the same gate electrode, the thick dielectric layer disposed adjacent to under the gate electrode over the SOI FET body contact, as tunneling leakage current measurement devices. The thick dielectric layer minimizes parasitic tunneling leakage currents that otherwise interfere with thin dielectric tunneling current measurements from the gate electrode in the channel region of the SOI FET.

[0006] A first aspect of the present invention is a structure comprising: a silicon body formed in a semiconductor substrate; a dielectric layer on a top surface of the silicon body; and a conductive layer on a top surface of the dielectric layer, a first region of the dielectric layer between the conductive layer and the top surface of the silicon body having a first thickness and a second region of the dielectric layer between the conductive layer and the top surface of the silicon body having a second thickness, the second thickness different from the first thickness.

[0007] A second aspect of the present invention is a method of measuring leakage current, comprising: providing a first and a second device, each device comprising: a silicon body formed in a semiconductor substrate; a dielectric layer on a top surface of the silicon body, a first region of the dielectric layer having a first thickness and a second region of the dielectric layer having a second thickness, the first thickness less than the second thickness; a conductive layer on a top surface of the dielectric layer; a dielectric isolation extending from a top surface of the semiconductor substrate into the semiconductor substrate on all sides of the silicon body; a buried dielectric layer in the semiconductor substrate under the silicon body, the dielectric isolation contacting the buried dielectric layer; a first region of the conductive layer extending in a first direction and a second region of the conductive layer extending in a second direction, the second direction perpendicular to the first direction; and the first region of the conductive layer disposed over the first region of the dielectric layer and an adjacent first portion of the second region of the dielectric layer, the second region of the conductive layer disposed over a second portion of the second region of the dielectric layer, the second portion of the second region of the dielectric layer adjacent to the first portion of the second region of the dielectric layer; and performing measurements of current flow between the conductive layer and the silicon body for each of the first and second devices.

[0019] FIG. 1A is a top view of an SOI FET according to first and second embodiments of the present invention. In FIG. 1A, an FET 100 includes a silicon body 105, a “T” shaped conductive layer 110 having a first region 115 and a integral second region 120 perpendicular to first region 115, and a dielectric layer (e.g. a gate dielectric layer), a thin dielectric region 125 (e.g. a thin gate dielectric region) and a thick dielectric region 130 (e.g. a thick gate dielectric region). Thick dielectric region 130 is shown by the dashed lines. Thin and thick dielectric regions 125 and 130 may formed from a single integral dielectric layer, from two separate but abutting dielectric layers or thick region 130 may include a second dielectric layer over an underlying first dielectric layer while thin region 125 just includes the second dielectric layer. First and second source/drains 135 and 140 are formed in body 105 on opposite sides of first region 115 of conductive layer 110. A body contact region 145 is formed in body 105 adjacent to a side 150 of second region 120 of gate 110 away from first region 115 of gate 110. Body 105 is surrounded by trench isolation (TI) 155. A first stud contact 160 contacts gate 110 and a second stud contact 165 contacts body contact region 145 of body 105.

[0020] For an N-channel FET (NFET) device body 105 is doped P− except for first and second source/drain regions 135 and 140 which are doped N+ and body contact region 145 which is doped P+. For a P-channel FET (PFET) device body 105 is doped N− except for first and second source/drain regions 135 and 140 which are doped P+ and body contact region 145 which is doped N+.

[0021] First region 115 of conductive layer 110 has a width W and a length L. Thick dielectric region 130 extends from second region 120 of conductive layer 110 a distance D (e.g. has a width D) under first region 115 of conductive layer 110.

[0022] FIG. 1B is a cross-section through line 1B—1B of FIG. 1A. In FIG. 1B, trench isolation 155 physically contacts a buried oxide layer (BOX) 170. BOX 170 in turn physically contacts a silicon substrate 175. Thus body 105 is electrically isolated from silicon substrate 175 or any adjacent devices. In FIG. 1B, an interlevel dielectric layer 180 is formed over conductive layer 110 and stud first and second contacts 160 and 165 extend through interlevel dielectric layer 180. An optional metal silicide contact 185 is formed between first stud contact 160 and conductive layer 110 and an optional metal silicide contact 190 is formed between second stud contact and body contact region 145. Examples of metal silicides include titanium silicide, tantalum silicide, tungsten silicide, platinum silicide and cobalt silicide.

[0023] Thin dielectric region 125 has a thickness T1 and thick dielectric region 130 has a thickness T2. In one example T1 is between about 0.8 nm and about 1.5 nm. In one example T2 is between about 2 nm and about 3 nm. Thin dielectric region 125 may comprise silicon dioxide, silicon nitride, a high K material, metal oxides, Ta₂O₅, BaTiO₃, HfO₂, ZrO₂, Al₂O₃, metal silicates, HfSi_xO_y, HfSi_xO_yN_z and combinations thereof. Thick dielectric region 130 may also comprise silicon dioxide, silicon nitride, a high K material, metal oxides, Ta₂O₅, BaTiO₃, HfO₂, ZrO₂, Al₂O₃, metal silicates, HfSi_xO_y, HfSi_xO_yN_z and combinations thereof. Thick and thin dielectric regions 125 and 130 may comprise the same or different materials. A high K dielectric material has a relative permittivity above 10.

[0024] There are three tunneling current leakage paths from conductive layer 110 into body 105. The first leakage path (for tunneling leakage current I₁) is from first region 115 of conductive layer 110, through thin dielectric region 125 to body 105. The second leakage path (for tunneling leakage current I₂) is from first region 115 of conductive layer 110, through thick dielectric region 130 to body 105. The third leakage path (for tunneling leakage current I₃) is from second region 120 of conductive layer 110, through thick dielectric region 130 to body 105 and body contact region 145.

[0025] FIG. 5C is a cross-section through line 1C—1C of FIG. 1A. In FIG. 5C, first and second source/drains 135 and 140 are aligned to opposite sidewalls 195 and 200 respectively of first region 115 of conductive layer 110. For clarity, no spacers are illustrated in FIG. 5C (or FIGS. 1A, 1B or 1D), however, the invention is applicable to devices fabricated with spacers. Spacers are thin layers formed on the sidewalls of gate electrodes and source/drains are aligned to the exposed sidewall of the spacer rather than the sidewall of the gate electrode as is well known in the art.

[0026] FIG. 5D is a cross-section through line 1D—1D of FIG. 1A. In FIG. 5D, it should be noted that thick dielectric region 130 does not extend under all of second region 120 of conductive layer 110.

[0027] Returning to FIGS. 1A and 1B, gate tunneling leakage current density J is a function of the dielectric layer material, the dielectric layer material and the voltage across the dielectric layer (for an FET this is VT). In the following discussion reference to both FIGS. 1A and 1B will be helpful. The total gate to body tunneling leakage current I_GB (hereafter gate tunneling leakage) of FET 100 is equal to I₁+I₂+I₃ as shown in FIG. 1B. The tunneling leakage current density of thin dielectric region 125 is, J₁ and of thick dielectric region 130 is J₂. In general, gate tunneling leakage current I is equal to J times the area of the dielectric in a particular region. Therefore, gate tunneling leakage current I₁ is equal to J₁·L(W−D). Gate tunneling leakage 12 is equal toJ₂ ·L·D. Gate tunneling leakage 13 is equal to J₂·A·B. (A is shown in FIG. 1A.) The total gate tunneling leakage of SOI FET 100 is given by:
I_GB=L₁·L(W−D)+J₂·L·D+J₂·A·B  (1)

[0028] When used as a measurement structure, SOI FET 100 is designed so that 13 remains constant, and the relations L−(W−D)>L·D and T2>T1 are chosen to make I₁>I₂.

[0029] FIG. 2 is a top view of an exemplary tunneling gate current measure structure according to the first embodiment of the present invention. In FIG. 2, a test structure 210 includes a first SOI FET 215 and a second SOI FET 220. First SOI FET 215 is similar to SOI FET 100 of FIG. 1A, except first region 115 of conductive layer 110 has a width WA as opposed to a width W in FIG. 1A. Second SOI FET 220 is similar to first SOI FET 215 except first region 115 of conductive layer 110 has a width WB as opposed to a width WA. In the first embodiment of the present invention WA can not be equal to WB, the goal being having two otherwise identical SOI FETs with different thin dielectric areas.

[0030] The total gate tunneling leakage current of SOI FET 215 (assuming the current through second region 120 of conductive layer 110 is negligible as discussed supra in reference to FIGS. 1A and 1B) can be expressed as I_GBA=I_1A+I_2A+I_3A where I_1A=J₁·L(WA−D), I_2A=J₂·L·D and I_3A=J₂·A·B to give:
I_GBA=J₁·L(WA−D)+J₂·L·D+J₂·A·B  (2)

[0031] and the total gate tunneling leakage current of SOI FET 220 can be expressed as I_GBB=I_1B+I_2B+I_3B where I_1B=J₁·L(WB−D), I_2A=J₂·L·D, and I_3A=J₂·A·B to give:
I_GBB=J₁·L(WB−D)+J₂·L·D+J₂·A·B  (3)

• • [0032] and subtracting I_GBA from I_GBB and rearranging gives:
    I_GBA−I_GBB=J₁·L(WA−WB).  (4)

[0033] Since both I_GBA and I_GBB may be measured by applying a voltage across and then measuring a current flowing through stud contacts 160 and 165 and with WA, WB, A and B as known values (design value plus fabrication bias) J₁ can be solved for. With J₁ known, I₁ for any SOI FET having a same thin dielectric layer as thin dielectric region 125 can be calculated. J₂ and I₂ may then be calculated as well. I_GBA and I_GBB are measured at the same voltage. In one example, I_GBA and I_GBB are measured at the threshold voltage (VT) of a conventional (single thickness gate dielectric) SOI FET.

[0034] FIG. 3 is a top view of an exemplary tunneling gate current measure structure according to a second embodiment of the present invention. In FIG. 3, a test structure 225 includes a first SOI FET 230 and a second SOI FET 235. First SOI FET 230 is similar to SOI FET 100 of FIG. 1A, except thick dielectric region 130 extends from second region 120 of conductive layer 110 a distance DA under first region 115 of conductive layer 110 (e.g. a region of thick dielectric region 130 under second region 120 of conductive layer 110 has a width DA) as opposed to a distance D in FIG. 1A. Second SOI FET 235 is similar to first SOI FET 230 except thick dielectric region 130 extends from second region 120 of conductive layer 110 a distance DB (e.g. a region of thick dielectric region 130 under second region 120 of conductive layer 110 has a width DA) under first region 115 of conductive layer 110 as opposed to distance DA. In the second embodiment of the present invention DA can not be equal to DB, the goal being having two otherwise identical SOI FETs with different thin dielectric areas.

[0035] The total gate tunneling leakage current of SOI FET 230 can be expressed as I_GBA=I_1A+I_2A+I_3AI_1A=J₁·L(W−DA), I_2A=J₂·L·Dl , and I_3A=J₂·A·B to give:
I_GBA=J₁·L(W−DA)+J₂·L·DA+J₂·A·B  (5)

• • [0036] and the total gate tunneling leakage current of SOI FET 235 can be expressed as I_GBB=I_1B−I_1B where I_1B=J₁·L(W−DB), I_1B=J₂·L·DB, and I_1A=J₂·A·B, to give:
    I_GBB=J₁−L(W−DB)+J₂·L·DB+J₂·A·B.  (6)

[0037] Since both I_GBA and I_GBB may be measured by applying a voltage across and then measuring a current flowing through stud contacts 160 and 165 and with L, W, DA, and DB, A, B as known values (design value plus fabrication bias) and equations (5) and (6) provide two equations with two unknowns, J₁ and J₂ can be solved for. With, J₁ and J₂ known, I₁ and I₂ for any SOI FET having a same thin dielectric layer as thin dielectric region 125 can be calculated.

[0038] FIG. 4A is a top view of an SOI FET according to third and fourth embodiments of the present invention. In FIG. 4A, an SOI FET 240 is similar to SOI FET of FIG. 1A with the following exceptions:

[0039] SOI FET 240 is essentially symmetrical about a central axis 245 passing through and perpendicular to both body 105 and a conductive layer 110A is “H” shaped. First region 115 of conductive layer 110A is positioned between integral second and third regions 120 that perpendicular to first region 115. Thin dielectric region 125 is positioned between first and second thick dielectric layers 130 (defined by the dashed lines). First and second body contact regions 145 are formed in body 105 adjacent to a sides 150 of first and second regions 120 of gate 110A. A first stud contact 160 contacts gate 110 and a first and second stud contacts 165 contact body contact regions 145. First region 115 of conductive layer 110A has a width W and a length L. Thick dielectric region 130 extends from first and second regions 120 of conductive layer 110A distances D under first region 115 of conductive layer 110A.

[0040] When used a s measurement structure, SOI FET 240 is designed so that 13 remains constant, and L-(W−D)>L·D and T2>T1 making I₁>I₂.

[0041] FIG. 4B is a cross-section through line 4B—4B of FIG. 4A. In FIG. 4B, there are five tunneling current leakage paths from conductive layer 110A into body 105. The first leakage path (for tunneling leakage current I₁) is from first region 115 of conductive layer 110, through thin dielectric region 125 to body 105. The second and third leakage paths (for tunneling leakage currents 12) are from first region 115 of conductive layer 110, through first and second thick dielectric layers 130 to body 105. The fourth and fifth leakage path (for tunneling leakage currents 13) are from second and third regions 120 of conductive layer 110, through respective first and second thick dielectric layers 130 to body 105 and respective body contact regions 145.

[0042] FIG. 5 is a top view of an exemplary tunneling gate current measure structure according to the third embodiment of the present invention. In FIG. 5, a test structure 250 includes a first SOI FET 255 and a second SOI FET 260. First SOI FET 250 is similar to SOI FET 240 of FIG. 4A, except first region 115 of conductive layer 110 has a width WA as opposed to a width W in FIG. 4A. Second SOI FET 260 is similar to first SOI FET 255 except first region 115 of conductive layer 110A has a width WB as opposed to a width WA. In the third embodiment of the present invention WA can not be equal to WB, the goal being having two otherwise identical SOI FETs with different thin dielectric areas.

[0043] Equation (1) I_GBA−I_GBB=J₁L(WA−WB) derived for the first embodiment of the present invention is applicable to the third embodiment of the present invention. The third embodiment of the present invention eliminates errors in gate tunneling leakage induced at the edge of body 105 under gate 110 of FIG. 2 by eliminating that edge.

[0044] Again both I_GBA and I_GBB are measured by applying a voltage across and then measuring a current flowing through stud contacts 160 and 165 and in one example, I_GBA and I_GBB are measured at the threshold voltage (VT) of a conventional (single thickness gate dielectric) SOI FET.

[0045] FIG. 6 is a top view of an exemplary tunneling gate current measure structure according to the fourth embodiment of the present invention. In FIG. 6, a test structure 265 includes a first SOI FET 270 and a second SOI FET 275. First SOI FET 270 is similar to SOI FET 240 of FIG. 4A, except thick dielectric layers 130 extend from second and third regions 120 of conductive layer 110A distances DA under either side of first region 115 of conductive layer 110A as opposed to a distance D in FIG. 4A. Second SOI FET 275 is similar to first SOI FET 270 except thick dielectric region 130 extends from second and third regions 120 of conductive layer 110A distances DB under either side of first 115 of conductive layer 110A as opposed to distance DA. In the fourth embodiment of the present invention DA can not be equal to DB, the goal being having two otherwise identical SOI FETs with different thin dielectric areas.

[0046] The following two equations in two unknowns, J₁ and J₂ may be derived in a similar manner to equations (5) and (6) supra:
I_GBA=J₁·L(W−DA)+2·J₂·L·DA+2·J₂·A·B  (7)
I_GBA=J₁·L(W−DB)+2·J₂·L·DB+2·J₂·A·B.  (8)

[0047] Again both I_GBA and I_GBB are measured by applying a voltage across and then measuring a current flowing through stud contacts 160 and 165 and in one example, I_GBA and I_GBB are measured at the threshold voltage (VT) of a conventional (single thickness gate dielectric) SOI FET.

[0048] The fourth embodiment of the present invention eliminates errors in gate tunneling leakage induced at the edge of body 105 under gate 110 of FIG. 3 by eliminating that edge.

[0049] Thus, the present invention provides a silicon-on-insulator field effect transistor with reduced non-channel gate to body leakage and a structure and method for measuring tunnel leakage current of silicon-on-insulator field effect transistors.

[0050] The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.