Method for fabricating a recessed channel field effect transistor (FET) device

[0001] 1. Field of the Invention

[0002] The present invention relates generally to methods for fabricating field effect transistor devices. More particularly, the present invention relates to methods for fabricating field effect transistor devices with enhanced performance.

[0003] 2. Description of the Related Art

[0004] Common in the semiconductor product art is the fabrication and use of field effect transistor devices. Field effect transistor devices are readily fabricated and scaled with either or both polarities. They are typically employed as switching devices within both logic semiconductor products and memory semiconductor products.

[0005] Field effect transistor devices are thus common and generally essential in the semiconductor product art. However, they are nonetheless not entirely without problems.

[0006] In that regard, as semiconductor product integration levels have increased and field effect transistor device dimensions have decreased, it has become increasingly difficult to fabricate field effect transistor devices with enhanced performance. Performance within advanced field effect transistor devices of reduced dimensions may be compromised by effects such as short channel effects and source-drain resistance effects.

[0007] It is thus desirable to fabricate field effect transistor devices with enhanced performance. It is towards the foregoing object that the present invention is directed.

[0008] Various field effect transistor devices having desirable properties, and methods for fabrication thereof, have been disclosed within the semiconductor product art.

[0009] Included but not limiting among the field effect transistor devices and methods are those disclosed within: (1) Huang, in U.S. Pat. No. 5,814,544 (a field effect transistor device with a recessed channel region formed employing a thermal oxidation method); and (2) Yu, in U.S. Pat. No. 6,225,173 (a field effect transistor device with a recessed channel formed employing a planarizing method).

[0010] The teachings of each of the foregoing references are incorporated herein fully by reference.

[0011] Additional methods for forming field effect transistor devices with enhanced performance are desirable.

[0012] It is towards the foregoing object that the present invention is directed.

[0013] A first object of the invention is to provide a method for forming a field effect transistor device.

[0014] A second object of the invention is to provide a method in accord with the first object of the invention, wherein the field effect transistor device is formed with enhanced performance.

[0015] In accord with the objects of the invention, the invention provides a method for forming a recessed channel field effect transistor device.

[0016] The method first provides a semiconductor substrate. A first sacrificial layer is formed upon the semiconductor substrate and a pair of source/drain regions is implanted into the semiconductor substrate while employing the first sacrificial layer as a mask. A pair of second sacrificial layers is formed overlying the pair of source/drain regions and adjoining the first sacrificial layer. The first sacrificial layer is then removed to form an aperture which exposes the semiconductor substrate. The semiconductor substrate exposed within the aperture is etched to form an elongated aperture. A pair of sacrificial sidewall spacer layers is formed upon the sidewalls of the elongated aperture and a gate dielectric layer is formed at the bottom of the elongated aperture. A gate electrode is then formed filling the remainder of the elongated aperture. The pair of second sacrificial layers and the pair of sacrificial sidewall spacer layers is then removed. Finally, a pair of lightly doped extension regions is then implanted into the semiconductor substrate while employing the gate electrode as a mask.

[0017] The invention provides a method for forming a field effect transistor device with enhanced performance.

[0018] The invention realizes the foregoing object by forming the field effect transistor device with a recessed channel region and with lightly doped extension regions formed after source/drain regions.

[0021] The present invention provides a method for forming a field effect transistor device with enhanced performance.

[0022] The invention realizes the foregoing object by forming the field effect transistor device with a recessed channel region and with lightly doped extension regions formed after source/drain regions.

[0023] The preferred embodiment of the invention illustrates the invention within the context of forming a field effect transistor device within a silicon-on-insulator semiconductor substrate. However, the present invention is not intended to be so limited. Rather, the invention may be employed for forming field effect transistor devices within semiconductor substrates including but not limited to silicon semiconductor substrates and silicon-germanium alloy semiconductor substrates, whether bulk semiconductor substrates or silicon (or silicon-germanium) on-insulator semiconductor substrates. In addition, the present invention may be employed for forming field effect transistor devices of either or both polarities within a semiconductor substrate.

[0024] FIG. 1 to FIG. 11 show a series of schematic cross-sectional diagrams illustrating the results of progressive stages in forming a field effect transistor device in accord with a preferred embodiment of the invention.

[0025] FIG. 1 illustrates a silicon-on-insulator semiconductor substrate prior to forming thereupon the field effect transistor device.

[0026] Within FIG. 1, the silicon-on-insulator semiconductor substrate comprises a semiconductor substrate 10 having formed thereupon a buried oxide layer 12. In turn, formed upon the buried oxide layer 12 is a pair of isolation regions 16a and 16b which bound an active silicon layer 14 which is also formed upon the buried oxide layer 12.

[0027] As noted above, the invention is not limited to a silicon-on-insulator semiconductor substrate as illustrated in FIG. 1. Alternatively, the invention may employ a bulk silicon or silicon-germanium alloy substrate, a silicon-germanium on-insulator substrate or an otherwise laminated semiconductor substrate which provides a surface layer formed of a semiconductor material upon which may be formed a field effect transistor in accord with the invention.

[0028] Within FIG. 1, the buried oxide layer 12 is typically a silicon oxide layer formed to a thickness of from about 1500 to about 4000 angstroms. In addition, the active silicon layer 14 is formed to a thickness of from about 1 to about 2 microns and a linewidth of from about 0.3 to about 1 micron. Finally, the pair of isolation regions 16a and 16b is typically formed of a silicon oxide material.

[0029] FIG. 2 illustrates the results of further processing of the silicon-on-insulator semiconductor substrate of FIG. 1.

[0030] FIG. 2 illustrates a pad dielectric layer 18 formed nominally centered upon the active silicon layer 14 and a dummy gate 20 formed aligned upon the pad dielectric layer 18. Together, the pad dielectric layer 18 and the dummy gate 20 form a first sacrificial layer.

[0031] Within the invention, the pad dielectric layer 18 is optional, but generally formed of a silicon oxynitride dielectric material formed to a thickness of from about 100 to about 300 angstroms. In addition, the dummy gate 20 is typically formed of a silicon oxide material, although other materials, which need not necessarily be dielectric materials, may also be employed. Typically, the dummy gate 20 is formed to a thickness of from about 4000 to about 6000 angstroms. Each of the pad dielectric layer 18 and the dummy gate 20 is formed to a linewidth of from about 0.1 to about 0.3 microns.

[0032] FIG. 3 illustrates the results of further processing of the silicon-on-insulator semiconductor substrate of FIG. 2.

[0033] FIG. 3 illustrates the results implanting a dose of first implanting dopant ions 23 into the active silicon layer 14 while employing the pad dielectric layer 18 and the dummy gate 20 as a mask. The ion implantation forms a pair of source/drain regions 22a and 22b which include a thickness of the active silicon layer 14.

[0034] Within the invention, the dose of first implanting dopant ions 23 may be of either polarity as is appropriate for forming the pair of source/drain regions 22a and 22b, and of a dosage and energy as is otherwise conventional for forming the pair of source/drain regions 22a and 22b. Typically, the pair of source/drain regions 22a and 22b is formed with a dopant concentration of from about 1E15 to about 1E18 dopant atoms per cubic centimeter. In addition, the pair of source/drain regions 22a and 22b is typically thermally annealed at a temperature of from about 900 to about 1100 degrees centigrade for a time period of from about 1 to about 2 hours such as to repair ion implant damage within the active silicon layer 14.

[0035] FIG. 4 illustrates the results of further processing of the silicon-on-insulator semiconductor substrate of FIG. 3.

[0036] FIG. 4 illustrates a pair of patterned planarized second sacrificial layers 24a and 24b formed adjoining a pair of opposite sidewalls of the dummy gate 20 and the pad dielectric layer 18.

[0037] The pair of patterned planarized second sacrificial layers 24a and 24b is typically formed of a silicon nitride material when the dummy gate 20 is formed of a silicon oxide material and the pad dielectric layer 18 is formed of a silicon oxynitride material. Other materials combinations may, however, be employed providing adequate etch selectivity of the dummy gate 20 and the pad dielectric layer 18 with respect to the pair of patterned planarized sacrificial layers 24a and 24b. Typically, the pair of patterned planarized second sacrificial layers 24a and 24b is formed incident to planarizing a blanket layer while employing a planarizing method such as a reactive ion etch (RIE) etchback planarizing method or (more preferably) a chemical mechanical polish (CMP) planarizing method. Either of the foregoing planarizing methods may employ the dummy gate 20 as a planarizing stop layer.

[0038] FIG. 5 illustrates the results of further processing of the silicon-on-insulator semiconductor substrate of FIG. 4.

[0039] FIG. 5 illustrates the results of stripping the dummy gate 20 and the pad dielectric layer 18 from interposed between the pair of patterned planarized second sacrificial layers 24a and 24b to form an aperture 25 exposing at its bottom a portion of the active silicon layer 14.

[0040] The dummy gate 20 and the pad dielectric layer 18 may be stripped selectively with respect to the pair of patterned planarized second sacrificial layers 24a and 24b while employing stripping methods and materials as are otherwise generally conventional in the semiconductor product fabrication art. Typically, such stripping methods and materials may employ, but are not limited to, hydrofluoric acid containing stripping methods and materials when the dummy gate 20 is formed of a silicon oxide material, the optional pad dielectric layer 18 is formed of a silicon oxynitride material and the pair of patterned planarized second sacrificial layers 24a and 24b is formed of a silicon nitride material.

[0041] FIG. 6 illustrates the results of further processing of the silicon-on-insulator semiconductor substrate of FIG. 5.

[0042] FIG. 6 illustrates the results of etching the active silicon layer 14 exposed at the bottom of the aperture 25 defined by the pair of patterned planarized second sacrificial layers 24a and 24b with an etching plasma 26, to form an etched active silicon layer 14′ exposed at the bottom of an elongated aperture 25′.

[0043] The etching plasma 26 will typically employ an etchant gas composition appropriate to the silicon material from which is formed the active silicon layer 14. Such an etchant gas composition will typically comprise a chlorine containing etchant gas. Typically, the active silicon layer 14 is etched to a depth of from about 500 to about 2000 angstroms when forming the etched active silicon layer 14′. The exposed surface of the etched active silicon layer 14′ may also be reodxidized to form a sacrificial oxide layer of from about 10 to about 50 angstroms thereupon, and thus provide enhanced surface conditioning of the etched active silicon layer 14′. As is understood by a person skilled in the art, the etch depth when forming the etched active silicon layer 14′ may be adjusted to provide an optimal thickness of a channel region of a field effect transistor device formed incident to further processing the silicon-on-insulator semiconductor substrate whose schematic cross-sectional diagram is illustrated in FIG. 6. Such an optimal thickness may be employed to control field effect transistor device parameters, such as threshold voltage. In addition, the etch depth provides a recessed channel region within the field effect transistor device, in conjunction with a pair of raised source/drain regions 22a and 22b within the field effect transistor device.

[0044] FIG. 7 shows the results of further processing of the silicon-on-insulator semiconductor substrate of FIG. 6.

[0045] FIG. 7 first shows a pair of sacrificial sidewall spacer layers 28a and 28b formed into the elongated aperture 25′ and adjoining a pair of sidewalls of the pair of patterned planarized second sacrificial layers 24a and 24b. The pair of sacrificial sidewall spacer layers 28a and 28b may be formed employing a blanket conformal layer deposition and anisotropic etching method as is conventional in the semiconductor product fabrication art. Typically, the pair of sacrificial sidewall spacer layers 24a and 24b is formed of a silicon oxide material.

[0046] FIG. 7 also shows a gate dielectric layer 30 formed upon the etched active silicon layer 14′ exposed at the base of the elongated aperture 25′. The gate dielectric layer 30 is typically formed of a silicon oxide dielectric material formed incident to thermal oxidation of the etched active silicon layer 14′. Typically, the gate dielectric layer 30 is formed to a thickness of from about 10 to about 70 angstroms.

[0047] FIG. 8 illustrates the results of further processing of the silicon-on-insulator semiconductor substrate of FIG. 7.

[0048] FIG. 8 illustrates a blanket gate electrode material layer 32 formed upon exposed portions of the pair of patterned planarized second sacrificial layers 24a and 24b, the pair of sacrificial sidewall spacer layers 28a and 28b and the gate dielectric layer 30, while completely filling the elongated aperture 25′.

[0049] The blanket gate electrode material layer 32 is typically formed of a doped polysilicon material (having a dopant concentration of from about 1E19 to about 1E22 dopant atoms per cubic centimeter) formed to an appropriate thickness such as to completely fill the elongated aperture 25′.

[0050] FIG. 9 illustrates the results of further processing of the silicon-on-insulator semiconductor substrate of FIG. 8.

[0051] FIG. 9 illustrates the results of planarizing the pair of patterned planarized second sacrificial layers 24a and 24b, the pair of sacrificial sidewall spacer layers 28a and 28b and the blanket gate electrode material layer 32 to form a pair of patterned twice planarized second sacrificial layers 24a′ and 24b′, a pair of truncated sacrificial sidewall spacer layers 28a′ and 28b′ and a gate electrode 32′.

[0052] The foregoing planarizing is typically effected while employing a chemical mechanical polish planarizing method.

[0053] FIG. 10 illustrates the results of further processing of the silicon-on-insulator semiconductor substrate of FIG. 9.

[0054] In a first instance, FIG. 10 illustrates the results of stripping the pair of patterned twice planarized second sacrificial layers 24a′ and 24b′ and the pair of truncated sacrificial sidewall spacer layers 28a′ and 28b′ from adjacent or adjoining the gate electrode 32′.

[0055] The pair of twice planarized second sacrificial spacer layers 24a′ and 24b′ when formed of a silicon nitride material may typically be stripped while employing a phosphoric acid etchant solution at elevated temperature. In addition, the pair of truncated sacrificial sidewall spacer layers 28a′ and 28b′ when formed of a silicon oxide material may be stripped while employing a hydrofluoric acid etchant solution.

[0056] Finally, FIG. 10 also illustrates a pair of lightly doped extension regions 34a and 34b formed within the recess within the etched active silicon layer 14′, and bridging to the pair of source/drain regions 22a and 22b. The pair of lightly doped extension regions 34a and 34b is formed while employing a dose of second implanting dopant ions 35 in conjunction with the gate electrode 32′ as a mask.

[0057] The dose of second implanting dopant ions 35 is of the same polarity as the dose of first implanting dopant ions 23, but provided at a considerably lower dose of and energy such as to provide the pair of lightly doped extensions regions 34a and 34b of dopant concentration from about 1E12 to about 1E14 dopant atoms per cubic centimeter.

[0058] FIG. 11 illustrates the results of further processing of the silicon-on-insulator semiconductor substrate of FIG. 10.

[0059] FIG. 11 illustrates a pair of laminated spacer layers 36a and 36b formed adjoining a pair of sidewalls of the gate electrode 32′.

[0060] The pair of laminated spacer layers 36a and 36b is typically formed of a silicon nitride material laminated to a silicon oxide material as a lower layer.

[0061] FIG. 11 also shows a series of metal silicide layers 38a, 38b and 38c formed upon the pair of source/drain regions 22a and 22b and the gate electrode 32′.

[0062] The series of metal silicide layers 38a, 38b and 38c may be formed from any of several metals as are conventional in the semiconductor fabrication art, including but not limited to titanium, tungsten, platinum, vanadium and molybdenum metals. Typically, the series of metal silicide layers 38a, 38b and 38c is each formed to a thickness of from about 200 to about 1000 angstroms, while employing a salicide method.

[0063] FIG. 11 illustrates a field effect transistor device formed within a silicon-on-insulator semiconductor substrate. The field effect transistor device is formed with enhanced performance.

[0064] The field effect transistor device realizes the foregoing object by fabricating the field effect transistor device with a recessed channel region, and with a pair of lightly doped drain extension regions formed after a pair of source/drain regions.

[0065] Within the field effect transistor device of the present invention, the recessed channel region is formed in a self-aligned fashion with respect to the pair of source/drain regions such as to provide reduced source/drain resistance within the field effect transistor device. The self-aligned method also provides for forming a gate electrode of less than minimal photolithographically resolvable linewidth and for forming a gate electrode after source/drain region formation thus avoiding ion implant damage to the gate electrode. In addition, the pair of raised source/drain regions (and the resultant pair of embedded laminated spacers as 36a and 36b as illustrated in FIG. 11) provide for inhibited metal silicide layer incursion and bridging. Further, by providing a method wherein the pair of source/drain regions 22a and 22b is formed and thermally annealed prior to forming the pair of lightly doped extension regions 34a and 34b, short channel effect performance is generally improved.

[0066] The preferred embodiment of the invention is illustrative of the invention rather than limiting of the invention. Revisions and modifications may be made to methods, materials, structures and dimensions in accord with the preferred embodiment of the invention while still providing a method for forming a field effect transistor device in accord with the invention, further in accord with the accompanying claims.