Sigma-delta modulator with PWM output

[0001] The present invention relates to the improvement of a generated arbitrary waveform by using a sigma-delta modulator and subsequent pulse width modulation. The improved generated arbitrary waveform can for example be used as a stimulus signal for an electronic device to be tested.

[0002] Integrated Circuits (IC) generally need to be tested to assure proper operation. This—in particular—is required during IC development and manufacturing. In the latter case, the ICs are usually tested before final application. During test, the IC, as Device Under Test (DUT), is exposed to various types of stimulus signals, and its responses are measured, processed and usually compared to an expected response of a good device. Automated Test Equipments (ATE) usually perform these tasks according to a device-specific test program. Examples for ATE are the Agilent 83000 and 93000 families of Semiconductor Test Systems of Agilent Technologies as disclosed e.g. under http://www.ate.agilent.com/ste/products/intelligent test/SOC test/SOC Tech Oview.shtml. Details of those families are also disclosed e.g. in EP-A-859318, EP-A-864977, EP-A-886214, EP-A-882991, EP-A-1092983, U.S. Pat. No. 5,499,248, U.S. Pat. No. 5,453,995.

[0003] Arbitrary Waveform Generators (AWG) are used to provide stimulus signals for the DUT. High OverSampling Ratio (OSR), which could be applied in view of ATE with high bit rates, causes jitter-induced noise due to increased number of transitions per time. Thus, the full capability of ATE cannot be exhausted.

[0004] It is an object of the invention to provide an improved generated arbitrary waveform. The object is solved as defined by the independent claims. Preferred embodiments are defined by the dependent claims.

[0005] According to embodiments of the present invention, the high timing resolution of a high frequency ATE bit rate can be exploited without increasing the number of transitions. By introducing a minimum pulse width during pulse width modulation the data dependent jitter is reduced. Preferably, the minimum pulse width is pre-determinable and can be adapted to the specific circumstances. Even an automatic adaptation of the minimum pulse width to the specific circumstances is possible, e.g. an automatic adaptation to the data dependent jitter permissible or to the boundary conditions of the ATE.

[0006] Preferably a series of numbers is inputted to said sigma-delta modulator as a software version of said desired improved generated arbitrary waveform having a predetermined frequency. For providing said series of numbers an Arbitrary Waveform Generator (AWG) can be used. The sigma-delta modulator is operated at a higher frequency than the frequency of said series of numbers inputted which is the frequency fawg of the Arbitrary Waveform Generator. The ratio of the operation frequency of the sigma-delta modulator and the frequency of the signal at the input of the signal-delta modulator comprises OSR as a factor. Preferably, the sigma-delta modulation is software based.

[0007] Preferably, also the pulse width modulation can be software based and being operated at the same or at a higher frequency fbit than the operation frequency of the sigma-delta modulator. The bit stream resulting from the pulse width modulation is filtered, e.g. by a low-pass filter, resulting in an improved generated arbitrary waveform as hardware output signal having the same frequency as the series of numbers at the input of the sigma-delta modulator.

[0008] In a preferred embodiment a multi-bit sigma-delta modulation is used with a predetermined number of bit levels to obtain the same noise shaping with a lower OSR, thus reducing the jitter impact.

[0009] In a preferred embodiment pulse width modulation is used for digital-to-analog conversion of the multi-level codes of the multi-bit sigma-delta modulator without increasing the number of transitions. Accordingly, increase of clock jitter due to high OSR is avoided. Since multi-bit sigma-delta modulators have better stability, the order of the sigma-delta modulator can be increased to achieve better noise-shaping with the same OSR, or the same noise-shaping with a lower OSR, thus reducing the impact of clock jitter.

[0010] Although a pulse width equal to zero is possible according to embodiments of the present invention, in a preferred embodiment a minimum pulse width is guaranteed by the pulse width modulation in order to reduce the effect of unequal rise times and fall times. Preferably the bits for establishing said minimum pulse width are introduced as leading bits and/or trailing bits in each bit stream segment resulting from said pulse width modulation.

[0011] By reversing the bit sequence of every second bit stream segment of said bit stream resulting from said pulse width modulation, as a kind of mirroring odd and even bit streams segments, the number of transitions and thus the date dependent jitter is reduced, e.g. by 50%. Preferably, reversing the bit sequence is established by software.

[0012] In a preferred embodiment pulse width modulation comprises a number of output channels to be added by analog addition, e.g. by an analog 50 Ω adder. By adding multiple channels more levels in the software modulator can be used in order to provide a better noise shaping at a given maximum bit rate of the ATE.

[0013] The ratio of the bit frequency fbit resulting from said analog addition of said output channels and the operating frequency fSD of said sigma-delta modulator is equal to said minimum pulse width plus the integer above the ratio of said number of bit levels minus 1 and said number of output channels.

[0014] Preferably bit assignment is rotated between the output channels in order to eliminate effect of unbalanced signal levels of the output channels.

[0015] The present invention also relates to a method for testing an electronic device as Device Under Test (DUT) incorporating the above described method for providing an improved generated arbitrary waveform, which is used as a stimulus signal for the DUT.

[0016] Furthermore, the present invention relates to a software program or product for executing either the method for providing an improved generated arbitrary waveform and/or the method for testing an electronic device when running on a date processing system such as a computer. Preferably, the program or product is stored on a data carrier.

[0017] Furthermore, the present invention relates to a system for providing an improved generated arbitrary waveform comprising a sigma-delta modulator, preferably a multi-bit sigma-delta modulator, for modulating a series of numbers that is or can be regarded as a software version of said improved generated arbitrary waveform. Furthermore, the system comprises a pulse width modulator for pulse width modulation with a minimum pulse width of the output signal of said sigma-delta modulator.

[0025] FIG. 1 shows a block diagram of a system 10 for providing an improved generated arbitrary waveform. The system 10 comprises a sigma-delta modulator 12, a pulse width modulator 14, and a low pass filter 16. The system 10 receives at its input 18 a series of numbers that can be regarded as a software version or representation of said improved generated arbitrary waveform desired on the output 20 of the system 10. The signal frequency fawg at the input 18 is the same as at the output 20. The signal at the input 18 can be regarded as the generated arbitrary waveform to be improved, and the signal at the output 20 can be regarded as the improved generated arbitrary waveform.

[0026] The sigma-delta modulator 12 comprises a signal transfer block 22 having a signal transfer function H(z) in the order L. An allocation block 24 provides the output signal 26 of the sigma-delta modulator 12 having a predetermined number nlev of bit levels. The output signal is also coupled back to the input of the signal transfer block 22 by a Digital/Analog Converter DAC 28. The sigma-delta modulator 12 is operated at a frequency being twice the frequency of the signal at the input 18 and being multiplied by the OverSampling Ratio OSR.

[0027] The ratio of the operating frequency fbit of the pulse width modulator 14 and the operating frequency fSD of the sigma-delta modulator 12 is equal to the number nlev of bit levels minus 1 and plus the minimum pulse width pwmin. During the pulse width modulation, the minimum pulse width is guaranteed as can be seen from the figures described below. The output signal 30 of the pulse width modulator 14 is conducted to the filter 16, which is an RC circuit providing low pass filtering. The filter 16 is operated at continuous time.

[0028] FIG. 2 shows a signal diagram representing the signal transfer from the output signal 26 of the sigma-delta modulator 12 being the input signal of the pulse width modulator 14, and the output signal 30 of the pulse width modulator 14. In the shown example, the output signal 26 comprises seven bit levels with CODE 0 to 6. Each code is converted by the pulse width modulation into a bit stream with odd and even bit stream segments 36, 38. Supplemental leading bits 32 and trailing bits 34 are introduced in each bit stream segment 36, 38 guaranteeing a minimum pulse width.

[0029] By reversing the bit sequence of every second bit stream segment 38 of the bit stream resulting from the pulse width modulation, i.e. reversing the bit sequence of every EVEN bit segment 38, the number of transitions is reduced as being obvious from FIG. 2.

[0030] FIG. 3 shows two signal diagrams, the upper one in the original form and the lower one with reversed bit sequence for every second bit stream segment 38. In the upper diagram in any bit stream segment 36, 38 there are two transitions 40. By reversing the bit sequence of every second bit stream segment 38 as indicated with broken line in the lower signal diagram, the number of transitions is reduced to one for each bit stream segment 36, 38 and thus by 50%.

[0031] FIG. 4 shows a second embodiment for the pulse width modulator 114. As input signal the output signal 26 of the sigma-delta modulator 12 shown in FIG. 1 is used having a signal frequency fFD. The output of the pulse width modulator 114 provides multiple channels B1 to Bnch which are added by an analog adder 42, e.g. a 50 Ω adder, resulting in an output signal 30 having a bit frequency fbit as defined by the equation shown in FIG. 5.

[0032] Accordingly the ratio of the bit frequency fbit/fFD is equal to the integer above the ratio of the number of levels nlev provided by the allocation block 24 shown in FIG. 1 minus 1 and the number nch of channels B1 to Bnch of the pulse width modulator 114 shown in FIG. 4 plus the minimum pulse width pwmin. Adding multiple channels allow to use more levels in the software pulse width modulator 114 at a given maximum bit rate fbit of the ATE resulting in a better noise shaping.

[0033] FIG. 6 shows signal diagrams for the pulse width modulator 114 shown in FIG. 4. In the example of FIG. 6 the number of levels nlev of the allocation block 24 is 10, the number of channels nch of the pulse width modulator 114 is 3, and the minimum pulse width pwmin is 2. Accordingly two supplemental bits are introduced as leading bits 32 and trailing bits 34 respectively. Bit assignment is rotated in order to eliminate the effect of unbalanced levels. In the first bit stream segment 44 the order of bit assignment is channel B1-B2-B3-B1. In the second bit stream segment 46 the order of bit assignment is channel B2-B3-B1-B2-B3-B1-B2. In the third bit stream segment 48 the order of bit assignment is channel B3-B1.