Method and device for a state-dependent control of the transient behavior of semiconductor power switches

[0001] This invention relates to the field of power electronics. It relates to a method and a device for the regulation of the transient behavior of semiconductor power switches in accordance to the preamble of the independent claims.

[0002] Such a method is disclosed in the article of H. Rüedi et al., “Dynamic Gate Controller (DGC)—A new IGBT Gate Unit for High Current/High Voltage Modules”, PCIM'95 (Official Proceedings of the International Power Conversion), p. 241–149, Nuremberg, Germany, 1995. An IGBT is driven by a dynamic gate controller (DGC) in such a manner that specified constant values of the time derivative of the collector-emitter voltage over the IGBT (voltage gradient dv_CE/dt) and of the current through the free-wheeling diode or the IGBT (collector current gradient di_C/dt) are maintained during switching independently of the load current and the DC bus voltage. For this purpose, signals proportional to the voltage gradient and current gradient are fed back to the input of the gate driver. The voltage over the emitter—auxiliary-emitter inductance of an IGBT-module or the signal from a field probe at a power terminal of an IGBT-module serves as signal for the current gradient di_C/dt.

[0003] Even though the DGC allows to avoid a complicated application with a snubber network, the DGC is poorly suited for IGBTs arranged in series. Although the current gradient di_C/dt for every IGBT module in series is identical, differences between the individual transfer factors of the IGBT regulation loops lead to deviations from the ideal gate current. These offsets lead to a different charging of the equivalent output capacitances of the IGBTs and therefore to an uncontrolled increase of the individual collector-emitter voltages of single IGBTs. Hence, IGBTs arranged in series cannot be synchronously switched with sufficient accuracy. In that case, the serial collector-emitter voltages can then only be symmetrized by reducing the switch-on time at the expense of higher transient losses.

[0004] Furthermore the DGC controller is not suited for reliably regulating the strongly non-linear behavior of IGBTs, in particular during fast switch-on, because of the constant and in part contradicting reference values for the voltage and current gradients. In particular, the transition behavior of both control circuits for the current gradient di_C/dt and the voltage gradient dv_CE/dt remains uncontrolled. In an extreme case the controllability of the IGBTs is lost due to an oscillating transition behavior during the switching operation.

[0005] A further problem results from the trend to reduce the emitter-auxiliary-emitter inductance. The high signal amplification required for this leads to strongly limited regulation dynamics. Due to the finite slew rate of the control loops, among other things, the problem of the insufficient controllability in the range of transition is made worse.

[0006] In EP 0 797 301 a turn-on operation of a IGBT is controlled by a gate current being used as manipulated variable for regulating a gate. This relies on there being a quadratic dependence between the gate voltage above the threshold voltage and the load current. An IGBT control loop with a feedback of state variables, which characterize the state of the IGBT on the power side, to the gate driver is not provided. A control loop on the gate side only is, how-ever, insufficient for controlling the non-linear switching behavior of IGBTs.

[0007] It is an object of the invention to disclose a method and a device for actively regulating the transient switching operation of semiconductor power switches that is especially suited for synchronization of the switching behavior of serial semiconductor power switches.

[0008] In e first aspect of the invention a regulation method is suggested for transient switching operations of a semiconductor power switch, wherein the switch comprises at least one control terminal or one gate controlled by a gate driver, a first power terminal or collector and a second power terminal or emitter, wherein a free-wheeling diode is arranged in series to the semiconductor power switch, wherein furthermore, at least one actual value is determined or approximated for at least one primary state variable of the semiconductor power switch and is fed back to the gate driver, and the actual value and a reference value of the state variable are used as input values for generating a manipulated variable for the control terminal in such a manner that a collector current gradient of the semiconductor power switch is regulated in a phase A, in which the free-wheeling diode is in a conducting state, and a collector-emitter voltage gradient of the semiconductor power switch is regulated in a phase B, in which the free-wheeling diode is in a non-conducting state. Both gradients can be directly regulated values of the control loop or are indirectly regulated by other regulated values. The primary state variable serves to characterize the state, in particular the electric and/or thermal loads, of the semiconductor power switch in the control loop. It can be e.g. a collector voltage, a collector current or a gradient of these values. Values derived from state values are, in this context, considered themselves to be state values again.

[0009] The application, according to the invention, of a two phase model of the charge state of the serial free-wheeling diode for separating the di_c/dt regulation from a dv_CE/dt-regulation of the semiconductor power switch allows, for the first time, to realize a reliable control of the strongly non-linear transient behavior of semiconductor power switches. The method can be applied to complete and partial turn-on and turn-off processes. In phase A, the main transient of the collector current i_C is regulated by means of the di_C/dt control loop in such a manner that the state of charge and therefore the conductivity of the free-wheeling diode can be switched with optimum speed, and, at the same time, an overshoot behavior of the collector current can be limited while switching on the semiconductor power switch. In phase B, the main transient of the collector-emitter voltage v_CE is regulated by means of the dv_CE/dt control loop in such a manner that the semiconductor power switch can be turned off or turned on with optimum dynamics and, at the same time, an overshoot of the collector voltage can be limited while turning off the semiconductor power switch. Controllability is maintained all the times during the transients because a uncontrolled transition behavior of both control loops and a resultant oscillatory behavior are effectively prevented.

[0010] In first embodiments the phases are passed in order A-B during a turn-on operation of the semiconductor power switch and in order B-A during a turn-off operation, wherein the semiconductor power switch is controlled in each case in a regulatable state in a preceding phase A0 and B0, respectively, namely, for example, in phase A0, by means of increasing a gate-emitter voltage over a threshold value v_T or in, phase B0, by means of decreasing a gate-emitter voltage below a threshold value v_T+i_C/g_m with g_m=transconductance of the semiconductor power switch.

[0011] In a second embodiment, in phase A, the absolute value of collector current gradient |diC/dt| and, in phase B, the absolute value of the collector-emitter voltage gradient |dv_CE/dt| are temporarily increased, and they are decreased towards the end of the phases. Thus, the transient switching operation can be accelerated and the power dissipation of the switch can, in addition, be reduced.

[0012] In a third embodiment, for improving the dynamics and stability of the method of regulation for at least a secondary state variable of the semiconductor switch, such as a gate voltage, a gate current, its gradient or a collector-emitter voltage gradient, an actual value is determined or approximated and fed back to an output stage of the amplifier of the gate driver. By such a comprehensive state regulation with feedback to one or more amplifier stages, resonant frequencies of the feedback loop are shifted, oscillations are damped, and, all in all, the frequency response of the method of regulation can correspondingly be modified in advantageous manner.

[0013] In a fourth embodiment, measured actual values (measured values) and/or approximated actual values (approximate values) are determined for at least one primary and/or secondary state variable and/or a value derived therefrom. The approximation can e.g. be carried out by means of differentiation or averaging of measured values, by extrapolation for determining approximate values of future actual values, by transformation from indirect measured values e.g. by means of predetermined correction or calibration factors or by combination of such steps. For example, a collector current can be determined from the gate emitter voltage or from a time integral of the gate current or the induction voltage over an emitter inductance. The gate emitter voltage can be determined from a time integral of the gate current.

[0014] In fifth embodiments a time dependent function for the reference value is provided and/or actual values of the state variable are repeatedly measured during the transient switching process. Furthermore, a modified reference value for at least one phase A, B, A0, B0 of the current or the next switching process can be provided based on a calculated or estimated control loop offset between a reference value and an actual value of a state variable. In this manner the regulation process can be carried out with high accuracy and be adapted to the current state of the system.

[0015] In sixth embodiments a collector voltage v_c, namely e.g. a collector-emitter voltage v_CE or, in approximation, a collector gate voltage v_CG is chosen as, preferably sole, primary state variable. Preferably, in a corresponding function v_CE^ref(t), v_CG^ref(t) of the reference voltage, the phase A is implemented by an amplitude step proportional to the collector current gradient di_c/dt to be controlled, and the phase B by immediately providing the collector-emitter voltage gradient dv_CE/dt to be controlled. With such a v_CE control loop excellent dynamics and stability of the control loop can be achieved with comparatively simple means. The v_CE control loop is, in addition, especially well suited for the voltage symmetrization of semiconductor power switches arranged in series. Variants are: at least a double value of an average gradient and/or a total change of amplitude of the reference value function of the voltage in phase B as compared to phase A, adaptation of an amplitude change in phase A as a function of the load current, of a shape of a time dependence of the collector current, of a temperature of the free-wheeling diode or of a break-off behavior of a current or a voltage at the free-wheeling diode, several amplitude steps in phase A for shortening the switching process, different collector-emitter voltage gradients in phase B for limiting the required gate current, implementation of a phase A0 by providing a preceding small amplitude step of the reference voltage function, initialization of a phase B0 by specifying a minimum value of the reference voltage function, determination, in phase A, of an improved modified reference voltage function by an adaptive modification of the reference voltage controlled by an actual value feedback or, where applicable, by a fixed modification of the reference value during the switch-on and/or switch-off process, and determination of offsets in the control loop at least for the collector voltage and the collector voltage gradient and application of the maximum control loop offset for generating the manipulated variable.

[0016] In seventh embodiments, a transition time between the phases A and B is detected in particular by means of a main criterion and/or an additional criterion for validating the main criterion for a measured or an approximated state variable.

[0017] In an eight embodiment, a control loop parameter of the method for regulation, such as a control loop gain, limits for the manipulated value, feedback factors or a feedback function, is adapted in discrete steps or continuously depending on measured or approximated values of a state variable or depending on an expected ideal manipulated variable. For example, a control loop gain and/or limits for the manipulated variable are chosen to be large in the edge regions of phases A and/or B and, where applicable, to be maximum in the phases A0 or B0, and are decreased upon transition between the phases A, B, i.e. at large collector-emitter voltages and large collector currents. Hence, by adapting the control loop gain the reduced transconductance in the switched-off state and in the increased gate-collector or Miller capacity of the semiconductor power switch in the switched-on state are compensated and the dynamics and accuracy of the control loop are optimized by a reduction of the control loop gain during the transient switching process. For this, the control loop gain function is varied in steps for large control loop gain and comparatively continuously for small control loop gain. By an adaptation of the upper and lower limits of the manipulated variable in the same sense, oscillations in the manipulated variable due to resonant oscillations of the nonlinear control loop are limited and therewith the reliability of the regulation process is further increased. For an expected ideal manipulated variable a time dependence of the absolute value of a gate current (|i_G|) can be set to be proportional to t_A^−0.5 in the phase A and proportionally to t_B² in the phase B, wherein t_A, t_B=time values for the phases A, B.

[0018] In a ninth embodiment an actual value of a primary state variable is kept within a tolerance interval given by an upper and a lower reference value function. Preferably, a phase C is passed during switch-off after the phase A, where a semiconductor power switch is partially and temporarily switched-on upon each increase of the collector voltage above a predetermined maximum value by means of a pulsed gate current until the collector voltage has dropped to a minimum voltage that can be specified.

[0019] In tenth embodiments a v_CE regulation is applied to a switch-on or switch-off process of an arrangement of i=1 . . . n semiconductor power switches in series by v_CE regulating at least n−1 switches. During a switch-on process, the phases A0 can be introduced individually, in particular asynchronously, for each switch in order to bring all semiconductor power switches into the range where regulation is possible. In the phase A, a main part of the total voltage drop induced over the leakage inductance of the series arrangement can be attributed to a single semiconductor power switch in order to achieve a steep initial rise of the collector current gradient. Alternatively, the switch-on times for phase A can be substantially synchronized by detecting an increase of an actual value of the collector current gradient di_c/dt and/or the collector current i_c above a limiting value. In each case a substantially common transition time between the phases A and B for all semiconductor power switches is guaranteed because of the vCE closed loop control.

[0020] In an eleventh embodiment, in an inverter with serial semiconductor power switches and free-wheeling diodes arranged parallel thereto, a transient switch-on process of the first bridge arm is regulated according to the invention while, in the second bridge arm, a switch-off transient of the free-wheeling diodes is regulated by partially switching on parallel semiconductor power switches in such a way that the anode-cathode voltages and/or power dissipations of the free-wheeling diodes are symmetrized.

[0021] In a second aspect the invention relates to a gate driver designed for carrying out the method according to the invention. Such a gate driver comprises measuring means and processing means for at least a primary state variable of a semiconductor power switch, a reference value generator, an actual value—reference value comparator and an amplifier for generating a manipulated variable for a control terminal or a gate of the semiconductor power switch, wherein the reference value generator comprises a first generator for generating a first reference value by means of which, in a phase A where a free-wheeling diode in series to the semiconductor power switch is in a conducting state, the manipulated variable is adapted for regulating a collector current gradient di_c/dt of the semiconductor power switch, wherein the reference value generator further comprises a second generator for generating a second reference value, by means of which, in a phase B where the free-wheeling diode is in a non-conducting state, the manipulated variable is adapted for regulating a collector-emitter voltage gradient dv_CE/dt of the semiconductor power switch.

[0022] In a first embodiment, the measuring means and processing means comprise a signal detector and a actual value generator for a collector voltage and a collector current gradient of the semiconductor power switch. Furthermore, the first generator for generating a collector voltage amplitude variation and the second generator for generating a collector voltage current gradient are switched off. Preferably, the reference voltage generator comprises means for calculating all reference values from a common reference voltage function that can be specified.

[0023] In a second embodiment the actual value generator comprises a differentiator for generating a gradient of actual values and an adder for the weighted addition of actual values and actual value gradients. Alternatively, the actual value generator and the reference value generator comprise an extrema value generator for determining a maximum of an absolute value of standardized control loop offsets of the collector voltage and of the collector voltage gradient.

[0024] In a third embodiment, the gate driver comprises detection means for determining a transition time between the phases A and B, which in particular comprise a signal detector and a calculator unit with a threshold value switch for a main criterion as well as, optionally, a generator for an additional criterion and a validation device.

[0025] In a forth embodiment, the gate driver additionally has a signal detector for feeding back actual values of at least one secondary state variable to at least one amplifier output stage.

[0026] In a fifth embodiment, the gate driver comprises means for adapting control loop parameters, such as a control loop gain, an upper bound or a lower bound for the manipulated variable or a feedback coefficient or a feedback function for a signal detection of a primary and/or secondary state variable. In particular the means are designed for an approximate control of an absolute gate current in the phase A proportional to t_A^−0.5 and in the phase B proportional to t_b² and in the range of a transition time of the phases A and B for control by a minimum.

[0027] In a sixth embodiment, the amplifier is a current amplifier for a gate current manipulated variable. The amplifier can have several output stages.

[0028] In seventh embodiments, the gate driver comprises an amplifier with at least one output stage for generating a controlled variable for a control terminal or a gate of a semiconductor power switch, wherein the output stage comprises at least one linearly adjustable first current source for generating small gate currents with a small regulation control loop offset and a large regulation stability as well as at least one second current source that is adjustable in non-linear or step wise manner and that can be added in parallel for generating large gate currents with high regulation dynamics. By means of this structure of the current source it is possible to generate strong gate currents with extremely short rise times at the beginning and the end of the switching operation and small gate currents with exact regulatability during the transition in an intermediate range between the phases A and B for the control terminal of the semiconductor power switch.

[0029] In following eighth embodiments, the first and the second current source, respectively, are divided into several logical and/or physical first and second partitions. Furthermore, the gate driver comprises a structure control for activating the first and/or second current sources and/or of partitions of the first and/or second current source. The structure control is in particular designed such that (i) in the course of the first phase B or A of a switching process the second partitions can be switched-off successively, and then the first partitions can be regulated down and/or switched of successively, and that (ii) in the course of the second phase B or A of a switching process the first partitions can be regulated up and/or on switched on successively and then the second partitions can be switched on successively. In addition, all partitions can be activated in phases A0 and B0. The structure control can also be designed such that a pulsed gate current can be generated by switching on and switching off second and/or first partitions.

[0030] In a ninth embodiment, the first current source comprises a linear cascade of current mirror arrangements of transistors. In addition to this, the second current source can comprise a mirror arrangement of transistors, wherein a gate of an output transistor of the mirror arrangement can be switched between two voltages. Furthermore, an actual value-reference value comparator for quickly driving the current sources can comprise a current mirror arrangement of transistors, and, in particular, can be divided into third partitions of several current mirror arrangements.

[0031] Furthermore, the invention relates to a semiconductor power switch or an arrangement of semiconductor power switches with at least one gate driver according to the invention. IGBTs, MOSFETs and/or BJTs are suited as semiconductor power switches. The arrangement can be an arrangement in series, an arrangement in parallel or a serial arrangement of arrangements in parallel, and in particular it can be a switch module, in particular an inverter, for traction, high voltage DC transmission, radio transmitters, inductive heating or inductive welding.

[0032] Further embodiments, advantages and applications of the invention result from the dependent claims as well as from the now following description with reference to the figures.

[0046] In the figures, similar parts are provided with the same reference numerals.

[0047] FIG. 1 shows a semiconductor power switch S1, such as an IGBT module, for switching a load circuit 2, which is modeled by a DC voltage source V_DC, a current source for the load current i_L and an inductance L_S. A free-wheeling diode D_S is in series to the semiconductor power switch S₁. A control terminal G of the switch S₁ is fed by a gate driver GT with a gate current i_G for driving the power branch collector C-emitter E. The simplified model for the internal set up of the switch S₁ comprises a gate input inductance L_G, a gate resistor R_g and an auxiliary gate g, a collector inductance L_C and an auxiliary collector c, an auxiliary collector auxiliary gate or Miller capacitance C_π, an emitter inductance L_e and an auxiliary emitter e as well as an auxiliary gate auxiliary emitter capacitance C_π. The voltages are typically characterized by indices designating the reference points. In short, the voltages v_CE, v_ce, v_CG, v_cg or e.g. also v_Ce, V_cE, v_Cg, v_cG can be designated as collector voltages v_C, and the v_GE, v_ge or e.g. also v_Ge, v_gE as gate voltage v_G. v_Le is the inductance voltage over the emitter inductance L_e. For the collector current i_C the relation i_C=g_m·v_ge hold true, wherein g_m=transconductance of the switch S₁.

[0048] FIG. 2 shows an example of a two phase regulation according to the invention for a switch-on and switch-off process of the switch S₁. When switching on, a step Δv_CE, 104 or a more or less steep gradient 102 for the reference value v_CE^ref or a reference value function v_CE^ref(t) for the collector-emitter voltage v_CE are specified. Due to the equation
Δv_CE=V_DC−v_CE≈L_s*di_C/dt  (G1)
which can be derived in approximation, a collector voltage gradient dv_C/dt proportional to the amplitude change Δv_CE is induced by the inductance L_S. Hence, the current gradient di_C/dt through the power terminals C, E caused by the sweeping behavior of the free-wheeling diode in phase A is indirectly regulated via the voltage v_CE between the power terminals C, E. At the end of phase A, the “reverse recovery” behavior of the diode D_S leads to a self passivation of the collector current transient. As soon as the edge zones of the diode D_S are swept free from carriers, the diode D_S can build up a reverse voltage, Δv_CE increases and the collector-emitter voltage v_CE falls below the reference value V_CE^ref. Then, the phase B can be introduced, during which the gradient of the collector-emitter voltage dv_C^ref/dt is controlled by specifying a reference value dv_c^ref/dt or a reference value function dv_C^ref(t)/dt. During switch-off, the phase B and then the phase A are passed in analog manner.

[0049] It is also possible to directly specify separate reference values di_C^ref/dt and dv_CE^ref/dt or reference value functions di_C^ref(t)/dt and dv_CE^ref(t)/dt for the gradients of the collector current di_c/dt and the collector-emitter voltage dv_CE/dt. In any case, the gradients can only be controlled indirectly through a manipulated variable value for the gate G. Suited manipulated values are a gate current i_G or a gate voltage v_G. i_G or v_G or an approximation for i_G or v_G can be used for a feedback into the control loop, wherein the approximation can e.g. be gained by differentiation, integration, short time averaging, estimation, or similar, from time dependent values of i_G, v_G or other state variables of the switch S₁. In addition, in the two-phase model for switching processes according to the invention, a closed control loop is implemented by determining or approximating at least one actual value of a primary state variable, in particular of the collector voltage v_C, of the collector current i_C or a of value derived therefrom, such as a gradient, and by feeding it to the gate driver G_T. From the control offset between the actual value (also called regulation value, “plant output”, “output” or “process variable”) and the reference value (also called guidance value or “reference variable”), the manipulated variable (also called “plant input) is determined.

[0050] FIG. 3 shows the actual gate current requirement i_G(t) for implementing the phases A and B for a switch-on process. Shown are, at the top, the collector-emitter voltage reference function v_CE^ref(t), the actual collector-emitter voltage function v_CE(t) and the actual collector current function i_c(t) as well as, at the bottom, the gate current i_G(t) and the actual function of the emitter induction voltage v_Le(t) proportional to the collector current gradient, wherein, according to a simplified model for the behavior of an IGBT switch S₁, the non-linearities of the transconductance g_m as a function of the gate emitter voltage V_ge and the Miller capacitance C_μ as a function of the gate emitter voltage v_CE are approximated by the equations
g_m=di_C/dv_ge=T*(V_ge−v_T) for v_ce>v_ge−v_T  (G2)
C_μ=const*V_CE^−0.5  (G3)
wherein T=transconductance parameter, v_T gate threshold voltage for controllability of the IGBT S₁ and const=a constant. The transconductance g_m is, for large values of v_ge−v_T (e.g. several Volts) sublinear to v_ge−v_T.

[0051] First, by specifying a collector voltage step Δv_CE, 104, the gate current i_G is driven to a maximum. As soon as the controllability of the IGBT S₁ has been reached, phase A is introduced by the fact that v_CE (t) starts to decrease and i_c(t) starts to increase. The start of phase A can easily be detected by an increase of the absolute value of the emitter inductance voltage V_Le(T). As soon as the control loop offset v_CE(t)−v_CE^ref(t) becomes small, the gate current i_G(t) is regulated down. It can be shown that an ideal gate current in phase A decreases in its absolute value nearly proportionally to t_A^−0.5, wherein t_A=a time variable for phase A, and approximately t_A=0 can be used at the start of phase A. Close to the maximum value of the collector current i_c(t) there is a range 200 of the transition time t₁ between phases A and B. There, the collector current gradient di_C/dt cannot be maintained anymore because the edge zones of the free-wheeling diode D_S are substantially swept clean. The regulation of the voltage gradient is started, the absolute value of the emitter inductance voltage v_Le(t) decreases and the absolute value of the gate current |i_G| is controlled by a minimum. Its rebound occurs ideally approximately proportionally to t_b², wherein t_B=a time variable for the phase B and approximately t_B=0 can be used at the start of phase B. More or less strong deviations of the actual time dependence of the gate current i_G(t) can occur due to the actual, fed back time dependence of a primary state variable (e.g. of i_c(t)) or due to the dynamics of the control loop.

[0052] Hence, the invention implements, for the first time, a complete closed-loop control of the switch-on and switch-off process of a semiconductor power switch S₁, in particular by taking into account its strongly non-linear transconductance g_m and Miller capacitance C_μ and the strongly non-linear discharge behavior of the edge zones of the free-wheeling diode D_S. By means of the 2-phase regulation, the main transient of the collector current i_c(t) is regulated in phase A with di_c/dt as regulated value, and the main transient of the collector voltage v_c(t) in phase B with dv_CE/dt as regulated variable.

[0053] FIG. 4 shows a simple arrangement for driving the transition behavior of the control loops in the phases A and B for the case of a regulation of v_CE according to FIGS. 2 and 3. Actual values for the change of amplitude Δv_CE and the gradient dv_CE/dt of the collector voltage v_C are coupled out over a resistor and capacitors R_fb, C_fb and C_fb, and compared to the corresponding reference values Δv_ce^ref and dv_CE^ref/dt in difference generators 6. The closed loop control offsets are normalized and the offset with the larger absolute value is fed by a maximum value generator 12 in dependence of a switching instruction as input value to a current amplifier 7 for generating the gate current i_G. Evidently, a minimum value generator, each input of which is connected to a sum of a signed control loop offset with a switching instruction voltage 8 of higher voltage with opposite sign, is equivalent to the maximum value generator 12. In this sense, 12 generally denotes an extrema value generator. As, in phase A, by specifying the amplitude step Δv_CE^ref, the control loop off-set Δv_CE−Δv_CE^ref dominates, and, in phase B, by specifying a collector voltage gradient dv_CE^ref/dt that is steeper than the actual value, or of a corresponding collector voltage step, the control loop offset dv_CE/dt−dv_CE^ref dominates, the desired quantity is regulated in this way and a controlled transition between phase A and phase B is guaranteed.

[0054] A particularly simple control loop with feedback of the collector voltage vCE and the collector voltage gradient dv_CE/dt can be implemented by weighted summation instead of using a maximum value generator 12. For the actual value x_m(t) and the reference value x_ref(t) of the combined state variables and for the gate current i_G, the following equations are valid:
x_m(t)=c₁*v_CE(t)+c₂*dv_CE(t)/dt and  (G4)
x_ref(t)=c₁*v_CE^ref(t)+c₂*dv_CE^ref(t)/dt and  (G5)
i_G(t)=k_p*(x_m(t)−x_ref(t)),  (G6)
wherein k_p=control loop gain. In a further embodiment, the feedback factor c₁ can be set to zero, such that the collector voltage gradient dv_CE/dt is regulated directly. In this way devices can be dispensed with in the power circuit. To increase the stability of this embodiment, an additional integrator can be introduced into the control loop. The integration should be prevented or reduced during the switching process in phases A0 and B0 in order to improve the dynamics.

[0055] In the control loop process according to the invention, a transition time t₁, t₂ can also be determined between the phases A and B. For this purpose, in particular a main criterion, and, where applicable, an auxiliary criterion for validating the main criterion, are detected and used for the active introduction of the second phase B in a switch-on process. One or more of the following inequalities are especially suited as a main criterion:

• [0056] |V_AK|>ε_AK, wherein V_AK=a voltage over the free-wheeling diode D_S and ε_AK=a first threshold value that can be specified;
• [0057] |di_c/dt|<ε_diC, in particular |v_Le|/L_e<ε_diC, wherein ε_diC=a second threshold value that can be specified, wherein, in particular given a subsequent violation of this main criterion (e.g. by oscillations 300 in FIG. 9), a detection of the transition time t₁, t₂ is not revoked;
• [0058] |Δv_C|>ε_vC, wherein ε_vC=a third threshold value that can be specified;
• [0059] |dv_c/dt|>ε_dvC, wherein ε_dvCE=a fourth threshold value that can be specified;
• [0060] |i_G|<ε_iG, wherein ε_iG=a firth threshold value that can be specified;
• [0061] |dv_G/dt|<ε_dvG, wherein dv_G/dt=a gradient of the gate voltage and ε_dvG=a sixth threshold value that can be specified,
• [0062] |v_G|<|v_Gmax|−ε_vGmax, wherein v_Gmax=a maximum value of the gate voltage and ε_vGmax=a seventh threshold value that can be specified; and/or
• [0063] t₁>t_M or t₂>t_M, wherein t_M=a maximum duration from the start of the switching process, and/or from a detectable change of state variables v_c, dv_c/dt, i_c, di_c/dt, i_G, v_G, di_G/dt, dv_G/dt, in particular as soon as |Δv_C|>ε_vC·ε₁ holds true with ε₁<1.

[0064] A faster determination or approximation of the voltage v_AK over the free-wheeling diode D_S is possible according an equation V_AK=−δv_CE+V_AKf+K·V_Le, wherein V_Le and a flow voltage V_AKf of the free-wheeling diode D_S in a phase A0 preceding phase A are measured or estimated. δv_CE designates a change of amplitude of the collector-emitter voltage in phase A as compared to phase A0 and K a proportionality factor. In particular, K=−(L_σ−L_C)/L_e applies, wherein L_σ=L_C+L_e+L_S=total inductance of the load circuit 2, L_C=collector inductance, or K is a proportionality factor that can be specified according to an estimated value for V_AK (e.g. 0V<V_AK<4V).

[0065] One or more of the following inequalities are especially suited as a additional criterion:

• [0066] |V_G|>ε_vG with ε_vG>v_T, wherein ε_vG=a eighth threshold value that can be specified;
• [0067] |i_C|>ε_iC, wherein ε_iC=a ninth threshold value that can be specified, and/or
• [0068] t₁>t_m or t₂>t_m, wherein t_m=a minimum time duration from the start of the switching process.

[0069] Advantageously, the transition time is detected with an accuracy of better than 10%, preferably 4%, particularly preferably 2%, as compared to the duration of phase A.

[0070] FIG. 5 shows that, for a switch-on process, a phase A0 for achieving controllability of the collector current transient as a function of the gate current i_G can be implemented through the small amplitude step 101 in the reference voltage value function v_CE^ref(t). Furthermore, the phase A can be accelerated by specifying first a large amplitude step 103, and, in the course of phase A, an oppositely directed amplitude step 105 in v_CE^ref(t). Analogously, in phase B, a temporarily increased or maximum voltage gradient 106 and, at the end of phase B, a reduced voltage gradient 107 can be used. In general, the time dependence of the reference voltage value function v_CE^ref(t) is best specified by a piece-wise linear or trapezoidal function. Following phase B, a gate current i_G(t) can be regulated in a phase B0 in such a manner that, in the phase B of the subsequent switch-off process, the controllability, i.e. a gate voltage V_GE<V_T+i_C/g_m with v_T=threshold voltage, of the collector-emitter voltage gradient dv_CE/dt by means of the gate current i_G is guaranteed.

[0071] Examples for modifications of the reference value function v_CE^ref(t) are shown in FIG. 6 for a switch-on process and in FIG. 2 for a switch-off process. During switch-on (FIG. 6), a control loop offset v_CE(t)−v_CE^ref(t) can be detected and corrected by specifying a modified reference voltage value function v_C^ref′(t)=v_c^ref(t)+ΔΔv_CE, hence, in the present embodiment, by means of an additional small amplitude step ΔΔv_CE. For detecting of the control loop off-set, the actual value of the collector current gradient di_c/dt can e.g. be determined by measuring the collector current i_c at at least two times t₁₀ and t₁₁ and be compared to a reference value di_C^ref/dt. During switch-off (FIG. 2), 109 designates the desired stationary reference value for v_CE. In phase A, an amplitude step Δv_CE, 104 would have to be specified in such a manner that a voltage value 108 is always larger than the stationary reference value 109 in order to control the induction voltage over L_S. Furthermore, however, an overshoot of the collector-emitter voltage v_CE can be prevented by temporarily specifying an amplitude step Δv_CE, 104 that is decreased by a correction value ΔΔv_CE. 108 as a modified reference value v_CE^ref,. In this way, in particular the voltage value 108 can be below the stationary reference value 109.

[0072] FIG. 7 shows a tolerance interval regulation by means of the collector voltage vC as a primary state variable. Here, a tolerance interval is specified by specifying a maximum value v_Cmax and a minimum value v_Cmin for v_C, and an actual value of v_C is kept within the tolerance interval v_Cmax, V_Cmin preferably by means of a pulsed manipulated signal i_G, v_G. In particular, a gate voltage pulse v_G>v_T is generated by means of a positive and a subsequent, delayed negative current pulse i_G(t). The duration of the gate voltage pulse v_G>v_T is adapted by means of the delay of the negative voltage pulse i_G(t) in such a way that the collector voltage v_C falls to a specifiable value within the tolerance interval v_Cmax, v_Cmin.

[0073] FIGS. 8 and 9 show an advantageous application of the v_CE control loop in a serial arrangement with, as an example, two semiconductor power switches S₁, S₂. Here, collector voltages v_C1 and v_C2, in particular v_CE1 and v_CE2, over each semiconductor power switch S₁, S₂ are regulated as described above. A synchronization of the phases A0 is not required. As shown in FIG. 8, a time delay Δt and/or different reference voltage steps Δv_CE1>Δv_CE2 can be specified in order to assign a major part of the total voltage drop Δv_CE1+Δv_CE2 induced over the stray capacitance of the serial arrangement to a single semiconductor power switch S₂. In this way an exactly defined, steep initial rise of the collector current transient i_C(t) is achieved. After the time delay Δt the remaining semiconductor power switches S₂ are switched on, which increases the gradient of the collector current di_C/dt. By means of the reference voltage steps Δv_CE1, Δv_CE2, the time and amplitude of which can be specified individually, a desired distribution or symmetrization of thermal dissipation losses can be also achieved for the for the semiconductor power switches S₁, S₂.

[0074] FIG. 9 shows an example for synchronizing the phases A after an asynchronous start of the phase A or, where applicable, the phase A0. The gate current time dependencies i_G2(t) and i_G1(t) required for the vCE closed loop controls are shown until the start of phase B. The semiconductor power switch S₂ driven by a time delayed voltage step Δv_CE2 experiences first an overshoot of the collector voltage v_CE2(t). As soon as all control loop offsets decrease or the controllability for all semiconductor power switches S₁, S₂ has been achieved, the collector current i_C(t) starts to increase and phase A is started for all semiconductor power switches S₁, S₂ without further synchronization effort. In the case of preceding phases A0, phase A can be introduced actively for all semiconductor power switches S₁ as soon as the collector current i_C or the collector current gradient di_C/dt exceeds a specifiable threshold value. The collector current i_C can e.g. be determined from a time integral of the induction voltage v_Le over the emitter inductance L_e. The collector current gradient can e.g. be determined by measuring the collector current i_C at different times t₁₂, t₁₃ and by calculating the gradient di_C/dt.

[0075] FIG. 10 shows, for a half bridge of an inverter, a first bridge arm with semiconductor power switches S₃, S₄ and parallel diodes D_p3 and D_p4 and a second bridge arm in simplified representation with only a single switch S₁. The regulation method according to the invention, and in particular the v_CE closed loop control, is applied to S₁. Further-more, in the simultaneous switch-off process of the second bridge arm, anode-cathode voltages V_AK3, V_AK4 and/or power dissipations of the free-wheeling diodes D_p3, D_p4 of the second bridge arm can at least be partially limited, and in particular symmetrized, by identifying at least one free-wheeling diode D_p4 with an excessive anode-cathode voltage gradient dv_AK4/dt and by temporarily and/or partially closing, in a control loop operation, the corresponding parallel semiconductor power switch S₄ according to the regulation method. According to FIG. 10, v_C3=v_AK3, v_C3=v_AK3 and v_C=v_C3+v_C4 applies. In particular, the control loop operation is started as soon as phase B is detected in the regulation method. In the control loop operation, a manipulated signal i_G, v_G can be specified in such a way that an absolute value of the collector voltage gradient |dv_C4/dt| of the corresponding semiconductor power switch S₄ in the second bridge arm does not exceed a limiting value ε_dv. Preferably, ε_dv=N/(n*(1+E)) applies, with N=an absolute value of an expected value of the collector voltage gradient |dv_C/dt| of the first bridge arm, n=a number of the free-wheeling diodes D_p3, D_p4 of the second bridge arm and E=(dv_C/dt−dv_C^ref/dt)/dv_C^ref/dt a standardized offset of the control loop operation. The control loop operation must not be applied to all free-wheeling diodes DP3, DP4 of the second bridge arm simultaneously in order to avoid large transversal currents in a bridge arm. For example, the activation of the semiconductor power switch S₃ belonging to the slowest diode D_p3 can be prevented. The slowest diode D_p3 can e.g. be recognized by the highest anode-cathode voltage V_AK3 or collector-emitter voltage v_CE3 of the corresponding switch S₃ immediately after the end of the switch-off transient. Further-more, it is desirable that, for a fast switch-on capability of the semiconductor power switch S₄ to be activated in the second bridge arm, an average value of its transconductance g_m larger than zero is maintained.

[0076] The big advantage of the control loop operation can be seen from FIG. 10, lower part. The switch S₄ is closed partially, such that a small collector correction current i_k4(t) flows through S₄. This increases the emitter voltage v_E4 of S₄ by approximately 100 V and, therefore, a more symmetric distribution of the collector voltage v_C in the second bridge arm is achieved. In the shown embodiment, the collector correction current i_k3(t) through S₃ is zero and the corresponding emitter voltage v_E3 remains unchanged.

[0077] FIG. 11 shows an example for a gate driver GT for carrying out the regulation method according to the invention. The gate driver GT comprises a signal detector 9 and an actual value generator 3, which is connected thereto, for a primary state variable v_c, dv_c/dt, i_C, id_C/dt, a reference value generator 4, an actual value—reference value comparator 6 and an amplifier 7 for generating a manipulated variable i_G, v_G the gate G. The reference value generator 4 comprises a first generator 41 for generating a first reference value v_C^ref for regulating a collector current gradient di_c/dt in phase A and a second generator 42 for generating a second reference value dv_C^ref/dt for regulating a collector-emitter current gradient dv_CE/dt in phase B. In the following, preferred embodiments are listed.

[0078] The reference value generator 3 can comprise a differentiator 31 for generating the gradient of actual values and an adder 32 for the weighted addition of actual values and actual value gradients. Alternatively, the current value generator 3 and the reference value generator 4 can comprise an extrema value generator 12 for determining a maximum of the absolute values of the standardized control loop offsets for the phases A and B according to FIG. 4.

[0079] Furthermore, the gate driver GT can comprise means 5, 10 for the detection of the transition time t₁, t₂ between the phases A and B. The detection means 5, 10 typically comprise a signal detector 10 and a calculator unit 5, wherein the calculator unit 5 comprises a threshold value switch 51 for a main criterion and, optionally, a generator 52 for an additional criterion. In a validation device 53 the main criterion is checked by means of the additional criterion and approved or rejected. 51a and 52a designate signal lines for the main criterion and the additional criterion.

[0080] FIG. 12 shows a gate driver GT with a signal detector 9 for feeding back actual values of at least one secondary state variable i_G, v_G, di_G/dt, dv_C/dt to at least one output stage 7a, 7b of the amplifier 7. As an example, signals proportional to the collector-emitter voltage v_CE, to the collector-emitter voltage gradient α₃·dv_CE/dt, to the gate-emitter voltage v_GE, to the gate current α₁·i_G and/or to the gate current gradient α·di_G/dt are fed back, wherein α₁, α₂ and α₃ are factors of proportionality. Here, as well as elsewhere and in the claims, quantities that make reference to collector C, emitter E or gate G of the semiconductor power switch S₁–S₄, can generally also be understood as referring to auxiliary collector c, auxiliary emitter e or auxiliary gate g. C₇ designates the output capacity of the amplifier 7, R a measurement resistor, L a measurement inductance and C_fb an extraction capacity. The feedback factors c₁–c₅ serve for weighing the fed-back actual values of the primary and/or secondary state variables v_C, dv_C/dt, i_C, di_C/dt, i_G, v_G, di_G/dt, dvG/dt. They can also be replaced by feedback functions f. The actual values are added in devices 91, 92, 93. Furthermore, the gate driver GT can comprise means for adapting a control loop gain k_p or upper limit S_M or a lower limit S_m for the manipulated variable.

[0081] FIG. 13 shows a gate driver GT with the already described extrema value generator 12 and an output stage of the amplifier 7 partitioned according to the invention. It comprises a linearly controllable first current source L with partial amplifiers or first partitions L1–L4 connected in parallel and a second current source N, which can be added in parallel and be controlled in non-linear or stepwise manner, with partial amplifiers or second partitions N1–N4 arranged in parallel. Furthermore, a structure control 11 for activating the current sources L, N and the partitions L1–L4 and N1–N4 is provided. The partitions L1–L4, N1–N4 can be implemented in logical or physical manner. By using weighted partitions L1–L4, N1–N4, the transfer function of the semiconductor power switch S1–S4 can be compensated for, and at the same time the bandwidth of the gate driver can be maximized.

[0082] FIG. 14 shows the manner of operation of the partitioned amplifier 7. Shown is an ideal gate current time-dependence i_G(t) and a gate current time-dependence according to the invention approximated with partitions L1–L3, N1–N3. The ideal gate current i_G(t) is e.g., as discussed above, proportional to t_A^−0.5 in phase A and proportional to t_B² in phase B. In phase A0, the partitions L1–L2 and N1–N3 are active. At the beginning of phase A, the gate current i_G is decreased by first switching off second partitions N3, N2, N1, and by then switching off and/or regulating down first partitions L2, L1. In the transition between phases A and B, the gate current i_G is controlled by a minimum, and then, during the phase B, increased again by a reversed order of the measures of phase A. In phase B0, depending on requirements, a plurality or all of the partitions L1–L3, N1–N2 are active. Because of a large or maximum control loop gain k_p, short switching times are achieved.

[0083] The lines drawn in bold show an upper limit S_M and a lower limit S_m for the gate current i_G or of the addable partitions L1–L4, N1–N4, in order to limit oscillations, in particular the amplitude of a resonant oscillation or a limiting cycle, of the gate current i_G. The limits S_M, S_m are adapted while passing phases A, A0, B, B0 depending on the ideal gate current requirement, in particularly approximately according to the discussed time dependencies proportional to t_A^−0.5 in phase A and to t_B² in phase B. Small gate currents i_G can be regulated with high speed, accuracy and stability by means of the first current source L. Large gate currents i_G can be regulated with very steep rise slopes and, in general, high dynamics, by means of the second current source N.

[0084] FIG. 15 shows an extended type of the gate driver GT with input and output amplifier stages partitioned according to the invention. On the input side, the comparator 6 for an actual current value i_vCE and a reference current i_ref for a collector voltage v_C is divided into three parallel partitions E0–E3 for a fast and precise driving of the current sources L, N. On the output side, there is a first amplifier stage 7a with a linear or controllable current source L, or L1–14, respectively, and with a current source N or N1–N4, which can be regulated in non-linear manner or be added in steps, and, in series, a second amplifier stage 7b with only a linear current source L or L1–L4. A control signal for activating the partitions L1–L4, N1–N4 and E0–E3 is generated in the structure control 11 by means of at least one threshold switch. An actual value and/or a reference value from the reference value generator 4 of a primary and/or secondary state variable v_C, dv_C/dt, i_C, di_C/dt, i_G, v_G, di_G/dt, dv_G/dt can be fed as input signal to the threshold switch.

[0085] FIGS. 16a, 16b and 16c show the set-up of the individual partial amplifiers E0–E3, L1–L4 and N1–N4. The first partitions L1–L4 comprise a linear cascade of current mirror arrangements of transistors T₅–T₈. The feedback 9 of state variables for stabilizing the control loop is connected to the emitter of the first current mirror arrangement via a transistor T₉ at the gate of which there is an output signal of the structure control 11. The second partitions N1–N4 comprise a mirror arrangement of transistors T₁₀–T₁₁. wherein the gate of output transistor T₁₁ of the mirror arrangement can be switched between being connected via a linear buffer BU for the gate voltage to the gate potential of the input transistor T₁₀ or a (not shown) fixed potential and a further, specifiable potential, in particular the emitter potential of the mirror arrangement, by means of at least one switch S. For example, a first switch S is connected directly and a second switch S via an inverter V with the structure control 11. i_n designates the input current of the current mirror, i_G the gate output current for the gate driver GT. The third partitions E0–E3 comprise a differential input with the input transistors T₁, T₂ for the actual and the reference current i_vCE and i_ref of the corresponding actual value and reference value of the relevant primary state variable v_C, dv_C/dt, i_C, di_C/dt, as well as a current mirror arrangement of transistors T₃, T₄. The structure control 11 is connected to the gate terminals of T₁, T₂. DIF designates the output signal of the partitions E0–E3 acting as comparator 6, and simultaneously the input signal of the linear second partitions L1–L4. In E0, the output signal DIF is set to a local reference potential in order to reduce the control loop gain. In deviation from FIG. 15, each first partition L1–L3 can be driven by exactly one third partition E1–E3. In that case the activation of the first partitions L1–L3 occurs, without intermediate switches, directly via the activation of the third partitions E1–E3.

[0086] The invention also relates to a semiconductor power switch S₁–S₄ or an arrangement of semiconductor power switches S₁–S₄ with at least one gate driver according to the invention. In particular, the or each semiconductor power switch S₁–S₄ comprises means for recording measured values of primary and/or secondary state variables v_C, dv_C/dt, i_C, di_C/dt, i_G, v_G, di_G/dt, dv_G/dt. Especially suited as semiconductor power switches are IGBTs (“insulated gate bipolar transistors”), MOSFETs (“metal oxide field effect transistors”) and BJTs (“bipolar junction transistors”). The arrangement can be an arrangement in series, a parallel arrangement or a serial arrangement of parallel arrangements, and in particular a switch module, in particular an inverter, for traction, high voltage DC transmission, radio transmitters, inductive heating or inductive welding.