US 6,960,799 B2Grant
Image sensor with a photodiode array
Issue Date:2005-11-01
•16 Claims
•3 Drawing Sheets
Abstract
An array of photodiodes includes regions of a second conductivity type formed in a semiconductive region of a first conductivity type, divided into three interleaved sub-arrays. All the photodiodes of a same sub-array are coated with a same interference filter including at least one insulating layer of determined thickness coated with at least one conductive layer. According to the present invention, the conductive layers are electrically connected to the semiconductive region of a first conductivity type.
Metadata
Assignee
- STMicroelectronics A.A.
Inventor
- Pierrick Descure
Application Information
Application Number:US 09/361,700
Filing Date:1999-07-27
Priority Date:1998-07-28
Art Unit:2811
Patent Drawings (3 sheets)
Description
Background of the Invention
[0001] 1. Field of the Invention
[0002] The present invention relates to the field of image sensors, usable for example in video cameras.
[0003] 2. Discussion of the Related Art
[0004] Among the various techniques for converting an image projected on a target into electric data, targets formed of a semiconductor substrate supporting an array of photodiodes are used. The diodes are generally reverse-biased and capacitively charged. In the absence of light, they keep their charge and, when lit, they discharge. A bright image element or pixel can thus be differentiated from a dark pixel and an image in the form of a matrix of data corresponding to the electric charges of each of the pixels can thus be restored.
[0005] Further, it is known to form this matrix so that all pixels are divided into three sub-arrays corresponding to each of three colors (currently, red, green, and blue). For this purpose, each of the pixels, that is, each of the diodes, is coated with a color filter. It is known to use an interference filter as a color filter. Interference filters formed of materials compatible with usual MOS-type integrated circuit manufacturing lines have also been provided. Thus, an interference filter may be formed of a silicon oxide layer coated with a polysilicon layer, itself coated with a silicon nitride layer. In fact, the successive materials have to alternately have low and high optical indexes.
[0006] In such structures, the storage capacity of each pixel is associated with the pixel dimension and more specifically with the dimension of the junction of the associated diode.
Summary of the Invention
[0007] An object of the present invention is to increase this storage capacity without increasing the dimension of an elementary cell of the sensor and without complicating its manufacturing.
[0008] To achieve this object as well as others, the present invention provides an array of photodiodes formed of regions of a second conductivity type formed in a semiconductive region of a first conductivity type, divided into three interleaved sub-arrays, all the photodiodes of a same sub-array being coated with a same interference filter including at least one insulating layer of determined thickness coated with at least one conductive layer. The conductive layers are electrically connected to the semiconductive region of a first conductivity type.
[0009] According to an embodiment of the present invention, the electric connection is indirect.
[0010] According to an embodiment of the present invention, the semiconductor substrate is a single-crystal silicon substrate, and the interference filter includes a silicon oxide layer formed above the substrate and a conductive polysilicon layer formed above the silicon oxide layer.
[0011] The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.
Brief Description of the Drawings
[0012] FIG. 1A shows a simplified cross-sectional view of a pixel of a photodiode array according to the present invention;
[0013] FIG. 1B shows the equivalent diagram of the pixel of FIG. 1A ;
[0014] FIGS. 2A , 2B, 2C illustrate successive steps of a method of realization of a layer of an interference filter used according to the present invention;
[0015] FIG. 3 shows in the form of a diagram an image sensor formed of a photodiode matrix according to the present invention; and
[0016] FIG. 4 shows an example of realization of a pixel of an image sensor according to FIG. 3.
Detailed Description
[0017] It should be noted that, as usual in the field of the representation of semiconductor components, the various drawings are not drawn to scale but that the dimensions of their various elements have been arbitrarily modified to facilitate the readability and simplify the drawing.
[0018] FIG. 1A shows a cross-sectional view of a photodiode associated with an interference filter according to the present invention. This photodiode is formed of an N-type semiconductive region 1 formed in a P-type semiconductor substrate 2. It will be assumed herein that the substrate is made of single-crystal silicon. Above region 1 is formed a multiple layer deposition forming an interference filter and including, for example, a silicon oxide layer 4, a polysilicon layer 5, and a silicon nitride layer 6. For optical radiation in the visible field, single-crystal silicon and polysilicon have a high refraction coefficient, on the order of 4, while silicon oxide and silicon nitride have low coefficients, on the order of 1.5. In a known manner, the thicknesses of the different layers have to be adjusted to have a coated effect and a filtering effect adapted to a specific wavelength. For example, if layers 5 and 6 have respective thicknesses of 20 and 50 nm, a filter is formed for blue by choosing for oxide layer 4 a thickness on the order of 150 nm, a filter is formed for green with a thickness on the order of 190 nm, and a filter is formed for red with a thickness on the order of 230 nm.
[0019] According to the present invention, polysilicon layer 5 is not left floating but is set to the same potential as substrate 2. This is schematically illustrated in the drawing by a contact between layer 5 and a heavily-doped P-type region 8 of substrate 2. Polysilicon layer 5 is sufficiently doped to be well conductive; it may also be coated with a metal layer (aluminum) or be silicided, outside regions where it is useful to make a filter.
[0020] Due to the link between layer 5 and substrate 2, the structure corresponds to the equivalent diagram shown in FIG. 1B. It is assumed that cathode region 1 of photodiode D is connected to a terminal K not shown in FIG. 1A and that the anode of the photodiode is connected to a terminal A, currently grounded. The presence of conductive layer 5 connected to the substrate is equivalent to the existence of a capacitor C arranged in parallel on the diode. The first “plate” of the capacitor is formed of layer 5 connected to the substrate, that is, to the diode anode. The second “plate” of the capacitor corresponds to cathode region 1 of the diode.
[0021] The equivalent capacity of each diode is thus increased, that is, the storage capacity of each photoelement and thus, the dynamics of the electric signals resulting from a lighting, is increased. The linearity of the charge/voltage characteristic is also improved by adding a constant capacitance to the capacitance of the diode junction which is variable with the applied voltage.
[0022] FIGS. 2A to 2C illustrate an example of a method for forming oxide layers of different thicknesses over three groups of cathode regions 1R, 1G, 1B respectively sensitive to red, to green, and to blue.
[0023] In a first step illustrated in FIG. 2A , a first silicon oxide layer 4-1 is deposited and etched to maintain it in place only above regions 1R.
[0024] In a second step illustrated in FIG. 2B , a second silicon oxide layer 4-2 is deposited and etched to only leave it in place above regions 1R and 1G.
[0025] In a third step illustrated in FIG. 2C , a third silicon oxide layer 4-3 is deposited and left in place. After this, a polysilicon layer 5 and possibly, as previously described, a silicon nitride layer, are deposited. Then, the structure is properly etched to enable making contacts at selected locations.
[0026] The thickness of layer 4-3, in the case of the example given previously, is 150 nm, and the thicknesses of layers 4-1 and 4-2 are 40 nm so that oxide layers having respective thicknesses of 230, 190 and 150 nm are found above regions 1R, 1G, and 1B.
[0027] FIG. 3 partially shows as an example and in the form of a circuit the conventional structure of a photodiode array intended for forming an image sensor. Each photodiode Dij is connected by its anode to the ground and by its cathode to the source of a precharge transistor Pij, the drain of which is connected to a reference voltage VR and the gate of which is connected to a row line Ri meant to select all the transistors Pij of a same row. Thus, in a first phase, diodes Dij are precharged. Then, after lighting, the voltage across the diodes is read by means of an amplifier formed, for example, of a first transistor Tij, the gate of which is connected to the connection node of transistor Pij and diode Dij, the source of which is connected to a column line Cj and the drain of which is connected to a high voltage Vdd. Each line Cj is connected to an amplifier Aj forming for example with transistor Tij a follower amplifier.
[0028] In such a structure, each diode Dij can be of the type described in connection with FIGS. 1A-1B , that is including a diode in parallel with a capacitor (not shown in FIG. 3).
[0029] An example of realization of a precharge transistor Pij and of a diode Dij is illustrated in FIG. 4. This structure is formed in a P-type single-crystal silicon substrate 10. Each transistor Pij includes an N-type drain region 11 and an N-type source region 12. Source region 12 extends to form the cathode region of diode Dij, the anode of which corresponds to substrate 10. Between the drain and the source of transistor Pij is formed an insulated gate 13, for example, made of polysilicon. The interference filter structure including layers 4, 5, and 6 already described in relation with FIG. 1 extends above most of region 12. Drain region 11 forms one piece with metallization 15 establishing a contact with a precharge voltage source VR.
[0030] Source/cathode region 12 forms one piece with a metallization 16 connected to the gate of transistor Tij (see FIG. 3). Further, and according to the present invention, polysilicon region 5 is connected to substrate 10. More currently, each of these regions will be connected to a common ground.
[0031] According to an alternative of the present invention, the diodes can be formed in a well itself formed in a substrate, that is, considering FIG. 4 , P region 10 is a well formed in an N-type substrate not shown. In this case, polysilicon region 5 can be connected to the substrate and not directly to region 10.
[0032] Of course, the present invention is likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art. In particular, the various described materials may be replaced with equivalent materials. Other materials compatible with the manufacturing of semiconductor components may be used to make the interference filter formed above each diode. A significant feature of the present invention is that one layer of this interference filter, separated from the semiconductor substrate by an insulating layer, is conductive and is connected to the substrate. All the described types of conductivity may be inverted. Further, although a silicon substrate has been described, it should be noted that other semiconductor systems may be adapted to the implementation of the present invention.
[0033] Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.
Claims
Post-issuance certificates present
The text shown below may not reflect later post-issuance changes.
1. An array of photodiodes made of regions of a second conductivity type formed in a semiconductive region of a first conductivity type, divided into three interleaved sub-arrays, each sub-array corresponding to a respective color of light, all photodiodes of a respective sub-array being coated with a same interference filter including at least one insulating layer of determined thickness coated with at least one conductive layer, a combined thickness of the at least one insulating layer and the at least one conductive layer being different for each sub-array, the determined thickness of said at least one insulating layer and said at least one conductive layer coating the respective sub-array determining the respective color of light that is interferentially filtered and provided to the respective sub-array, wherein the determined thickness of said at least one insulating layer is proportional to a wavelength of the color of light that is interferentially filtered, wherein said at least one conductive layer is electrically connected to the semiconductive region of the first conductivity type.
2. The array of photodiodes of claim 1, wherein the electric connection is indirect.
3. The array of photodiodes of claim 1, wherein the semiconductor substrate is a single-crystal silicon substrate, and the interference filter includes a silicon oxide layer formed above the substrate and a conductive polysilicon layer formed above the silicon oxide layer.
4. The array of photodiodes of claim 1, wherein the semiconductive region of the first conductivity type comprises a semiconductor substrate made of single-crystal silicon.
5. The array of photodiodes of claim 1, wherein said at least one insulating layer comprises a silicon oxide layer.
6. The array of photodiodes of claim 1, wherein said at least one conductive layer comprises a polysilicon layer.
7. The array of photodiodes of claim 1, further comprising a silicon nitride layer over said at least one conductive layer.
8. The array of photodiodes of claim 1, wherein said semiconductive region of the first conductivity type comprises a semiconductor substrate made of single-crystal silicon, said at least one insulating layer comprises a silicon oxide layer, and said at least one conductive layer comprises a polysilicon layer.
9. The array of photodiodes of claim 8, further comprising a silicon nitride layer over said at least one conductive layer.
10. The array of photodiodes of claim 9, wherein said single-crystal silicon layer and said polysilicon layer have a high refraction coefficient on the order of 4, while said silicon oxide layer and silicon nitride layer have a lower refract on coefficient, on the order of 1.5.
11. The array of photodiodes of claim 1, wherein said at least one conductive layer is connected to said semiconductive region of the first conductivity type at a heavily doped P-type region thereof.
12. The array of photodiodes of claim 1, wherein the at least one insulating layer includes a first insulating layer and a second insulating layer disposed below the first insulating layer, the first insulating layer extending across three photodiodes each in a different one of the three interleaved sub-arrays, and the second insulating layer extending across at least two photodiodes of the three photodiodes, wherein said at least on conductive layer extends across each of the three photodiodes above the first insulating layer.
13. The array of photodiodes of claim 12, wherein the at least one insulating layer further includes a third insulating layer, disposed below the second insulating layer, that extends across only one of the three photodiodes.
14. The array of photodiodes of claim 1, wherein said at least one insulating layer extends across three photodiodes each in a different one of the three interleaved sub-arrays, and wherein the determined thickness of said at least one insulating layer above each photodiode of the three photodiodes has a different thickness to interferentially filter a different wavelength of light.
15. The array of photodiodes of claim 1, wherein each of the photodiodes of each respective sub-array has a capacitance, and wherein said at least one conductive layer of the interference filter coating the respective sub-array forms a capacitance in parallel to the capacitance of each of the photodiodes of the respective sub-array.
16. The array of photodiodes of claim 1, wherein a thickness of said at least one conductive layer is substantially the same for each sub-array.
Patent Citations (61)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US4242694(A) | 1980-12-01 | Koike et al. | Applicant |
| US4407010(A) | 1983-09-01 | Baji et al. | Examiner |
| US4630091(A) | 1986-12-01 | Kuroda et al. | Applicant |
| US4996578(A) | 1991-02-01 | Motojima et al. | Examiner |
| US5084747(A) | 1992-01-01 | Miyawaki | Examiner |
| US5191399(A) | 1993-03-01 | Maegawa et al. | Applicant |
| US5237185(A) | 1993-08-01 | Udagawa et al. | Applicant |
| US5268309(A) | 1993-12-01 | Mizutani et al. | Applicant |
| US5306931(A) | 1994-04-01 | Stevens | Applicant |
| US5330933(A) | 1994-07-01 | Chan et al. | Applicant |
| US5345266(A) | 1994-09-01 | Denyer | Applicant |
| US5502488(A) | 1996-03-01 | Nagasaki et al. | Applicant |
| US5538207(A) | 1996-07-01 | Bordogna et al. | Applicant |
| US5580701(A) | 1996-12-01 | Lur et al. | Applicant |
| US5591997(A) | 1997-01-01 | Guidash et al. | Applicant |
| US5614744(A) | 1997-03-01 | Merrill | Examiner |
| US5621230(A) | 1997-04-01 | Guidash et al. | Applicant |
| US5747835(A) | 1998-05-01 | Pezzani | Applicant |
| US5831326(A) | 1998-11-01 | Chan et al. | Applicant |
| US5859462(A) | 1999-01-01 | Tredwell et al. | Applicant |
| US5881184(A) | 1999-03-01 | Guidash | Applicant |
| US5903021(A) | 1999-05-01 | Lee et al. | Applicant |
| US5926214(A) | 1999-07-01 | Denyer et al. | Applicant |
| US5945722(A) | 1999-08-01 | Tsuei et al. | Examiner |
| US5949061(A) | 1999-09-01 | Guidash et al. | Applicant |
| US5978025(A) | 1999-11-01 | Tomasini et al. | Applicant |
| US5981932(A) | 1999-11-01 | Guerrieri et al. | Applicant |
| US5982011(A) | 1999-11-01 | Kalnitsky et al. | Applicant |
| US5986297(A) | 1999-11-01 | Guidash et al. | Applicant |
| US6019848(A) | 2000-02-01 | Frankel et al. | Applicant |
| US6049118(A) | 2000-04-01 | Nagano | Examiner |
| US6051447(A) | 2000-04-01 | Lee et al. | Applicant |
| US6067113(A) | 2000-05-01 | Hurwitz et al. | Applicant |
| US6069377(A) | 2000-05-01 | Prentice et al. | Applicant |
| US6087703(A) | 2000-07-01 | Ohta et al. | Applicant |
| US6100551(A) | 2000-08-01 | Lee et al. | Applicant |
| US6100556(A) | 2000-08-01 | Drowley et al. | Applicant |
| US6107655(A) | 2000-08-01 | Guidash | Applicant |
| US6127697(A) | 2000-10-01 | Guidash | Applicant |
| US6133954(A) | 2000-10-01 | Jie et al. | Applicant |
| US6150683(A) | 2000-11-01 | Merrill et al. | Examiner |
| US6160281(A) | 2000-12-01 | Guidash | Applicant |
| US6160282(A) | 2000-12-01 | Merrill | Examiner |
| US6188056(B1) | 2001-02-01 | Kalnitsky et al. | Applicant |
| US6218656(B1) | 2001-04-01 | Guidash | Applicant |
| US6259124(B1) | 2001-07-01 | Guidash | Applicant |
| US6352876(B1) | 2002-03-01 | Bordogna et al. | Applicant |
| US6504572(B2) | 2003-01-01 | Kramer et al. | Applicant |
| US2002/0019070(A1) | 2002-02-01 | Laurin et al. | Applicant |
| EPA-0152353 | 1985-08-01 | Applicant | |
| EPA-0223136 | 1987-05-01 | Applicant | |
| EP1207686(A1) | 2002-05-01 | Applicant | |
| GB2276512(A) | 1994-09-01 | Applicant | |
| WO92/15036(A1) | 1992-09-01 | Applicant | |
| WO92/16999(A1) | 1992-10-01 | Applicant | |
| WO93/04556(A1) | 1993-03-01 | Applicant | |
| WO97/20434(A1) | 1997-06-01 | Applicant | |
| WO97/35438(A1) | 1997-09-01 | Applicant | |
| WO98/49729(A1) | 1998-11-01 | Applicant | |
| WO99/57887(A1) | 1999-11-01 | Applicant | |
| WO/52765(A1) | 2000-09-01 | Applicant |
Non-Patent Literature (9)
- French Search Report from French Patent Application 98 09801, filed Jul. 28, 1998.Applicant
- Patent Abstracts of Japan, vol. 009, No. 262 (P-398), Oct. 19, 1985 & JP-A-60 111225 (Matsushita Denki Sangyo KK).Applicant
- Christopher Bencher, Chris Ngai, Bernie Roman, Sean Lian, Tam Vuong, Dielectric Antireflective Coatings for DUV Lithography, Solid State Technology, Mar. 1997, vol. 40, Issue 3, Copyright 1997 by PennWell Publishing Company.Applicant
- R. Mehrotra, B.P. Mathur and S.Sharan, Reduction of the Standing Wave Effect in Positive Photoresist Using an Antireflection Coating, SPIE—The International Society for Optical Engineering, Mar. 1991, 487-491, vol. 1463, Published by the International Society for Optical Engineering.Applicant
- Patent Abstracts of Japan, vol. 009, No. 061, Mar. 19, 1985 & JP 59 198756 A (Hitachi Seisakusho KK).Applicant
- Patent Abstracts of Japan, vol. 1998, No. 03, Feb. 27, 1998 & JP 09 289301 A (Nikon Corp.) Nov. 4, 1997.Applicant
- Patent Abstracts of Japan, vol. 1998, No. 09, Jul. 31, 1998 & JP 10 098175 A (Toshiba Corp.).Applicant
- Patent Abstracts of Japan, vol. 2000, No. 11, Jan. 2, 2001 & JP 2000 236081 A (Nikon Corp.) Aug. 29, 2000.Applicant
- Furumiya M. et al., “High Sensitivity and No-Cross-Talk Pixel Technology For Embedded CMOS Image Sensor” International Electron Devices Meeting 2000. IEDM. Technical Digest, San Francisco, CA, Dec. 10-13, 2000, New York, NY: IEEE, US, Dec. 10, 2000, pp. 701-704.Applicant