Computer-aided design system to automate scan synthesis at register-transfer level

[0001] This application claims the benefit of U.S. Provisional Application No. 60/279,710 filed Mar. 30, 2001 which is hereby incorporated by reference.

[0002] The present invention generally relates to the field of Computer-aided design (CAD) system using design-for-test (DFT) techniques. Specifically, the present invention relates to the field of Computer-aided design (CAD) system for performing scan synthesis in integrated circuits modeled at register-transfer level (RTL).

[0003] The design methodology for complex integrated circuit (IC) designs has evolved with the advancement in process technologies. Currently, hardware description languages (HDL) are widely used to describe the behavior of a circuit at different levels of abstraction. The most commonly used approach is using HDL, such as Verilog or VHDL, to describe the circuit at register-transfer level (RTL). A computer-aided design (CAD) tool, generally called logic synthesizer, is then used to transform the above HDL design description into a technology dependent gate-level netlist, taking into account user-specified constraints on timing, power, area, etc.

[0004] Integrated circuits need to be tested in order to verify the correctness of their functionality. With the ever-growing complexity of integrated circuits, the testing cost has become a significant portion of the total manufacturing cost. Hence, testability issues should be taken seriously in the design process. The reason that a design with better testability usually results in lower test generation and test application costs.

[0005] There are many techniques to improve the testability of a design and reduce the costs for test generation and test application. These techniques are generally referred to as DFT (design-for-test) techniques. Among various DFT techniques, the scan-based DFT technique is the most widely used. In a scan-based design, scan storage elements, called scan cells, are used to replace original storage elements (flip-flops and latches). Some additional logic may also be added to the original design. As a result, the controllability and observability of the design will be greatly enhanced. In addition, test points, both control points and observation points, can be inserted into the original design to further improve its controllability and observability. The process of repairing scan-based DFT rule violations, inserting test points, replacing original storage elements with scan cells, and stitching the scan cells together as scan chains forms the basis of a scan synthesis CAD system.

[0006] Prior-art scan synthesis solutions start with a technology-dependent gate-level netlist. This means that, even though a modern IC design is often coded at RTL, it must be first synthesized into a gate-level netlist in order to conduct scan synthesis. This Scan-after-Logic-Synthesis design flow is time-consuming, inefficient, and difficult to meet design constraints. In such a design flow, when an integrated circuit design contains any DFT rule violations, they must be repaired at gate-level. In addition, replacing an original storage element with a scan cell and adding test points are also conducted on the gate-level netlist. However, the logic added to fix DFT rule violations and to improve fault coverage may violate user-specified design constraints, be it power, timing, or area. Although designers may choose to rewrite RTL codes to fix such problems, it requires re-compilation and re-synthesis, which consumes a lot of time and effort. Moreover, it has to be repeated multiple times until all DFT rule violations are fixed. The product life cycle of a modern IC design is very short. Fixing DFT problems at such a late stage in a design flow may cause the product to miss the market window and incur huge revenue losses.

[0007] An alternative prior-art approach, aimed at eliminating or reducing the number of iterations in a design flow, is to perform scan synthesis during logic synthesis. Logic synthesis generally contains two major steps: generic transformation and technology mapping (including logic optimization). Generic transformation is to synthesize RTL codes into a generic technology-independent gate-level model. Technology mapping is to map the generic gate-level model into a technology dependent gate-level netlist, based on user-specified constraints and a given cell library. Scan synthesis now can be performed between generic transformation and technology mapping. This Scan-within-Logic-Synthesis is also called one-pass scan synthesis or one-pass test synthesis. In principle, this approach still works at gate-level and solely relies on designers to fix most, if not all, DFT rule violations at RTL first. The main advantage of the Scan-within-Logic-Synthesis approach over the Scan-after-Logic-Synthesis approach is that it does not need to go through the lengthy technology mapping to locate DFT rule violations, if any. The disadvantage of the Scan-within-Logic-Synthesis approach, however, is that designers must guarantee their RTL codes to be testable before one-pass scan synthesis is performed.

[0008] In order to solve the problem with the current Scan-within-Logic-Synthesis approach, three prior-art solutions are available: one for test point insertion in an unmapped gate-level netlist (prior-art solution #1), one for test point insertion at RTL (prior-art solution #2), and one for scan insertion at RTL (prior-art solution #3) as summarized bellow:

[0009] Prior-art solution #1 is described in U.S. Pat. No. 6,311,317 by Khoche, et al. (2001). This solution adds test points to an unmapped gate-level netlist, removing the need of adding test points to a gate-level netlist obtained after logic synthesis. This solution, however, suffers from a major disadvantage. That is, this solution does not perform any analysis on an unmapped gate-level netlist to guide designers in choosing test points. As a result, user inputs should be provided to specify test points. This is not only time-consuming but also inefficient in some cases when less-effective test points are specified.

[0010] Prior-art solution #2 is described in U.S. Pat. No. 6,301,688 by Roy, et al. (2001). This solution selects test points at RTL based on a cost function derived from the controllability and observability measures. A list of candidate test points is first constructed. For each test point candidate, the solution computes a cost function that models the average number of pseudorandom patterns required to detect a fault, over the complete fault set. The candidate test point, which results in the largest reduction in the cost function, is then selected. This test point selection process is repeated until the estimated fault coverage meets the user-specified requirement, or the number of selected test points exceeds the user-specified limit. The disadvantage of this solution is that it solely relies on a computed cost function to guide test point selection, which is not always accurate. As a result, this solution may yield a less-effective set of test points since no interactive test point selection is supported.

[0011] Prior-art solution #3 is described in U.S. Pat. No. 6,256,770 by Pierce, et al. (2001). This solution performs scan insertion, including scan replacement and scan stitching, at RTL. This solution, however, suffers from several disadvantages: First, this solution does not take the concept of multiple clock domains into consideration. It basically assumes that all RTL modules will be implemented on a single clock domain. This is not a practical assumption since most modern IC designs consist of multiple clock domains, operating at a signal frequency or multiple frequencies. Second, this solution does not take the concept of hierarchical scan synthesis into consideration. Given the fact that modern IC designs are growing rapidly in size and complexity, any non-scalable solution without supporting hierarchical scan synthesis will be of only limited use. Third, this solution does not support scan repair, which is indispensable in preparing a design for scan synthesis. In fact, a complex RTL design may contain many scan DFT rule violations, such as asynchronous set/reset signals, generated clocks, constant clocks, clocks connected to data inputs of storage elements, gated clocks, latches, bi-directional ports, combinational feedback loops, pulse generators, tri-state busses, etc. Such violations must be fixed before scan insertion. Fourth, this solution does not support scan extraction, which is often needed to extract scan information from a scanned RTL design. Fifth, this solution does not support interactive scan debug and interactive scan repair, which are important when scan chains do not operate as intended.

[0012] In order to solve the disadvantages of prior-art solution, the present invention employs a new approach called Scan-before-Logic-Synthesis to move scan synthesis completely to the register-transfer level (RTL). The present invention will perform scan synthesis completely before logic synthesis, based on testability analysis, clock domain analysis, and user constraints. This Scan-before-Logic-Synthesis approach will allow designers to find all DFT rule violations at RTL and fix them by hand or by software. The present invention performs scan insertion and test point insertion at RTL and generate testable RTL codes for synthesis and verification. With the present invention, designers can verify scanned codes at RTL. The verified RTL codes can then be synthesized using any commercially available logic synthesis tool, based on original design constraints. The present invention can avoid costly iterations caused by scan chain insertion, test point insertion, and DFT violation repair at gate-level. In one embodiment of the present invention, the CAD system supports hierarchical RTL scan synthesis by allowing designers to conduct RTL scan synthesis module-by-module, and then stitching the scanned RTL modules hierarchically up to the top-level module.

[0013] Accordingly, what is needed in this present invention is a computer-aided design (CAD) system for effectively automating RTL scan synthesis or Scan-before-Logic-Synthesis, whose advantages are listed above. The CAD system can generate flush and random test benches to verify and debug scanned RTL codes. In addition, hierarchical test benches can also be generated to verify and debug the scanned RTL design at top-level.

[0014] The following table summarizes the results of analyzing different synthesis approaches:

[0015]

		Scan-after-	Scan-within-	Scan-before-
	Feature/Synthesis	Logic	Logic	Logic
	Input Model	Gate-Level	RTL	RTL
	Output Model	Gate-Level	Gate-Level	RTL
	Timing Closure	Difficult	Medium	Easy
	Synthesis Time	Long	Medium	Short

[0016] Accordingly, a primary objective of the present invention is to provide such an improved Scan-before-Logic-Synthesis system, comprising a computer-aided design (CAD) system for RTL scan synthesis. The inputs to the CAD system are RTL codes described in HDL (hardware description language) and scan constraints. The RTL codes for any integrated circuit can be in such a format as Verilog, VHDL, etc. The CAD system for RTL scan synthesis will consist of a suite of programs for performing such tasks as RTL testability analysis, clock-domain minimization, scan and test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and test bench generation. The Scan-before-Logic-Synthesis CAD system in accordance with the present invention is summarized as follows:

(1) RTL Compilation

[0017] Assume that an integrated circuit modeled at RTL is described in HDL, such as Verilog, VHDL, etc. RTL compilation will compile the RTL codes into a design database for all subsequent tasks. The design database captures the RTL circuit model which in essence are connections between RTL operators like adder, subtractor, multiplier, comparator, multiplexer, etc. Since not all nets in RTL nets are visible from the RTL codes, an index is given to each net in the RTL circuit. Cross probing is provided for all nets and RTL operators in the RTL circuit to the original RTL codes. The flip-flops, latches, and tri-state busses are inferred from the RTL codes.

(2) Testability Analysis at RTL

[0018] The present invention comprises any software that uses a CAD method to perform testability analysis on the design database to check whether the RTL codes contain any coding and DFT rule violations. In addition to reporting such violations as floating primary inputs, floating primary outputs, floating bi-directional pins, objects with floating inputs or outputs, floating nets, and transparent patches, the CAD system also reports such unique information as combinational feedback loops, potentially combinational feedback loops, generated clocks, sequentially gated clocks, combinationally gated clocks, constant clocks, connections from clocks to flip-flop or latch inputs, connections from clocks to output ports, connections to both clock and data inputs of a flip-flop or latch, generated set/reset signals, sequentially gated set/reset signals, combinationally gated set/reset signals, destructive set/reset signals, crossing clock domains, pulse generators, potential bus contentions, etc. If any such violation is found, the violation will be recorded and a summary of the violations will be reported. The testability analysis also generates clock domain analysis results that will be used in clock domain minimization. Controllability and observability measures are computed for all nets to the bit-level accuracy. These testability measures will be used as references to guide interactive test point insertion at RTL.

(3) Single-Frequency Clock-Domain Minimization at RTL

[0019] The present invention further comprises any software that uses a CAD method to perform clock-domain analysis based on the RTL codes of an integrated circuit in order to identify clock domains that do not interact with each other. The CAD method starts from clock input signals in the analysis process and generates a minimum set of scan clocks needed to test the integrated circuit at a reduce clock speed but concurrently. This RTL clock-domain analysis will result in less memory usage in fault simulation or test pattern generation and shorter test time. The present invention further comprises any apparatus that can merge and share scan clocks with primary data input pins.

[0020] For example, consider an integrated circuit with 8 clock domains, CD1 to CD8, controlled by 8 clocks, CK1 to CK8, respectively. Assume that one clock frequency, which may be applied with several different clock phases, is to be used to test the integrated circuit on an ATE (automatic test equipment). Conventionally, in order to test all clock domains, 8 different set of clock waveforms need to be applied. However, if two clock domains, e.g. CD2 and CD4, have no crossing clock-domain logic between them, in other words, if CD2 and CD4 do not interact with each other, the same set of clock waveforms can be applied to both CD2 and CD4.

(4) Multiple-Frequency Clock-Domain Minimization at RTL

[0021] The present invention further comprises any software that uses a CAD method to perform clock-domain analysis based on the RTL codes of an integrated circuit in order to identify clock domains that do not interact with each other. The CAD method starts from clock input signals in the analysis process and generates the minimum set of scan clocks needed to test the integrated circuit at its intended clock frequency or at-speed. If used in scan-test mode, this RTL clock-domain analysis will result in less memory usage in fault simulation or test pattern generation and shorter test time. If used in self-test mode, this RTL clock-domain analysis will result in less memory usage is self-test circuitry synthesis, smaller self-test circuitry, shorter fault simulation time, and shorter test time. The present invention further comprises any apparatus that can merge and share scan clocks with primary data input pins.

[0022] For example, consider an integrated circuit with 8 clock domains, CD1 to CD8, controlled by 8 clocks, CK1 to CK8, respectively. Assume that each clock domain is to be tested at its intended clock frequency or at-speed. Conventionally, in order to test all clock domains, 8 different set of clock waveforms need to be applied. However, if two clock domains running at the same frequency, e.g. CD2 and CD4, have no crossing clock-domain logic between them, in other words, if CD2 and CD4 do not interact with each other, the same set of clock waveforms can be applied to both CD2 and CD4.

(5) Scan and Test Point Selection at RTL

[0023] In order to reduce test time and test costs on an ATE (automatic test equipment), an integrated circuit is usually configured into having multiple scan chains. Scan chains are constructed based on the results of RTL testability analysis and clock domain minimization as described in (2), (3), and (4), as well as user-specified scan constraints. The CAD system will perform further analysis to decide the scan clock for each scan chain, balance the scan chain length when desired, and order the scan cells based on the clock domains when the scan chain consists of scan cells from different clock domains. Grouping and ordering of scan cells based on clock domains are useful to reduce the complication of clock skews and routing difficulties.

[0024] The CAD system can select only part of storage elements as scan cells, resulting in a partial-scan design, which can reduce the area overhead, routing difficulties, and performance degradation potentially associated with a full-scan or almost full-scan design. Especially, one can choose to select only part of storage elements as scan cells in such a manner that all sequential feedback loops are virtually removed through replacing original storage elements with scan cells. The resultant partial-scan design, called a feed-forward partial-scan or a pipe-lined partial-scan design, may have several non-scanned storage elements between two stages of scan cells. This property is characterized by sequential cell-depth. For example, a partial-scan design of a sequential cell-depth of 2 means that a signal value can be propagated from one stage of scan cells to another by applying at most two clock pulses. Note that a full-scan or almost full-scan design has a sequential cell-depth of 0. The CAD system can select scan cells for a partial-scan design based on the sequential cell-depth specified in scan constraints.

[0025] In addition, an integrated circuit could contain complex combinational logic blocks and large macro cells such as memories and mixed-signal blocks. In order to test the complex combinational logic blocks and the shadow logic surrounding the macro cells, it might be required to add test points, including control points, observation points, and control-observation points (called scan points). Furthermore, if an integrated circuit is to be tested with pseudorandom test patterns in self-test mode, test points may also need to be added since the circuit may contain a substantially large number of random pattern-resistant faults. The testability measures computed in RTL testability analysis can be used to guide test points insertion to improve the fault coverage of the integrated circuit. The designer can also interactively select a test point or a set of test points and let the system re-compute the estimated fault coverage for the integrated circuit. This interactive test point selection increases the flexibility and the chance of improving the circuit's fault coverage.

[0026] The present invention further comprises any software using a CAD system to first identify scan cells and test points, and then build scan chains based upon the scan clocks derived as the result of single-frequency clock-domain minimization at RTL and multiple-frequency clock-domain minimization at RTL, as well as user-specified scan constraints. The order of scan cells at this stage is determined based on module names and instance names. This order may not be final as it can be easily changed at a later stage when layout information becomes available.

(6) Scan Repair and Test Point Insertion at RTL

[0027] The scan chains constructed as the result of (5) may not function properly and the design may suffer from low fault coverage if the design contains any unfixed DFT rule violation. The most common DFT rule violations include generated clocks, constant clocks, asynchronous set/reset signals, potential bus contentions, transparent latches, gated clocks, combinational feedback loops, etc. If any scan-based DFT rule violations are found during RTL testability analysis, the designer can either fix the violations manually on the RTL codes, or resort to the CAD system to repair the violations automatically. Two additional input signals, one being a scan enable signal SE and the other being a test enable signal TE, can be added to the RTL codes for this purpose. The two enable signals, SE and TE, will be used to control the operation of added scan logic so that the circuit can function correctly during scan operations. Depending on the type of the violation, an enable signal, SE or TE, can be used to repair the violation. The following table summarizes the circuit operation mode under different SE and TE values.

[0028]

	TE	SE	Mode
	0	0	normal
	1	1	shift
	1	0	hold and capture

[0029] In addition, the CAD system will use either of the two enable signals, TE and SE, to add test points, including control points and observation points. A control point can be implemented with an AND gate, OR gate, multiplexer, or XOR gate; an observation point can be implemented with a new storage element or an XOR gate coupled to an existing storage element or primary output.

[0030] The present invention further comprises any software using a CAD system to automatically repair any DFT rule violations found during RTL testability analysis, such as generated clocks, constant clocks, clocks connected to data input, asynchronous set/reset signals, potential bus contentions, transparent latches, gated clocks, combinational feedback loops, etc. In addition, it further comprises any software using a CAD system to insert the selected test points.

(7) Scan Replacement and Scan Stitching at RTL

[0031] The storage elements identified during scan selection should be replaced with RTL codes representing scan cells after scan selection. Scan logic is added to make latches transparent during test. Then, all scan cells should be stitched together based on the scan chain order determined in the scan and test point selection stage.

[0032] The present invention further comprises any software using a CAD system to replace the storage elements identified during scan and test point selection with RTL codes representing scan cells and making latches transparent during test. In addition, the CAD system stitches all identified scan cells, either at the module level or at the top level. The scan enable signal SE is also connected in this stage to form complete scan chains.

(8) Scan Extraction at RTL

[0033] An integrated circuit can contain third-party scanned IP's (intellectual properties), such as CPU or DSP cores. It is important that such cores shall be tested properly. For this purpose, scan extraction is performed to extract the already existed scan chains from the circuit described in RTL codes.

[0034] The present invention further comprises any software using a CAD system to extract scan chains from scanned IP cores described in RTL codes, based on user-specified scan data input and output pins.

(9) Interactive Scan Debug at RTL

[0035] It is possible that during scan extraction or after scan replacement and scan stitching, the scan chains are still broken. It is important that such broken scan chains and scan instances shall be identified and repaired.

[0036] The present invention further comprises any software using a CAD system to allow the designer to interactively trace, either forwards or backwards, any scan chain and display signal values. Whenever any error is found, interactive commands, such as force 0 or 1, can be used to allow the designer to change internal signal values so that the designer can proceed further until all problems related to broken scan chains are identified and fixed. To aid in debugging, the present invention further comprises any software using a CAD system to display the RTL codes being traced and highlight the values on its corresponding schematics.

(10) Interactive Scan Repair at RTL

[0037] The present invention further comprises any software using a CAD system to allow the designer to conduct interactive scan repair. As long as any broken chains are identified and fixed during interactive scan debug, these fixes must be reflected on the RTL codes by modifying the original RTL codes by hand or by software.

(11) Test Bench Generation at RTL

[0038] Upon successful verification of scan chains, an integrated circuit now becomes testable. The designer can now verify the scanned integrated circuit with his/her own test benches created or use the flush and random test benches created by the CAD system.

[0039] The present invention further comprises any software using a CAD system to allow a designer to generate flush or random test benches based upon the extracted scan chains on scanned RTL codes.

(12) Hierarchical Scan Synthesis and Test Bench Generation at RTL

[0040] A large and complex integrated circuit usually contains many large modules or IP cores. To reduce scan synthesis time, one can first do scan synthesis on a module-by-module basis, and then stitch them together at top-level.

[0041] The present invention further comprises any software using a CAD system to allow the designer to do scan synthesis, comprising stages described from (1) through (12), on a module-by-module basis, stitch them together at top-level, and generate the required top-level flush or random test benches.

[0069] The following description is presently contemplated as the best mode of carrying out the present invention. This description is not to be taken in a limiting sense but is made merely for the purpose of describing the principles of the invention. The scope of the invention should be determined by referring to the appended claims.

[0070] FIG. 1 shows an example integrated circuit design before scan synthesis and its corresponding scan-based integrated circuit design after scan synthesis in accordance with the present invention.

[0071] FIG. 1A shows a typical integrated circuit design before scan synthesis is performed. The design 136 has 4 clock domains CD1 101 to CD4 104, 3 crossing clock-domain logic blocks CCD1 105 to CCD3 107, primary inputs 108 to 111, primary outputs 116 to 119, and bi-directional pins 120 to 123. In addition, it has 4 system clocks CK1 112 to CK4 115, running at 3 different frequencies. Furthermore, storage elements (SE) exist in each clock domain.

[0072] FIG. 1B shows the resulting design 157 after scan synthesis is performed on the integrated circuit design 136 shown in FIG. 1A. After scan synthesis, all or part of original storage elements (SE) are replaced with scan cells (SC). In addition, the scan cells are stitched into one or a plurality of scan chains (SCN), which can be accessed by scan inputs 149 to 152 and scan outputs 153 to 156. A scan cell can accept data either from its corresponding functional logic, or from its previous scan cell in the scan chain or a scan input, depending on the values of scan enable signals SE1 145 to SE4 148. These scan enable signals, together with test enable signals TE1 141 to TE4 144, are also used to fix scan design rule violations.

[0073] A scan-based integrated circuit, such as the one shown in FIG. 1B, is tested by repeating three operations: shift, capture, and comparison or compaction, as described bellow:

[0074] During the shift operation or in a shift cycle, pseudorandom or predetermined stimuli will be shifted through scan inputs 149 to 152 to all scan cells SC in all scan chains SCN within the 4 clock domains, CD1 101 to CD4 104, simultaneously. After the shift operation or a shift cycle is completed, capture clocks are applied to all clock domains, CD1 101 to CD4 104, to capture circuit responses into scan cells. After the capture operation or a capture cycle is completed, the circuit responses captured into all scan cells SC are shifted out through scan outputs 153 to 156 for direct comparison during the comparison operation or for compaction during the compaction operation. In order to determine if the circuit 157 is faulty or not, the comparison operation compares captured circuit responses with expected circuit responses after each stimulus is applied; while the compaction operation compresses captured circuit responses into a signature repeatedly after each stimulus is applied. The signature is only compared with the expected signature once all stimuli have been applied.

[0075] FIG. 2 shows a block diagram of a computer-aided design (CAD) system for scan synthesis at RTL, of one embodiment of the present invention. The RTL scan synthesis CAD system 200 accepts the user-supplied synthesizable RTL codes 202 and the scan constraints 201. The scan constraints 201 contain all set-up information and scripts required for compiling 203 the RTL codes 202 into a design database 204, based on which RTL testability analysis 205, clock-domain minimization 206, scan selection 207, test point selection 208, scan repair and test point insertion 209, scan replacement and scan stitching 210, scan extraction 211, interactive scan debug 212, and interactive scan repair 213 are performed. The CAD system then produces final scanned RTL codes 215 as well as HDL (hardware description language) test benches 214. All reports and errors are stored in report files 216.

[0076] FIG. 3 shows an example report generated by testability analysis at RTL in accordance with the present invention. The report 300 consists of two parts: Circuit Statistics and Testability Analysis Summary. Circuit Statistics reports such information as the numbers of primary input pins, primary output pins, bi-directional pins, accessible nets, accessible flip-flops, accessible latches, accessible register files, accessible memory elements, inaccessible flip-flops, inaccessible latches, inaccessible register files, and inaccessible memory elements in the circuit under analysis. Testability Analysis Summary reports the numbers of various types of scan design rule violations found during RTL testability analysis, including floating primary input ports, floating primary output ports, floating bi-directional ports, objects with floating inputs, objects with floating outputs, floating nets, sequential gated set/reset, combinational gated set/reset, generated set/reset, destructive set/reset, generated clocks, sequential gated clocks, combinational gated clocks, constant clocks, connections from clocks to data inputs, transparent latches, unfixed bi-directional pins, combinational feedback loops, potential combinational feedback loops, pulse generators, potential bus contentions, and crossing clock domains. In addition, detailed information on the identified scan design rule violations, including module names, and locations, is also included in the report.

[0077] FIG. 4 shows an example of reducing test generation cost and test application cost for a design containing 8 clock domains, of one embodiment of the present invention at single-frequency or slow-speed. The design 400 has 8 clock domains, CD1 401 to CD8 408, which is controlled by 8 clocks, CK1 to CK8 (not shown in FIG. 4) respectively. For the purpose of clock domain minimization, the clock information is specified in scan constraints in the following ASCII format:

[0078]

	%TA_CONSTRAINTS
	{
		%CLOCK CK1 = ′010000000000000000000000′;
		%CLOCK CK2 = ′000010000000000000000000′;
		%CLOCK CK3 = ′000000010000000000000000′;
		%CLOCK CK4 = ′000000000010000000000000′;
		%CLOCK CK5 = ′000000000000010000000000′;
		%CLOCK CK6 = ′000000000000000010000000′;
		%CLOCK CK7 = ′000000000000000000010000′;
		%CLOCK CK8 = ′000000000000000000000010′;
}

[0079] In the above specification, each clock is given a different phase. As a result, a total of 24 clock phases are used. Clock-domain minimization is performed to minimize the number of clocks needed for test in order to reduce test generation cost and test application cost. Note that, through testability analysis at RTL, the information on how clock domains interact with each other is obtained. Based on this information, clock-domain minimization will be performed by merging clock domains that do not interact with each other. In the design 400, since CD1 401 interacts with all other clock domains, it cannot be merged with any other clock domain. Clock domains CD2 402 and CD4 404 do not interact each other and thus can be merged. Since CD3 403, CD5 405, CD6 406, CD7 407, and CD8 408 do not interact each other, they can also be merged. As a result, the design 400 can be tested using only 3 scan clocks, SCK1 415 to SCK3 417. The capture sequences of the 3 scan clocks in one-hot mode, non-overlapping mode, and overlapping mode, are given below:

[0080]

	%CAPTURE_SEQUENCE // In one-hot mode
	{
	%CLOCK SCK1 = ′010′;
	%CLOCK SCK2 = ′010′;
	%CLOCK SCK3 = ′010′;
	}
	% CAPTURE_SEQUENCE // In non-overlapping mode
	{
	%CLOCK SCK1 = ′010000000′;
	%CLOCK SCK2 = ′000010000′;
	%CLOCK SCK3 = ′000000010′;
	}
	% CAPTURE_SEQUENCE // In overlapping mode
	{
	%CLOCK SCK1 = ′0111000′;
	%CLOCK SCK2 = ′0011100′;
	%CLOCK SCK3 = ′0001110′;
	}

[0081] Here, SCK1={CK1}, SCK2={CK2, CK4}, and SCK3={CK3, CK5, CK6, CK7, CK8}. SCK2={CK2, CK4}, for example, means that scan clock SCK2 416 is wired to both clocks CK2 and CK4 to test clock domains CD2 402 and CD4 404, simultaneously. In overlapping mode, for example, 7 clock phases are used instead of 24 clock phases.

[0082] FIG. 5 shows an example of reducing test generation cost and test application cost for a design containing 8 clock domains, of one embodiment of the present invention at multiple-frequency or at-speed. The design 500 has 8 clock domains, CD1 501 to CD8 508, which is controlled by 8 clocks, CK1 to CK8 (not shown in FIG. 5) respectively. Clock domain CD1 501 is operated at 50 MHz, clock domains CD2 502 and CD4 504 are operated at 66 MHz, all other clock domains are operated at 133 MHz. For the purpose of clock domain minimization, the clock information is specified in scan constraints in the following ASCII format:

[0083]

	%TA_CONSTRAINTS
	{
	%CLOCK CK1 = ′010000000000000000000000′;
	%CLOCK CK2 = ′000010000000000000000000′;
	%CLOCK CK3 = ′000000010000000000000000′;
	%CLOCK CK4 = ′000000000010000000000000′;
	%CLOCK CK5 = ′000000000000010000000000′;
	%CLOCK CK6 = ′000000000000000010000000′;
	%CLOCK CK7 = ′000000000000000000010000′;
	%CLOCK CK8 = ′000000000000000000000010′;
	}

[0084] During clock-domain minimization, clock domains with the same frequency are analyzed at the same time. Since CD1 501 is the only clock domain that operates at 50 MHz, it must be tested independently with a scan clock SCK1 516. Since CD2 502 and CD4 504 are operated at the same frequency of 66 MHz and they do not interact with each other, their corresponding clocks CK2 and CK4 can be merged into one scan clock SCK2 517. Since CD3 503, CD6 506, CD7 507, and CD8 508 are operated at 133 MHz and they do not interact each other, their corresponding clocks CK3, CK6, CK7, and CK8 can be merged into one scan clock SCK3 518. However, since CD5 505, though operated at the same frequency as CD3, CD6, CD7, and CD8, interacts with CD3 503, CD5 505 should be tested independently with a scan clock SCK4 519. As a result, the design 500 can be tested using only 4 scan clocks SCK1 516 to SCK4 519. The capture sequences of the 4 scan clocks in one-hot mode and non-overlapping mode are given below:

[0085]

	%CAPTURE_SEQUENCE // In one-hot mode
	{
	%CLOCK SCK1 = ′010′;
	%CLOCK SCK2 = ′010′;
	%CLOCK SCK3 = ′010′;
	%CLOCK SCK4 = ′010′;
	}
	%CAPTURE_SEQUENCE // In non-overlapping mode
	{
	%CLOCK SCK1 = ′0100000′;
	%CLOCK SCK2 = ′0001000′;
	%CLOCK SCK3 = ′0000010′;
	%CLOCK SCK4 = ′0001000′;
	}

[0086] Here, SCK1={CK1}, SCK2={CK2, CK4}, SCK3={CK3, CK6, CK7, CK8}, and SCK4={CK5}. SCK2={CK2, CK4}, for example, means that scan clock SCK2 517 is wired to both clocks CK2 and CK4 to test clock domains CD2 502 and CD4 504, simultaneously. In the non-overlapping mode, for example, only 7 clock phases instead of 24 clock phases are used. SCK2 517 and SCK4 519 can operate concurrently but at different frequencies. This is because the clock domains, CD2 502 and CD4 504, driven by SCK2 517, and the clock domain CD5 505 driven by SCK4 519 do not interact with each other.

[0087] FIG. 6 shows an example design with 2 clock domains driven by 2 scan clocks in accordance with the present invention, where an optimal order for applying a sequence of the 2 scan clocks to the 2 clock domains in a capture cycle is identified in order to minimize the memory usage in transforming an integrated circuit for fault simulation or ATPG (automatic test pattern generation).

[0088] As shown in FIG. 6, clock domains CD1 601 and CD2 602 are driven by scan clocks CK1 605 and CK2 606, respectively. In addition, there is a unidirectional crossing clock domain logic block CCD1 603 from CD1 601 to CD2 602, and there is a unidirectional crossing clock domain logic block CCD2 604 from CD2 602 to CD1 601. Assume that, the memory sizes needed to store the design databases of CD1 601, CD2 602, CCD1 603, and CCD2 604, measured by analyzing the corresponding RTL codes through fast-synthesis or estimation, are denoted by S(CD1), S(CD2), S(CCD1), and S(CCD2), respectively. Note that such a size should reflect the size of the gate-level netlist once the corresponding RTL codes are synthesized. In addition, assume that a single capture clock pulse is applied to each scan clock in a capture cycle.

[0089] First, consider the capture order of CK1 605 to CK2 606. When CK1 605 captures, S(CD1)+S(CCD2) of memory is needed for circuit transformation; then, when CK2 606 captures, S(CD1)+S(CD2)+S(CCD1)+S(CCD2) of memory is needed for circuit transformation since values in clock domain CD1 601 have already changed because the capture operation is first conducted in CK1 605. That is, the total memory usage for this scan clock order is proportional to A=2*S(CD1)+S(CCD1)+S(CD2)+2*S(CCD2).

[0090] Second, consider the capture order of CK2 606 to CK1 605. When CK2 606 captures, S(CCD1)+S(CD2) of memory is needed for circuit transformation since values in clock domain CD1 601 have not changed yet; then, when CK1 605 captures, S(CD1)+S(CD2)+S(CCD1)+S(CCD2) of memory is needed for circuit transformation. That is, the total memory usage for this scan clock order is proportional to B=S(CD1)+2*S(CCD1)+2*S(CD2)+S(CCD2).

[0091] The difference in memory usage is A−B=(S(CD1)+S(CCD2))−(S(CD2)+S(CCD1)). Obviously, depending on the sizes of clock domains CD1 601 and CD2 602 as well as crossing clock domains CCD1 603 and CCD2 604, one can identify the optimal order for scan clocks CK1 605 and CK2 606.

[0092] FIG. 7 shows an example set of scan constraints for RTL scan selection and test point selection in accordance with the present invention.

[0093] As shown from line 3 to line 14, the user-specified scan constraints 700 indicate what modules shall be included or excluded from RTL scan insertion, how many scan chains are allowed, how many scan cells are allowed for each scan chain, whether it is required to balance all scan chains, and what cell depth is allowed for a feed-forward partial-scan design, etc. If no cell depth is specified, a full-scan design, of cell-depth 0, will be automatically assumed. Based on such constraints, RTL codes are analyzed and a set of scan instance files are generated, each containing a set of storage elements to be formed into one scan chain.

[0094] Scan selection starts by analyzing the design database and selecting storage elements within each clock domain that are directly controllable by a scan clock. When a selected storage element cannot be directly controllable by a scan clock, it can be repaired when so required. The selected storage cells are put into groups according to user-specified scan constraints, i.e. the maximum scan chain length, the number of scan chains, etc. When scan balancing is required, scan cells from different clock domains may be merged or split. In this case, it is necessary to perform scan ordering for scan cells within all clock domains to reduce clock skews and routing difficulties.

[0095] As shown from line 15 to line 28, the user-specified scan constraints 700 also indicate where to insert control points, including AND-control points, OR-control points, MUX-control points, and XOR-control points, as well as observation points, including normal observation points and XOR-observation points. Information on where to insert scan points is also specified in scan constraints 700.

[0096] FIG. 8 shows an example set of RTL Verilog codes and circuit models before and after scan repair of various asynchronous set/reset violations in accordance with the present invention.

[0097] In any scan-based DFT (design-for-test) technique, all asynchronous set/reset signals must be disabled in a shift cycle since they may destroy the values that are being shifted into scan chains. When an asynchronous set/reset signal is not driven directly by a primary input, it is hard to control the asynchronous set/reset signal during test. This is a scan design rule violation. Generally, there are four types of asynchronous set/reset violations; sequential gated set/reset, combinational gated set/reset, generated set/reset, and destructive set/reset. In a sequential gated set/reset violation, the set/reset signal can be traced back to a specified set/reset source gated with the output of a storage element such as a flip-flop or a latch. In a combinational gated set/reset violation, the set/reset signal can be traced back to a specified set/reset source gated with a primary input or the output of a combinational logic block. In a generated set/reset violation, the set/reset signal cannot be traced back to any primary input specified as a set/reset source. In a destructive set/reset violation, the set/reset signal is stuck at a certain logic value that sets or resets the storage element constantly. A scan enable signal, SE, is used for repairing such an asynchronous set/reset rule violation. The SE signal is set to logic value 1 in a shift cycle and is set to logic value 0 in a capture cycle or a functional cycle.

[0098] FIG. 8A shows an example set of RTL Verilog codes before and after scan repair of a sequential gated set/reset rule violation and a combinational gated set/reset rule violation in accordance with the present invention. In the original RTL Verilog codes, the asynchronous set/reset signal s_rst on line 11, of the inferred D flip-flop q1, can be traced back to the output of a D flip-flop z on line 8. Note that z is gated with the specified set/reset source signal rst on line 5. Obviously, this is a sequential gated set/reset violation. In addition, the asynchronous set/reset signal c_rst on line 18, of the inferred D flip-flop q2, can be traced back to the primary input x on line 6. Note that x is gated with the specified set/reset source rst on line 6. Obviously, this is a combinational gated set/reset violation. In the modified RTL Verilog codes, two new signals, scan_s_rst and scan_c_rst, are added to model the repaired s_rst and c_rst signals, respectively. The continuous assignment statements on lines 9 and 11 model the added scan logic that repairs the sequential gated set/reset violation and the combinational gated set/reset violation, respectively. In the modified RTL codes, SE on lines 9 and 11 is a scan enable signal. When SE has logic value 0, the RTL circuit behavior is the same as the original one; when SE has logic value 1, the signal scan_s_rst and scan_c_rst will become logic value 0, disabling the asynchronous set/reset operation of the D flip-flops inferred for signals q1 and q2 in the always blocks on lines 19 and 26, respectively.

[0099] FIG. 8B shows an example set of RTL Verilog codes before and after scan repair of a generated set/reset rule violation and a destructive set/reset rule violation in accordance with the present invention. In the original RTL Verilog codes, the asynchronous set/reset signal g rst on line 10, of the inferred D flip-flop q1, can be traced back to the output of a D-flip flop on line 6. Obviously, this is a generated set/reset violation. The asynchronous set/reset signal d_rst on line 17, of the inferred D flip-flop q2, is always stuck at logic value 1. Obviously, this is a destructive set/reset violation because the D flip-flop q2 will always be reset. In the modified RTL Verilog codes, two new signals, scan_g_rst and scan_d_rst, are added to model the repaired g_rst and d_rst signals, respectively. The continuous assignment statements on lines 9 and 11 model the added scan logic that repairs the generated set/reset violation and the destructive set/reset violation, respectively. In the modified RTL codes, SE on lines 9 and 11 is a scan enable signal. When SE has logic value 0, the RTL circuit behavior is the same as the original one; when SE has logic value 1, the signal scan_g_rst and scan_d_rst will become logic value 0, disabling the asynchronous set/reset operation of the D flip-flops inferred for signals q1 and q2 in the always block on lines 18 and 25, respectively.

[0100] FIG. 8C shows the circuit model corresponding to the original RTL codes in FIG. 8A. D flip-flops DFF2 822 and DFF3 823 are reset by asynchronous signals s_rst 831 and c_rst 832, respectively. Since the value of s_rst 831 is determined by an AND gate 824 with the output z 830 of D flip-flop DFF1 821 as one of its inputs, this is a sequential gated set/reset rule violation. Since the value of c_rst 832 is determined by an AND gate 825 with only primary inputs rst 826 and x 827 as its inputs, this is a combinational gated set/reset rule violation.

[0101] FIG. 8D shows the circuit model after scan repair of the sequential gated set/reset violation and the combinational gated set/reset violation shown in FIG. 8C. Here, two AND gates 837 and 838 as well as two inverters 835 and 836 are added to disable the reset operations of DFF2 822 and DFF3 823 only in a shift cycle via the scan enable signal SE 839. When SE 839 has logic value 0, s_rst 831 and c_rst 832 will be used to reset DFF2 822 and DFF3 823. respectively; when SE 839 has logic value 1, scan_s_rst 840 and scan_c_rst 841 will become logic value 0, preventing DFF2 822 and DFF3 823 from being reset in a shift cycle, respectively.

[0102] FIG. 8E shows the circuit model corresponding to the original RTL codes in FIG. 8B. D flip-flops DFF2 852 and DFF3 853 are reset by asynchronous signals g_rst 857 and d_rst 858, respectively. Since g_rst 857 comes directly from a D flip-flop DFF1 851, this is a generated set/reset rule violation. Since the reset port of DFF3 853 is stuck at logic value 1, this is a destructive set/reset rule violation.

[0103] FIG. 8F shows the circuit model after scan repair of the generated set/reset violation and the destructive set/reset violation shown in FIG. 8E. Here, two AND gates 863 and 864 as well as two inverters 861 and 862 are added to disable the reset operations of DFF2 852 and DFF3 853 only in a shift cycle via the scan enable signal SE 865. When SE 865 has logic value 0, g_rst 857 and d_rst 858 will be used to reset DFF2 852 and DFF3 853, respectively; when SE 865 has logic value 1, scan_s_rst 866 and scan_c_rst 867 will become logic value 0, preventing DFF2 852 and DFF3 853 from being reset in a shift cycle, respectively.

[0104] FIG. 9 shows an example set of RTL Verilog codes and circuit models before and after scan repair of various clock violations in accordance with the present invention.

[0105] Generally, in any scan-based DFT (design-for-test) technique, the clock signals of all scan cells must be directly controlled by a designated test clock. When a clock signal is not driven directly by a primary input specified as a test clock source, it is hard to control the clock during test. This is a scan design rule violation. There are four types of clock violations: generated clock, combinational gated clock, sequential gated clock, and constant clock. In a generated clock violation, the clock signal cannot be traced back to a primary input specified as a test clock source. In a combinational gated clock violation, the clock signal can be traced back to a specified test clock source gated with a primary input or the output of a combinational logic block. In a sequential gated clock violation, the clock signal can be traced back to a specified test clock source gated with the output of a storage element such as a flip-flop or a latch. In a constant clock violation, the clock signal is stuck at a certain logic value and breaks the corresponding scan chain.

[0106] FIG. 9A shows an example set of RTL Verilog codes before and after scan repair of various clock violations in accordance with the present invention. As shown in FIG. 9A, in the original RTL Verilog codes, the clock signal g_clk on line 8, of the inferred D flip-flop q1, is the output of a D flip-flop on line 4. This is a generated clock violation.

[0107] The clock signal c_clk on line 15, of the inferred D flip-flop q2, can be traced back to the specified clock source clk, gated with the signal clk_en. This is a combinational gated clock violation. The clock signal const_clk on line 19, of the inferred D flip-flop q3, is always stuck at logic value 0. This is a constant clock violation since the D flip-flop q3 can never be triggered. In the modified RTL Verilog codes, a test enable signal, TE, and a scan enable signal, SE, are added in order to repair various clock violations. test_g_clk is added on line 7 to model the repaired clock signal to fix the generated clock violation during test. test_c_clk is added on line 10 to model the repaired clock signal to fix the combinational gated clock violation or any sequential gated clock violation in a shift cycle. test_const_clock is added on line 12 to model the repaired clock signal to fix the constant clock violation during test.

[0108] FIG. 9B shows the circuit model corresponding to the original RTL codes in FIG. 9A. The D flip-flops DFF2 912, DFF3 913, and DFF4 914 are driven by clock signals g clk 921, c_clk 922, and const_clk 923, respectively. The clock signal g_clk 921 is the output of the D flip-flop DFF1 911; hence, this is a generated clock violation. The clock signal c_clk 922 is driven by the output of an AND gate 915, and is directly traced back to a designated clock source clk 919 and a primary input clk_en 920; hence, this is a combinational gated clock violation. Clock signal const_clock 923 is stuck at logic value 0; hence this is a constant clock violation.

[0109] FIG. 9C shows the circuit model after scan repair of the generated, combinational gated and constant clock violations. Two multiplexers 927 and 928 as well as one OR gate 929 are added to repair the above violations. When the test enable signal TE 930 is set to logic value 1 during test, the multiplexer 927 will select the designated test clock signal clk 919 as the clock of DFF2 912. The output of the OR gate 929 will be forced to logic value 1 in a shift cycle by the scan enable signal SE 931. This will allow DFF3 913 to be controlled directly by the designated test clock signal clk 919. The multiplexer 928 will also select the designated test clock signal clk 919 as the clock for DFF4 914 during test. After scan repair, the D flop-flops DFF2 912, DFF3 913, and DFF4 914 are all directly controlled by the designated test clock clk 919. Note that a sequential gated clock can be repaired in the same way as a combinational gated clock.

[0110] FIG. 10 shows an example set of RTL Verilog codes and circuit models before and after scan repair of a connection from clock to input violation in accordance with the present invention.

[0111] In any scan-based DFT (design-for-test) technique, a clock signal should not be connected to the data input of any storage element. Such a violation may create race condition in a capture cycle. The captured data in a capture cycle becomes unknown since it depends on the delay of the paths from the test clock to the clock input and the data input of the storage element. All paths from the clock to the data input of a scan cell must be broken during test.

[0112] FIG. 10A shows an example set of RTL Verilog codes before and after scan repair of a connection from clock to input violation in accordance with the present invention. In the original RTL Verilog codes, the clock signal clk is connected to the data input of the inferred flip-flip q via a combinational logic block as shown on line 1. In the modified RTL Verilog codes, a test enable signal TE is added on line 5, based on which a new signal test_clk_to_d on line 5 is added to model a stable logic value to the data input of flip-flop q. The continuous assignment statement on line 8 models the added scan logic. When TE has logic value 1, test_clk_to_d is set to logic value 1. As a result, the data input of the D flip-flop q will have a stable and known value during test.

[0113] FIG. 10B shows the circuit model corresponding to the original RTL codes in FIG. 10A. There is a connection from the clock signal clk 1015 to the data input of the D flip-flop DFF 1012 through an AND gate 1011. This is a connection from clock to data input violation.

[0114] FIG. 10C shows the circuit model after scan repair of the connection from clock to data input violation. One OR gate 1018 is added to repair the violation. When the TE signal 1019 is set to logic value 1 during test, the path from the clock signal clk 1015 to the data input of DFF 1012 will be disabled.

[0115] FIG. 11 shows an example set of RTL Verilog codes and circuit models before and after a latch is made transparent in accordance with the present invention.

[0116] FIG. 11A shows an example set of RTL Verilog codes before and after a latch is made transparent in accordance with the present invention. In the original RTL Verilog codes, the latch is inferred from variables which are read before they are written in an always block. The enable signal of the latch is also inferred from the original RTL Verilog codes. In any scan-based DFT (design-for-test) technique, latches must be replaced with scan latches or made transparent in a shift cycle. In modified RTL codes, a test enable signal TE is added on line 5 to make the latch transparent during test. The modified RTL Verilog codes have the same behavior as the original RTL codes when TE has logic value 0. Most commercial logic synthesis tools also support the instantiation of technology independent latches at RTL. In this case, scan latch replacement or scan repair can also be performed on the technology independent latch instances.

[0117] FIG. 11B shows the circuit model corresponding to the original RTL codes in FIG. 11A. The latch LAT 1111 must be made transparent during test.

[0118] FIG. 11C shows the circuit model after scan repair is performed to make the latch transparent. One OR gate 1116 is added to make the enable signal of the latch LAT 1111 always active during test. When the test enable TE signal 1117 is set to logic value 1 during test, the output 1118 of the added OR gate 1116 will become logic value 1, activating the latch LAT 1111.

[0119] FIG. 12 shows an example set of RTL Verilog codes and circuit models before and after scan repair of a bi-directional pin in accordance with the present invention.

[0120] FIG. 12A shows an example set of RTL Verilog codes before and after fixing a bi-directional pin to input mode, in accordance with the present invention. As shown in the modified RTL codes, a scan enable signal, SE, is added on line 7 to fix the bi-directional pin to input mode. Generally, in a scan-based DFT (design-for-test) design, each bi-directional pin must be fixed to either input or output mode during test.

[0121] FIG. 12B shows circuit model corresponding to the original RTL codes shown in FIG. 12A. The direction of the bi-directional pin abus 1213 is controlled by the tri-state buffer 1212. In a shift cycle, the pin must be fixed to either input or output mode.

[0122] FIG. 12C shows the circuit model after fixing the bi-directional pin to input mode. One AND gate 1217 and one inverter 1216 are added to disable the tri-state buffer 1212 in a shift cycle. When the scan enable signal SE signal 1218 is set to logic value 1 in a shift cycle, the new tri-state buffer enable signal, scan_tri_en 1219, will become logic value 0. As a result, the tri-state buffer 1212 will be disabled, thus fixing the bi-directional pin abus 1213 to input mode.

[0123] FIG. 13 shows an example set of RTL Verilog codes and circuit models before and after scan repair of a combinational feedback loop or a potential combinational feedback loop in accordance with the present invention.

[0124] In any scan-based DFT (design-for-test) technique, combinational feedback loops must be avoided. Combinational feedback loops are usually caused by design errors. However, if the use of combinational feedback loops is required in the design, the combinational feedback loops must be broken during test. A potential combinational feedback loop is a false loop in functional mode, but will be also broken if it can become a loop during test.

[0125] FIG. 13A shows an example set of RTL Verilog codes before and after scan repair of a combinational feedback loop or a potential combinational feedback loop in accordance with the present invention. In order to repair a combinational feedback loop violation or a potential feedback loop violation, a storage element is inserted into the loop. The added storage element will be replaced with a scan cell and will be stitched into scan chains. A test enable signal, TE, is used to fix such a combinational feedback loop violation or a potential feedback loop violation. In the modified RTL Verilog codes, an always block is added to model the inserted D flip-flop on line 10. The continuous assignment on line 14 uses TE to break a combinational feedback loop or a potential combinational feedback loop. When TE has logic value 1, such a combinational feedback loop or potential combinational feedback loop is broken by the inserted D flip-flop.

[0126] FIG. 13B shows circuit model corresponding to the original RTL codes in FIG. 13A. There are two combinational feedback loops in the circuit model. One combinational feedback loop goes from the output 1314 of the multiplexer 1311 through the output 1315 of the comparator 1312, and reaches back to the output 1314 of the multiplexer 1311. The other combinational feedback loop goes from the output 1314 of the multiplexer 1311 through the multiplexer 1311 itself, and reaches back to the output 1314 of the output of the multiplexer 1314.

[0127] FIG. 13C shows the circuit model after the combinational feedback loops shown in FIG. 13B are broken. One D flip-flop DFF 1317 and one multiplexer 1316 are added to repair the combinational feedback loop violations during test. The combinational feedback loops will be broken by DFF 1317 when the test enable signal TE 1319 is set to logical value 1 during test.

[0128] FIG. 14 shows an example set of RTL Verilog codes and circuit models before and after scan repair of a pulse generator violation in accordance with the present invention.

[0129] FIG. 14A shows an example set of RTL Verilog codes before and after scan repair of a pulse generator violation in accordance with the present invention. In the original RTL codes, the reset signal g_rst on line 3 comes from a pulse generator on line 1. Such a pulse generator may cause unexpected glitches that have adverse effects on a circuit in a capture cycle during test. A test enable signal TE is used to fix such a pulse generator violation. In the modified RTL Verilog codes, the signal test_g_rst on line 5 is added to model the repaired reset signal. The continuous assignment on line 5 uses TE to disable the reset signal during test.

[0130] FIG. 14B shows the circuit model corresponding to the original RTL codes shown in FIG. 14A. The output 1417 of D flip-flop DFF 1411 is connected through an AND gate 1412 to its own set/reset signal. The output 1417 of D flip-flop DFF 1411 may generate a short pulse during test, thus invalidating test results.

[0131] FIG. 14C shows the circuit model after the scan repair of the pulse generator violation shown in FIG. 14B is performed. An AND gate 1418 and an inverter 1419 are added to disable the set/reset signal of the D flip-flop DFF 1411 during test. When the test enable signal TE 1420 is set to logic value 1 during test, the set/reset signal of D flip-flop DFF 1411 is disabled.

[0132] FIG. 15 shows an example set of RTL Verilog codes and circuit models before and after scan repair of potential bus contention in accordance with the present invention.

[0133] In a shift cycle, any bus must not be driven by more than one driver; otherwise, bus contention will occur. If a bus contention violation is found by testability analysis at RTL, a scan enable signal SE will be used to repair the violation so that only one driver drives the bus in a shift cycle.

[0134] FIG. 15A shows an example set of RTL Verilog codes before and after scan repair of potential bus contention in accordance with the present invention. In the original RTL verilog codes, the enable signals that control the tri-state buffers come from the outputs of D flip-flops. If the D flip-flops are replaced by scan cells, more than one tri-state buffers may be activated in a shift cycle. After scan repair of this bus contention violation as shown in the modified RTL Verilog codes, a scan enable signal SE on lines 7 to 10 is added to enable only one bus driver but disable all others in a shift cycle when SE has logic value 1.

[0135] FIG. 15B shows the circuit model corresponding to the original RTL codes shown in FIG. 15A. The circuit will operate correctly in functional mode since the enable signals of the tri-state buffers 1516 to 1519 are fully decoded in functional mode. However, if the D flip-flops DFF1 1512 to DFF4 1515 are replaced with scan cells in a scan-based DFT technique, their outputs, tri_en[0] 1527 to tri_en[3] 1530, may take any combination of logic values. As a result, more than one tri-state buffers may be activated; thus causing a bus contention.

[0136] FIG. 15C shows the circuit model after scan repair of the bus contention shown in FIG. 15B is performed. As shown in FIG. 15C, one OR gate 1541, three AND gates 1542 to 1544, and three inverters 1545 to 1547 are added to the original circuit model shown in FIG. 15B in order to repair the bus contention violation. Here, if the scan enable signal SE 1548 is set to logic value 1 in a shift cycle, the repaired tri-state enable signal scan_tri_en[0] 1549 will become logic value 1, activating the tri-state buffer 1516. The other tri-state buffers are disabled since the repaired tri-state enable signals scan_tri_en[1] 1550, scan_tri_en[2] 1551 and scan_tri_en[3] 1552 will become logic value 0 in a shift cycle. As a result, only d1 1523 can drive the bus dbus 1531 in a shift cycle.

[0137] FIG. 16 shows an example set of RTL Verilog codes and circuit models before and after control point insertion in accordance with the present invention.

[0138] Based on the controllablity measures calculated in RTL testability analysis, control points are inserted to improve the controllablity of a design, resulting in less test cost and higher fault coverage. The user may interactively select a control point or a set of control points and let the system re-compute the estimated fault coverage. After control points are selected, the original RTL Verilog codes are modified to include the control point insertion logic. The types of control points that can be inserted are: OR-control points, AND-control points, MUX-control points, and XOR-control points. Flip-flops that are added for control points will be replaced with scan cells and will be stitched into scan chains during scan replacement and scan stitching. Various control points are modeled with different functions and tasks. Additional always blocks are also required to model added control flip-flops.

[0139] FIG. 16A shows an example set of RTL Verilog codes before and after OR-control point insertion and AND-control point insertion in accordance with the present invention. In the modified RTL Verilog codes, the functions on lines 8 and 16 model one 1-bit OR-control point and one AND-control point, respectively. The always block on line 24 models a control D flip-flop. The function call on line 29 models the inserted OR-control point for the signal running. The function call on line 38 models the inserted AND-control point for the signal each8.

[0140] FIG. 16B shows an example set of RTL Verilog codes before and after MUX-control point insertion and XOR-control point insertion in accordance with the present invention. In the modified RTL Verilog codes, the functions on lines 8 and 16 model one 1-bit MUX-control point and one XOR-control point, respectively. The always block on line 24 models a control D flip-flop. The function call on line 29 models the inserted MUX-control point for the signal running. The function call on line 38 models the inserted XOR-control point for the signal each8.

[0141] FIG. 16C shows the circuit model corresponding to the original RTL codes shown in FIG. 16A and FIG. 16B. Here, the MODULO unit 1624 and EQUAL units 1625 and 1626 are combinational logic blocks used to implement % (modulo) and = (equal) functions, respectively.

[0142] FIG. 16D shows the circuit model after one OR-control and one AND-control points are inserted into the original circuit model shown in FIG. 16C. The OR gate 1643 is inserted for the signal running 1629, while the AND gate 1646 is inserted for the signal each8 1634. The control D flip-flops DFF2 1641 and DFF3 1647 will be replaced with scan cells and will be stitched into scan chains in the scan replacement and scan stitching process. Note that values of ctrl_reg[0] 1649 and ctrl_reg[1] 1650 can be changed easily by shifting values through scan chains, thus improving the controllability of the selection input of the multiplexer 1621 and the input of the AND gate 1628.

[0143] FIG. 16E shows the circuit model after one MUX-control and one XOR-control points are inserted into the original circuit model shown in FIG. 16C. The MUX-control point 1662 is inserted for the signal running 1629, and the XOR-control point 1664 is inserted for the signal each8 1634. The control D flip-flops DFF2 1661 and DFF3 1665 will be replaced with scan cells and will be stitched into scan chains in the scan replacement and scan stitching process. Note that values of ctrl_reg[0] 1666 and ctrl_reg[1] 1667 can be changed easily by shifting values through scan chains, thus improving the controllability of the selection input of the multiplexer 1621 and the input of the AND gate 1628.

[0144] FIG. 17 shows an example set of RTL Verilog codes and circuit models before and after observation point insertion in accordance with the present invention.

[0145] Based on the observability measures calculated in RTL testability analysis, observation points are inserted to improve the observability of a design, resulting in less test cost and higher fault coverage. The user may interactively select an observation point or a set of observation points and let the system re-compute the estimated fault coverage. After observation points are selected, the original RTL Verilog codes are modified to include the observation point insertion logic. The types of observation points that can be inserted are: normal observation points using flip-flops, shared XOR-observation points, and control-observation points called scan points. Flip-flops that are added for observation points will be replaced with scan cells and will be stitched into scan chains during scan replacement and scan stitching. Various observation and scan points are modeled with different functions and tasks. Additional always blocks are also required to model added observation flip-flops.

[0146] FIG. 17A shows an example set of RTL verilog codes before and after normal observation point insertion in accordance with the present invention. In the modified RTL Verilog codes, two flip-flops are added as observation points for two signals, running and each8, respectively. The task on line 6 models one 1-bit observation point. The two task enable statements on lines 15 and 16 are used to model the added observation points. The observation flip-flops are inferred from the always statement on line 20.

[0147] FIG. 17B shows an example set of RTL Verilog codes before and after XOR-observation point insertion in accordance with the present invention. In the modified RTL Verilog codes, two signals, running and each8, are XOR-ed together and connected to the primary output d_out on line 19.

[0148] FIG. 17C shows an example set of RTL Verilog codes before and after XOR-observation point insertion and scan point insertion in accordance with the present invention. In the modified RTL Verilog codes, two signals, running and each8, are XOR-ed together to share one observation D flip-flop on lines 32. In addition, a scan point is added to the expression count72 on line 46. The always statement on line 29 models the D flip-flops for the observation point and the scan point.

[0149] The circuit model corresponding to the original RTL codes of FIG. 17A, FIG. 17B, and FIG. 17C is the same as the one shown in FIG. 16C.

[0150] FIG. 17D shows the circuit model after normal observation points are inserted into the original circuit model shown in FIG. 16C. The D flip-flop DFF2 1731 is inserted for the signal running 1629, while the D flip-flop DFF3 1732 is inserted for the signal each8 1634. DFF2 1731 and DFF3 1732 will be replaced with scan cells and will be stitched into scan chains in the scan replacement and scan stitching process. As a result, the values of running 1629 and each8 1634 can be observed through obsv_reg[0] 1733 and obsv_reg[1] 1734.

[0151] FIG. 17E shows the circuit model after one XOR-observation point is inserted into the original circuit model shown in FIG. 16C. In FIG. 17E, instead of connecting the two signals, running 1629 and each8 1634, to observation D flip-flops, they are connected to an XOR gate 1741, whose output is then connected to primary output dout 1742. As a result, the two signals, running 1629 and each8 1634, can be observed easily through primary output dout 1742.

[0152] FIG. 17F shows the circuit model after one XOR-observation point and one scan point are inserted into the original circuit model shown in FIG. 16C. In FIG. 17F, two signals, running 1629 and each8 1634, are merged by an XOR gate 1751 whose output is connected to an observation D flip-flop DFF2 1752. In addition, a D flip-flop DFF3 1753 and a multiplexer 1754 are added at the output of the inverter 1627. The D flip-flops DFF2 1752 and DFF3 1753 will be replaced with scan cells and will be stitched into scan chains in the scan replacement and scan stitching process. As a result, the values of running 1629 and each8 1634 can be observed through obsv_reg 1755. In addition, the observability of the output of the inverter 1627 and the controllability of the input of the AND gate 1628 can be improved by the scan point through scan_reg 1756.

[0153] FIG. 18 shows an example set of RTL Verilog codes before and after scan replacement and scan stitching in accordance with the present invention. In the original RTL codes, two D flip-flops are inferred by the always statement on line 9. In the modified RTL codes, scan replacement and scan stitching take place in the always statement on line 11. A scan enable signal, SE, a scan input signal, SI, and a scan output signal, SO, are added. In the modified RTL codes, the output of the first D flip-flop is automatically connected to the scan data input of the second D flip-flop during scan stitching as shown on lines 19 to 22.

[0154] FIG. 19 shows an example set of commands for scan extraction at RTL in accordance with the present invention. Two commands are provided: set_port on line 1 and extract on line 8. The set_port command is used to indicate which scan in and out ports should be used for scan extraction. The extract command performs scan extraction by using both simulation and topological searches to extract a scan chain with the specified scan in port and scan out port. The scan instances found during the process are stored in a specified file. If the process fails to extract an intact scan chain from the specified scan in port and scan out port, the longest path will be listed in the specified file, and an error message will be issued.

[0155] FIG. 20 shows an example set of commands for interactive scan debug at RTL in accordance with the present invention. During interactive scan debug, the designer will be able to trace and locate broken scan chains and provide temporary fixes until all errors are found. The present invention consists of 5 scan debug commands: force, force_clock, trace_fanin, trace_fanout, and flush_test, on lines 1, 4, 7, 10, and 13, respectively. The interactive scan debug process typically starts with specifying the input pattern that will be shifted in during flush test. A default pattern will be used if no input pattern is specified. The scan enable signal SE is set to enable the shift operation of the scan chain. The scan clock of the scan chain is set to activate the shift operation. The flush_test command performs simulation to shift in the pattern and checks if the scan chain is broken or some scan cells are transparent. If the scan chain is broken, the commands force, trace_fanin, and trace_fanout can be used to interactively force a certain value to a net in order to identify the cause of the broken scan chain.

[0156] FIG. 21 shows an example set of commands for interactive scan repair at RTL in accordance with the present invention. In interactive scan repair mode, the program will list each design rule violation and will provide a suggestion to fix it. The designer can either accept (A) the suggestion with recommended RTL codes to fix the rule violation automatically, or skip (S) the suggestion to modify original RTL codes later manually.

[0157] FIG. 22 shows 3 example syntaxes of input information for generating HDL (hardware description language) test benches and ATE (automatic test equipment) test programs. The input information mainly includes tester-specific timing diagrams specified in the ASCII format. In FIG. 22, a non-overlapping mode is shown. It can be seen that the ATE cycle time is set to 100 ns, the SCK1 clock rises at 20 ns and falls at 30 ns, the SCK2 clock rises at 40 ns and falls at 50 ns, the SCK3 clock rises at 60 ns and falls at 70 ns, and the SCK4 clock rises at 80 ns and falls at 90 ns. Additional information, such as primary output strobe timing, is also specified in FIG. 22. Based on such information, HDL test benches and ATE test programs can be generated. FIG. 22 also shows information for overlapping mode and one-hot mode, respectively.

[0158] FIG. 23 shows a flow diagram of a computer-aided design (CAD) system for hierarchical scan synthesis at RTL in accordance with the present invention.

[0159] Assume that an integrated circuit modeled at RTL consists of one top-level module and 2 independent modules. The CAD system 2300 for hierarchical RTL scan synthesis accepts user-supplied RTL codes for the top-level module 2308, and the 2 independent modules 2302 and 2305. The CAD system 2300 also accepts top-level scan constraints 2307 and 2 sets of module-level scan constraints 2301 and 2304. The scan constraints are needed for RTL scan synthesis on a module-by-module basis.

[0160] Module-level scan constraints, 2301 and 2304, contain all set-up information and scripts required to perform corresponding module-level RTL scan synthesis, 2303 and 2306, respectively. The top-level scan constraints 2307 contain all set-up information and scripts required to perform top-level RTL scan synthesis 2309. The CAD system will then produce final scanned RTL codes 2311 as well as HDL (hardware description language) test benches 2310. All reports and errors are stored in the report files 2312.

[0161] Part of example information needed for this hierarchical scan synthesis at RTL, described in the ASCII format, is shown as follows:

[0162]

%SCAN_SYNTHESIS_MODULES
{
	%MODULE module_1
	{
	%SCAN_IN = scan_in_of_module_1;	// Scan in ports
	%SCAN_OUT = scan_out_of_module_1;	// Scan out ports
	%SCAN_ENABLE = SE_1;	// Scan enable signal of module_1
	%TEST_ENABLE = TE_1;	// Test enable signal of module_1
	%DFT = module_dft_1;	// Scan constraints file of module_1
	}
	%MODULE module_2
	{
	%SCAN_IN = scan_in_of_module_2;	// Scan in ports
	%SCAN_OUT = scan_out_of_module_2;	// Scan out ports
	%SCAN_ENABLE = SE_2;	// Scan enable signal of module_2
	%TEST_ENABLE = TE_2;	// Test enable signal of module_2
	%DFT = module_dft_2;	// Scan constraints file of module_2
	}
}

[0163] FIG. 24 shows an example system in which a computer-aided design (CAD) system for RTL scan synthesis, in accordance with the present invention, may be implemented. The system 2400 includes a processor 2402, which operates together with a memory 2401 to run a set of the RTL scan synthesis software. The processor 2402 may represent a central processing unit of a personal computer, workstation, mainframe computer, or other suitable digital processing device. The memory 2401 can be an electronic memory or a magnetic or optical disk-based memory, or various combinations thereof. A designer interacts with the RTL scan synthesis software run by processor 2402 to provide appropriate inputs via an input device 2403, which may be a keyboard, disk drive, or other suitable source of design information. The processor 2402 provides outputs to the designer via an output device 2404, which may be a display, a printer, a disk drive, or various combinations of these and other elements.

[0164] FIG. 25 shows an environment in which a scanned RTL design developed using the process of FIG. 2 or FIG. 23 may be tested. The environment 2500 is generally referred to as a self-test environment. The scanned RTL random logic circuit described by scanned RTL codes 2503 is interconnected with self-test logic in a self-test environment. The self-test logic includes a self-test controller 2501, a pseudorandom pattern generator 2502, a circuit response analyzer 2504, and a multiplexer 2505. The pseudorandom pattern generator 2502 generates random patterns that are applied to the scan inputs 2513 and primary inputs 2516 during test. The multiplexer 2505 is controlled in such a manner that primary inputs 2516 get input values from the pseudorandom pattern generator 2502 in self-test mode. The circuit response analyzer 2504 compresses the scan outputs 2517, and optionally the primary outputs 2518, at each clock cycle and results in a signature at the end of self-test session. Then, the signature is compared with an expected signature to determine if there is a mismatch between them. The comparison can be conducted either on-chip or by an automatic test equipment (ATE) after the signature is shifted out. If the comparison is conducted on-chip, the result can be indicated by the Pass/Fail signal 2520. The self-test controller 2501 starts a self-test session in response to the START signal 2506, and sets the FINISH signal 2508 at the end of the self-test session. The self-test controller 2501 also generates all control signals including scan enable SE signals 2511. In addition, the self-test controller 2501 manipulates and controls self-test clocks CK 2512 based on original scan clocks SCK 2507.

[0165] FIG. 26 shows an environment in which a scanned RTL design developed using the process of FIG. 2 or FIG. 23 may be tested. The environment 2600 is generally referred to as a scan-test environment. The scanned RTL random logic circuit described by scanned RTL codes 2602 is interconnected with a set of automatic test equipment (ATE) 2601. The ATE 2601 is capable of applying a predetermined set of test vectors to the scan inputs 2603 and the primary inputs 2604 of the scanned RTL random logic circuit, and observing the scan outputs 2605 and the primary outputs 2606 to determine if there is a mismatch between observed and expected results at any clock cycle. The test vectors may be generated using an automatic test pattern generation (ATPG) program, which generates appropriate test vectors based on, for example, a gate-level netlist and a description of the scan chains.

[0166] Having thus described presently preferred embodiments of the present invention, it can now be appreciated that the objectives of the invention have been fully achieved. And it will be understood by those skilled in the art that many changes in construction & circuitry, and widely differing embodiments & applications of the invention will suggest themselves without departing from the spirit and scope of the present invention. The disclosures and the description herein are intended to be illustrative and are not in any sense limitation of the invention, more preferably defined in scope by the following claims.