Digital to analog converter augmented with direct charge transfer techniques

[0001] This application claims priority to U.S. Provisional Application No. 60/392,363 filed Jun. 27, 2002.

[0002] 1. Technical Field

[0003] The present application relates, in general, to digital to analog converters.

[0004] 2. Description of the Related Art

[0005] Digital to analog converters (hereafter referred to as “DACs”) attempt to produce a faithful reproduction of an analog continuous-time signal from discrete-time digital samples. In theory, a DAC can be implemented with an array of weighted analog components that are controlled by an incoming digital code. The outputs of the weighted analog components are then summed and filtered to reproduce a continuous-time signal.

[0006] One type of DAC is known in the art as an “oversampling” DAC. One example of an oversampling DAC device is shown in FIG. 1.

[0007] FIG. 1 shows related-art oversampling DAC device 100. Upsampling and digital interpolation filtering unit 104, composed of 8× upsampling unit 106 and digital interpolation filtering unit 108, receives the digital input signal. In operation, 8× upsampling unit 106 typically samples much faster than the rate at which the digital input signal is expected to change, and tends to create unwanted spectral images. Accordingly, digital interpolation filtering unit 108 receives the output of 8× upsampling unit 106 and removes the unwanted spectral images created by the operation of 8× upsampling unit 106.

[0008] Upsampling and digital zero order hold unit 110, composed of 32× upsampling unit 112 and digital zero order hold filtering unit 114 receives the output of digital interpolation filtering unit 108. In particular, 32× upsampling unit 112 receives the output of digital interpolation filtering unit 108. Digital zero order hold filtering unit 114 receives the output of 32× upsampling unit 112, and typically repeats an incoming sample for a number of times equal to the amount of upsampling (e.g., repeating 32 times).

[0009] The output of digital zero order hold filtering unit 114 feeds to digital noise shaping loop 119. Digital noise shaping loop 119 contains embedded quantizer unit 117 which typically reduces the number of elements required to perform the actual digital to analog conversion (e.g., such as those illustrated in DAC 118). Digital noise shaping loop 119 typically functions to push much of the digital quantization noise introduced by the quantization operation out of the signal band of interest and provides a high pass noise transfer function. The input to digital noise shaping loop 119 typically sees unity gain to the output of digital noise shaping loop 119, so signals of interest are generally not degraded by the operation of digital noise shaping loop 119.

[0010] The output of digital noise shaping loop 119 controls the switching of the actual DAC elements of DAC 118. In some cases, the designer may also choose to add element linearization circuitry which is controlled by the output of the digital noise shaping loop 119 and in turn dictates the switching of the actual DAC elements of DAC 118, such that the resulting output of the DAC array is unaffected by mismatches between the DAC elements. The actual DAC elements of DAC 118 typically deliver either charge or current to a summing node in order to produce a reconstructed analog signal.

[0011] The output of DAC 118 is received by analog postfilter 120. Generally, analog postfilter 120 is configured to reduce the out-of-band noise resulting from shaped quantization performed by digital noise shaper 116. Those having ordinary skill in the art will appreciate that, for a fully monolithic integrated circuit application, it is desirable that analog postfilter 120 be of at least the order of digital noise shaping loop 119 in order to attenuate out-of-band noise. Having analog postfilter 120 be at least the same order as noise shaping loop 119 helps prevent interference of out of band noise with other circuit blocks on a monolithic chip, and also avoids undesirable mixing with other out-of-band signals.

[0012] In modern integrated circuit (e.g., CMOS) processes, the digital circuitry used in upsampling, noise shaping, and analog postfiltering of the actual DAC element switching can be scaled down to the point where power and area consumption are very low for a given noise specification. However, the analog performance of such scaled down systems is often limited by inherent component noise, which has generally not been reduced as integrated circuit (e.g., CMOS) process resolution has increased. In response to this dilemma, related-art circuit techniques have been developed to reduce noise and power consumption. However, notwithstanding these related art techniques, a more or less constant need exists in the art for D/A techniques which reduce noise and power consumption, especially in scaled down monolithic integrated circuit applications.

[0013] In addition to the foregoing, there are additional problems associated with D/A converters having differing input (digital) and output (analog) common mode references. This problem originates from the fact that system designers typically assume that their negative references for both digital and analog components are the same—namely 0V. System designers do this because 0V is a convenient reference and it provides them with the maximum signal swing for a given positive reference. Analog reference voltages should typically be from rail-to-rail, that is from 0V to the maximum supply voltage, because the analog output swing must be as wide as possible. However, system designers have recognized that the negative digital reference does not necessarily need to be at 0V. The negative digital reference may be set higher so as to make the digital common mode the same as the analog common mode. In this case, system designers have recognized that the common mode references for the digital and analog need not be split, and in fact, for DCT (described following), the common mode references may be set to a value independent of the actual digital/analog common mode.

[0014] The drawback to this approach in D/A converter designs such as where a DCT postfilter is integrated with a D/A converter, however, is that by decreasing the difference between the positive and negative reference voltages, the amplitude of the signal that comes into the analog postfilter is also decreased. Since the noise of the analog postfilter is the same as before, the signal-to-noise ratio is now in turn decreased. In order to restore the signal-to-noise ratio, the power and area of the analog postfilter must increase to reduce the noise. Thus, the split-common mode reference scheme is preferred because the amplitude of the signal incoming to the analog postfilter need not be decreased. However, the split common mode reference scheme does cause problems as outlined above. Accordingly, a need exists for a scheme that will utilize a split common mode reference, while alleviating some of the problems associated with the scheme.

[0015] In one embodiment, an electronic system includes but is not limited to a digital to analog converter (DAC) having a DAC output; and an analog postfilter having a postfilter input coupled to the DAC output, said analog postfilter including a first direct charge transfer (DCT) coupled filter having a first DCT coupled filter input and a first DCT coupled filter output a second DCT coupled filter having a second DCT coupled filter input operably connected with the first DCT coupled filter output.

[0016] In one embodiment, a method for use with an electronic system includes but is not limited to coupling a digital to analog converter (DAC) output with an analog post filter having a first direct charge transfer (DCT) coupled filter and a second DCT coupled filter.

[0017] In one embodiment, a method for use with an electronic system includes but is not limited to filtering a digital to analog converter (DAC) output signal with an analog post filter having a first direct charge transfer (DCT) coupled filter and a second DCT coupled filter.

[0018] In one embodiment, an electronic system includes but is not limited to a digital to analog converter (DAC) having a DAC output; and an analog postfilter having a postfilter input coupled to the DAC output, said analog postfilter including at least (1) a dual common mode switching network coupled between the DAC output and a first DCT coupled filter input, and (2) a second DCT coupled filter having a second DCT coupled filter input coupled to a first DCT coupled filter output.

[0019] In one embodiment, a method for use with an electronic system, said method includes but is not limited to coupling a DAC output with a first direct charge transfer (DCT) coupled filter input wherein said coupling a DAC output with a first direct charge transfer (DCT) coupled filter input includes: (a) coupling a DAC sampling capacitor to a DAC common mode reference with a first switch, (b) coupling the first DCT filter input to an analog common mode reference with a second switch, and (c) said first switch and second switch controllable such that the DAC sampling capacitor is couplable to the first DCT filter input shortly after at least one of decoupling the DAC sampling capacitor from the DAC common mode reference and decoupling the first DCT coupled filter input from the analog common mode reference [FIG. 5]; and coupling a first DCT coupled filter output with a second DCT coupled filter input.

[0020] In one embodiment, a method for use with an electronic system includes but is not limited to compensating for a difference between a digital common mode reference voltage and an analog common mode reference voltage by coupling a Digital to Analog Converter (DAC) to the digital common mode reference voltage and coupling an analog portion to the analog common mode reference voltage at a first time and coupling at least a portion of the DAC with the analog portion at a second time; filtering a DAC output signal with a first direct charge transfer (DCT) coupled filter; and filtering an output of the DCT coupled filter with a second direct charge transfer (DCT) coupled filter.

[0021] The foregoing is a summary and thus contains, by necessity, simplifications, generalizations and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and is NOT intended to be in any way limiting. Other aspects, inventive features, and advantages of the devices and/or processes described herein, as defined solely by the claims, will become apparent in the non-limiting detailed description set forth herein.

[0037] The use of the same symbols in different drawings typically indicates similar or identical items.

I. Introduction

[0038] In one embodiment, improved D/A conversion is provided by use of devices and processes that utilize Direct Charge Transfer (DCT) coupled filtering. In another embodiment, D/A conversion is yet further improved by augmenting the DCT coupled filtering devices and processes with Correlated Double Sampling (CDS) circuitry and processes. In yet another embodiment, D/A conversion is yet further improved by augmenting the DCT filtering devices and processes with postfilter droop compensation circuitry and processes.

II. D/A Devices and Processes Having DCT Coupled Filter Blocks

[0039] A. DCT Coupled Filter Blocks

[0040] One disadvantage of switched-capacitor D/A topologies is the undesirable tradeoff between kT/C noise, capacitor area, and power dissipation. One circuit process that decouples the power dissipation factor from this tradeoff is referred to herein as Direct Charge Transfer (DCT) coupled filtering.

[0041] FIGS. 2A and 2B show two different schematic diagrams of direct charge transfer (DCT) coupled filter 200. As depicted below, the circuitry illustrated in FIGS. 2A and 2B can be shown to have a transfer function representative of a first-order filtering operation in discrete time; consequently, the circuitry depicted in FIGS. 2A and 2B is referred to herein as a “DCT coupled filter.” FIG. 2A depicts the switching and logic of DCT coupled filter 200. FIG. 2B illustrates an implementation of the circuitry of DCT coupled filter 200.

[0042] FIG. 2A shows the switching and logic of DCT coupled filter 200. During a first phase of operation Φ1, switch 230 is closed and hence the filter input terminal Vin(z) is connected to a first terminal of sampling capacitor Cdac 240 (e.g., a sampling capacitor of a digital to analog converter (DAC) as shown and described below). Also during the first phase of operation Φ1, switch 232 is closed and switch 236 is open, so the second terminal of the sampling capacitor Cdac 240 is connected to ground. During the first phase of operation Φ1, wherein the sampling capacitor Cdac 240 is acquiring charge, both switch 236 and 238 are open, so both operational amplifier (opamp) 202 and the feedback capacitor Cfb 242 are decoupled from the sampling capacitor Cdac 240. Consequently, during the first phase of operation Φ1, the sampling capacitor Cdac 240 does not appear as a load to opamp 202. In addition, during the first phase of operation Φ1, switch 234 is open.

[0043] During a second phase of operation Φ2, switch 230 is open and hence the first terminal of the sampling capacitor Cdac 240 has been decoupled from the filter input terminal Vin(z) and instead coupled with the operational amplifier 202 output. Also during the second phase of operation Φ2, switch 232 is open and switch 236 is closed, so the second terminal of the sampling capacitor Cdac 240 has been decoupled from ground and instead coupled with the feedback capacitor Cfb 242. In addition, during the second phase of operation Φ2, switch 234 is closed.

[0044] The DCT logic and switching shown in FIG. 2A realize a first-order filter transfer function, while avoiding connection of sampling capacitance in a configuration in which opamp 202 sees the aggregate capacitance as a load through the feedback network. Specifically, when DCT coupled filter 200 is analyzed, the analysis reveals that DCT coupled filter 200 has a transfer function of:
Vout(z)/Vin(z)=z^−1/2/((1+Cfb/Cdac)−(Cfb/Cdac)*z⁻¹)
which those skilled in the art will appreciate is representative of a first-order filtering operation in discrete time. Consequently, circuitry depicted in FIGS. 2A and 2B is referred to herein as a “DCT coupled filter” 200 having a filter input terminal Vin(z) and a filter output terminal Vout(z).

[0045] Unlike traditional RC-equivalent switched-capacitor networks in which an opamp (e.g., opamp 202) supplies a charging current for an integrating capacitor (e.g., feedback capacitor Cfb), in DCT coupled filter 200 of FIGS. 2A and 2B, during the second phase of operation Φ2 the sampling capacitor Cdac 240 connects in parallel with the integrating capacitance Cfb, passively sharing the input charge. Consequently, opamp 202 of DCT coupled filter 200 is now only tasked to drive the bottom-plate capacitance of the feedback capacitor, which is negligible in many modern wafer processes that offer metal-insulator-metal capacitors. Those skilled in the art will appreciate that this technique can save a substantial amount of power.

[0046] FIG. 2B illustrates one implementation of the circuitry of DCT coupled filter 200. In FIG. 2B the switches 230, 232, 234, 236, and 238 shown in FIG. 2A are implemented by transistors. The switches of FIG. 2B operate in the same fashion as their like-numbered counterparts of FIG. 2A. Switches described herein may be implemented as NMOS, PMOS, or a parallel combination of one NMOS and one PMOS transistor.

[0047] B. DCT Coupled Filter Having CDS Switching Matrix

[0048] In one embodiment of the subject matter of the present application, if the circuitry of DCT coupled filter 200 is augmented with what will be referred to herein as a correlated double sampling (CDS) technique switching matrix, DCT coupled filter 200 can be utilized even in applications that are highly noise sensitive. As an aid to understanding, prior to describing the DCT coupled filter augmented by the CDS switching matrix circuitry, the CDS technique will first be discussed in isolation.

1. CDS Technique

[0049] The CDS technique can be viewed as an autozeroing technique that can be used to eliminate opamp offset and finite opamp gain effects in switched-capacitor circuits. Why this is so will become apparent below.

[0050] FIGS. 3A and 3B show two different schematic diagrams of inverting switched-capacitor circuitry 300 which illustrate the correlated double sampling (CDS) technique. Although inverting switched-capacitor circuitry 300 of FIGS. 3A and 3B may appear superficially similar to other circuitry described elsewhere herein, the circuitry of FIGS. 3A and 3B is different than that circuitry shown elsewhere herein.

[0051] FIG. 3A shows inverting switched-capacitor circuitry 300 depicting the switching and logic of the CDS technique. During a second phase of operation Φ2, both switches 332 and 341 are closed and hence a first terminal of the correlated double sampling capacitor Ccds 344 is coupled to ground and a second terminal of the correlated double sampling capacitor Ccds 344 is coupled to both the negative input of opamp 320 and the feedback capacitor Cfb 342. This coupling allows the difference between error voltage Ve, at the negative input of opamp 320, and ground to be stored, or sampled, on the correlated double sampling capacitor Ccds 344. During a first phase of operation Φ1, switches 330, 334, and 336 are closed and switches 335, 332, and 341 are open. Hence, during the first phase of operation Φ1, wherein Vin is coupled to the sampling capacitor Cdac and wherein the integrator composed of Cfb and opamp 320 integrates, the low frequency components of Ve will not have changed much, resulting in the terminal of Ccds 344 opposite the opamp acting as a modified virtual ground 350 from which the low frequency components of Ve at the op-amp virtual ground 348 have been cancelled out. Heuristically, the foregoing described operation can be understood as follows: during the second phase of operation Φ2, the charge on correlated double sampling capacitor Ccds 344 will interact with the charge on feedback capacitor Cfb 342 such that on the next integrating phase of the two-clock waveform Φ1 in this case), the voltage on the feedback capacitor voltage Cfb 342 has been adjusted such that the error voltage of the operational amplifier, Ve(z), will effectively be “cancelled out,” so that the overall interaction will be “as if” the operational amplifier 320 were operating with substantially no error voltage. Hence, the CDS technique automatically “zeros out” the functioning of the overall operational amplifier technique, which is why CDS is referred to in the art as an “autozeroing” technique. With respect to inverting switched-capacitor circuitry 300, Vout(z) may be derived as follows:
Vout(z)=(−(Cdac/Cfb)*Vin(z)/(1−z⁻¹))−((1+(Cdac/Cfb))*(Ve(1−z^−1/2))/(1−z⁻¹)).

[0052] FIG. 3B illustrates one implementation of inverting switched-capacitor circuitry 300 wherein the CDS technique is achieved. In FIG. 3B the switches 330, 332, 334, 335, 336, and 341 shown in FIG. 3A are implemented by transistors. The switches of FIG. 3B operate in the same fashion as their like-numbered counterparts of FIG. 3A.

[0053] When inverting switched-capacitor circuitry 300 is analyzed, the analysis shows the transfer function of the error voltage Ve to the output is as follows (note that the cancellation is described in relation to the integrating phase of the two-clock waveform Φ1 as described in relation to FIGS. 3A and 3b)). First, as described above, Vout(z) may be derived as follows:
Vout(z)=(−(Cdac/Cfb)*Vin(z)/(1−z⁻¹))−((1+(Cdac/Cfb))*(Ve(1−z^−1/2))/(1−z⁻¹)).

[0054] Then, noting that:

[0055] Ve(n)=Vos+Vnoise(n)+(Vout(n)/A), where A is the low-frequency gain of the operating amplifier, rearranging terms and taking the Z-transform yields a transfer function of the error voltage Ve to the output is as follows

 Vouterror(z)=(1+Cdac/Cfb)*(Vnoise(1−z^−(1/2)))+(Vout/A)*(1−z^−(1/2)),

[0056] which is representative of a first-order differentiation operation performed on the input-referred opamp noise voltage, as well as the finite-gain effects of opamp 320, thereby increasing the effective DC gain of the integrator. That is, since, as has been described, the dominant portions of Ve change relatively slowly, the differentiation produced by the CDS technique tends to significantly reduce the input-referred opamp noise voltage. Consequently, as seen from the foregoing, the CDS technique may be utilized to reduce the op-amp input-referred 1/f noise, in applications where such noise is a problem. The 1/f noise is concentrated at low frequency and is in fact one dominant portion of Ve of concern.
2. DCT Coupled Filter Augmented with CDS Switching Matrix

[0057] FIGS. 4A, 4B, and 4C illustrate circuitry 400 of a DCT coupled filter augmented with a CDS switching matrix (circuitry that performs a CDS operation). The circuitry 400 of FIG. 4A includes switches 430, 432, 434, 436, 438, and 441. The switches are illustrated as transistors. The circuitry 400 also includes capacitors Cdac 440, Ccds 444, and Cfb 442. Because the circuitry 400 of FIGS. 4A, 4B, and 4C achieves both DCT and CDS techniques, and because some of the circuitry serves “double duty” as both DCT and CDS circuitry, it is easier to discuss each “aspect” of the circuitry of FIG. 4A in isolation.

[0058] FIG. 4B shows the circuitry of FIG. 4A, wherein those switches and components which provide a DCT coupled filter analogous to DCT coupled filter 200 of FIG. 2B are noted. Specifically, comparison of the circuitry of FIG. 4B with the circuitry of DCT coupled filter 200 depicted in FIG. 2B shows those switches and components which provide the DCT capability. Those switches are labeled in FIG. 4B as switches and components having reference numerals ending in “DCT”. The switches and components that provide the DCT capability function analogously to the like components shown and described in relation to FIGS. 2A and 2B.

[0059] FIG. 4C depicts the circuitry of FIG. 4A, wherein those switches and components which augment the operation of the DCT coupled filter by the CDS technique are noted. Specifically, comparison of the circuitry of FIG. 4C with the CDS circuitry depicted and described in relation to FIG. 3B shows those switches and components which provide the CDS autozeroing. Those switches and components are labeled in FIG. 4C as switches and components having reference numerals ending in “CDS”. Those skilled in the art will appreciate that the respective phases of the CDS circuitry shown in FIG. 4C are notated as the reverse of the similar functioning switches in FIG. 3B. The switches and components that provide the CDS capability function analogously to the like components shown and described in relation to FIGS. 3A and 3B, and are not be explicitly re-described here for sake of brevity

[0060] C. Analog Postfilter Composed of Cascaded DCT Coupled Filters

[0061] An analog postfilter of a DAC should preferably be of at least the order of the quantization noise shaping utilized by a digital noise shaper to attenuate out of band noise. In many applications, this shaping is second order. Accordingly, as has been shown above, insofar as that DCT coupled filter 200 provides a first order filtering transfer function, DCT coupled filter 200, in the absence of the subject matter of the present application, has historically not been recognized as viable for use as a complete analog postfilter. However, in one implementation of the subject matter described herein, DCT coupled filter 200 is utilized to create second order, or higher, filters by using cascaded DCT coupled filters 200.

1. Second Order Analog Postfilter

[0062] FIG. 5 shows a DAC system 500 having analog postfilters composed of cascades of DCT coupled filters augmented by CDS switching matrices. Second order analog postfilter 502 is representative of substantially all analog postfilters in FIG. 7. Second order analog postfilter 502 is composed of a cascade of DCT coupled filter augmented by CDS switching matrix 504 and DCT coupled filter augmented by CDS switching matrix 506. Comparison of the circuitry of the individual DCT coupled filters augmented by CDS switching matrices 504, 506 with the circuitry shown and described in relation to FIGS. 4A, 4B, and 4C shows that such individual DCT coupled filters augmented by CDS switching matrices are substantially analogous to the circuitry 400 shown and described in relation to FIGS. 4A, 4B, and 4C. DCT coupled filter augmented by CDS switching matrix 506 is shown having a dual common mode switch matrix” circuitry (discussed below), which is optional in one implementation. In DCT coupled filter augmented by CDS switching matrix 506, certain switches are shown as being part of 16 level switch arrays 508, 510, 512, and 514. With respect to the functioning of the Φ1 and Φ2 switch notation, the notation of at least some of the circuitry in FIG. 5 has been reversed from such notation as used in FIGS. 4A, 4B, and 4C. Following such reversal in notation is well within the ambit of one having ordinary skill in the art, especially in light of this explanatory note. The functioning of the CDS switching matrix 504 in cascade with DCT coupled filter augmented by CDS switching matrix 506 will not be explicitly described here. Understanding such functioning of the cascaded circuits can be understood in light of the discussion of the circuitry of FIGS. 4A, 4B, and 4C, above.

[0063] It is to be understood that, although DCT coupled filters augmented by CDS switching matrices are shown and described in relation to FIG. 5, in some implementations DCT coupled filters 400 can be cascaded in the absence of the CDS switching matrices (e.g., via use of DCT coupled filters 200). That is, in some noise-tolerant applications DCT coupled filters 200 function sufficiently well that the CDS switching matrices augmentations of such cascaded filters are not utilized in such applications. With respect to of FIG. 5, Opamp2 does not have a switched output. This is due to the fact that Opamp2 is used to drive continuous time (analog) circuitry.

[0064] It has been discovered that in many applications, the foregoing described cascaded DCT coupled filters work well, and that the foregoing described cascaded DCT coupled augmented by the CDS switching matrices work even better. However, it has also been discovered that in certain other applications, such as DACs implemented in monolithic integrated circuits, the performance of such cascaded DCT coupled filters augmented by the CDS switching matrices can be improved. Specifically, the performance can be improved by providing circuitry that allows the common mode voltage used by a DAC to be significantly different than the common mode voltage used by an operational amplifier circuit within the same integrated circuit, or within a monolithic integrated circuit. This circuitry, devised to alleviate the discovered common mode implementation difficulty, will be referred to herein as “dual common mode switch matrix” circuitry.

[0065] D. Dual Common Mode Switch Matrix Circuitry Coupling DAC With Analog Postfilter

[0066] FIG. 5 depicts encircled on the schematic, switches that function as dual common mode switch matrix circuitry that separates the common mode reference voltage of the DAC from the common mode reference voltage of the operational amplifier circuitry. On a first phase Φ1 of operation, switches S1 and S2 connect the bottom nodes of the DAC sampling capacitors Cdac to the DAC common mode reference, while switches S5 and S6 connect the CDS capacitors Ccds to the opamp common mode voltage reference. Thus, during the first phase Φ1 of operation, switches S3 and S4 are open, thereby separating the DAC common mode reference from the opamp common mode voltage reference.

[0067] On phase Φ2 of operation, the DAC sampling capacitors Cdac and the CDS capacitors Ccds are disconnected from their respective reference voltages and are thereafter connected through switches S3 and S4 to realize the DCT charge-sharing operation shown and described above.

[0068] E. Postfilter Droop Compensation of Analog Postfilter Composed of Cascaded DCT Coupled Filters

[0069] When the foregoing cascaded DCT coupled filters augmented by the CDS and dual common mode switching matrices were implemented, it was discovered that in most applications such circuitry functions exceptionally well. However, it was also discovered that, in certain other applications, such as audio applications, the performance can be improved by providing logic that alleviates what will be referred to herein as “passband droop” of the signal emerging from an analog postfilter.

[0070] FIG. 6A shows one illustration of the magnitude response of an analog postfilter wherein passband droop is present. As can be seen in FIG. 6A, the term “passband droop” indicates that an analog postfilter does not filter sharply at its cutoff frequencies, but rather rounds off, or “droops,” at its cutoff frequencies.

[0071] It has been found that in certain applications, such as audio applications, overall performance of systems can be significantly improved by use of “postfilter droop compensation logic,” typically located in an upsampling and digital interpolation filtering unit (see FIG. 7). This postfilter droop compensation logic introduces predistortion in the input signal such that the output signal emerging from an analog postfilter does not experience significant postfilter droop.

[0072] FIGS. 6B-6C respectively show illustrations of magnitude and phase responses of one implementation of postfilter droop compensation logic. This magnitude and phase responses are empirically or numerically chosen by the system designer to correct passband droop, such as that shown in FIG. 6A.

[0073] FIG. 6D shows a magnitude response of the analog postfilter shown and described in relation to FIG. 6A, when an input signal has been subjected to the postfilter droop compensation logic shown and described in relation to FIGS. 6B-C. As can be seen, implementation of postfilter droop compensation filter logic has functioned such that passband droop is no longer present in the output of the analog postfilter.

[0074] With reference now to FIG. 7, shown is DAC architecture 700, which is similar to DAC architecture 100 shown and described in FIG. 1, but which has been modified. Specifically, depicted is that analog postfiltering of DAC 118 is now being provided by second order analog postfilter 502, which as shown is similar to the analog postfilters shown and described in relation to FIGS. 4A, 4B, 4C, and 5 above.

[0075] Further illustrated is that upsampling and digital interpolation filtering unit 104 has been modified to become upsampling and digital interpolation filtering unit with postfilter droop compensation unit 704, which now contains postfilter droop compensation logic. Essentially, this postfilter droop compensation logic “pre-distorts” the digital input signal such that, when the ultimate output signal emerges from analog postfilter 700, the passband droop is no longer present (e.g., as illustrated in FIG. 6D). Postfilter droop compensation logic may be implemented via any one of various “pre-distortion” techniques well known to those having ordinary skill in the art.

[0076] The implementations, discussed above, described use of a DCT coupled filter having unity gain. In other implementations, other gains are employed. For example, FIGS. 8A-8D illustrate such alternate implementations, which are not described exhaustively for sake of brevity.

[0077] FIG. 8A shows a DCT coupled filter 800 that has gain enhancement circuitry. During a first phase of operation Φ1, switches 830, 832, 862, and 868 are closed. During a second phase of operation Φ2, the switches 836, 838, 864, and 866 are closed. The functioning of the various components of the DCT coupled filter 800 may be understood by comparison with analogous components, discussed at length above.

[0078] FIG. 8B shows a DCT coupled filter 850 that has gain enhancement circuitry that uses switch sharing. During a first phase of operation Φ1, switches 830, 832, and 862 are closed. During a second phase of operation Φ2, the switches 836, 838, and 864 are closed. The functioning of the various components of the DCT coupled filter 850 may be understood by comparison with analogous components, discussed at length above.

[0079] FIG. 8C shows a DCT coupled filter 852 that has gain enhancement circuitry that uses both switch sharing and the CDS technique. During a first phase of operation Φ1, switches 830, 832, 862, and 874 are closed. During a second phase of operation Φ2, the switches 838, 864, and 870 are closed. The functioning of the various components of the DCT coupled filter 852 may be understood by comparison with analogous components, discussed at length above.

[0080] FIG. 8D shows a DCT coupled filter 854 that has gain enhancement circuitry that uses switch sharing, the CDS technique, and the dual common mode reference technique. During a first phase of operation Φ1, switches 830, 862, 874, 876, and 878 are closed. During a second phase of operation Φ2, the switches 838, 864, 870, and 880 are closed. The functioning of the various components of the DCT coupled filter 854 may be understood by comparison with analogous components, discussed at length above.

[0081] FIG. 8A illustrates an implementation of the circuitry of a DCT coupled filter having gain enhancement. Inspection of the charge transfer within the circuit of FIG. 8A reveals that, in the Z-domain, the circuit transfer function can be derived as follows:
(Cfb/+Cdac)·Vout(z)=Cfb·Vout(z)·z⁻¹+(Cdac+Cg)·Vin(z)
$\frac{\mathrm{Vout}\left(z\right)}{\mathrm{Vin}\left(z\right)}=\frac{\left(1+\frac{\mathrm{Cg}}{\mathrm{Cdac}}\right)}{\left(\left(1+\frac{\mathrm{Cfb}}{\mathrm{Cdac}}\right)-\frac{\mathrm{Cfb}}{\mathrm{Cdac}}·z^{-1}\right)}$

[0082] The DC gain of the circuit is non-unity; however, this increase in flexibility is obtained at the cost of an additional loading capacitor which will require the opamp power dissipation to increase as Cg increases. Analysis shows that the switched-capacitor noise of this setup is similar to the original DCT case described above. Other transfer functions for the filters shown in FIGS. 8B-8D can be likewise derived using circuit analysis techniques.

[0083] Those having ordinary skill in the art will recognize that the state of the art has progressed to the point where there is little distinction left between hardware and software implementations of aspects of systems; the use of hardware or software is generally, but not always, a design choice representing cost vs. efficiency tradeoffs. Those having ordinary skill in the art will appreciate that there are various vehicles by which aspects of processes and/or systems described herein can be effected (e.g., hardware, software, and/or firmware), and that the preferred vehicle will vary with the context in which the processes and/or systems are deployed. For example, if an implementer determines that speed and accuracy are paramount, the implementer may opt for a hardware and/or firmware vehicle; alternatively, if flexibility is paramount, the implementer may opt for a solely software implementation; or, yet again alternatively, the implementer may opt for some combination of hardware, software, and/or firmware. Hence, there are several possible vehicles by which aspects of the processes described herein may be effected, none of which is inherently superior to the other in that any vehicle to be utilized is a choice dependent upon the context in which the vehicle will be deployed and the specific concerns (e.g., speed, flexibility, or predictability) of the implementer, any of which may vary.

[0084] The foregoing detailed description has set forth various embodiments of the devices and/or processes via the use of block diagrams, flowcharts, and examples. Insofar as such block diagrams, flowcharts, and examples contain one or more functions and/or operations, it will be understood that each function and/or operation within such block diagrams, flowcharts, or examples can be implemented, individually and/or collectively, by a wide range of hardware, software, firmware, or virtually any combination thereof. In one embodiment, the present invention may be implemented via Application Specific Integrated Circuits (ASICs). However, those skilled in the art will recognize that the embodiments disclosed herein, in whole or in part, can be equivalently implemented in standard Integrated Circuits, as one or more computer programs running on one or more computers (e.g., as one or more programs running on one or more computer systems), as one or more programs running on one or more controllers (e.g., microcontrollers) as one or more programs running on one or more processors (e.g., microprocessors, or digital signal processors), as firmware, or as virtually any combination thereof, and that designing the circuitry and/or writing the code for the software and or firmware would be well within the skill of one of ordinary skill in the art in light of this disclosure. In addition, those skilled in the art will appreciate that the mechanisms of the present invention are capable of being distributed as a program product in a variety of forms, and that an illustrative embodiment of the present invention applies equally regardless of the particular type of signal bearing media used to actually carry out the distribution. Examples of signal bearing media include, but are not limited to, the following: recordable type media such as floppy disks, hard disk drives, CD ROMs, digital tape, and computer memory; and transmission type media such as digital and analog communication links using TDM or IP based communication links (e.g., packet links).

[0085] In a general sense, those skilled in the art will recognize that the various embodiments described herein which can be implemented, individually and/or collectively, by a wide range of hardware, software, firmware, or any combination thereof can be viewed as being composed of various types of “electrical circuitry.” Consequently, as used herein “electrical circuitry” includes, but is not limited to, electrical circuitry having at least one discrete electrical circuit, electrical circuitry having at least one integrated circuit, electrical circuitry having at least one application specific integrated circuit, electrical circuitry forming a general purpose computing device configured by a computer program (e.g., a general purpose computer configured by a computer program which at least partially carries out processes and/or devices described herein, or a microprocessor configured by a computer program which at least partially carries out processes and/or devices described herein), electrical circuitry forming a memory device (e.g., forms of random access memory), and electrical circuitry forming a communications device (e.g., a modern, communications switch, or optical-electrical equipment).

[0086] Those skilled in the art will recognize that it is common within the art to describe devices and/or processes in the fashion set forth herein, and thereafter use standard engineering practices to integrate such described devices and/or processes into systems which are typically partly analog and partly digital. That is, the devices and/or processes described herein can be integrated into analog and partly digital systems via a reasonable amount of experimentation well within the ambit of those having an ordinary amount of skill in the art. In particular, while the subject matter of the present application has been described herein in the context of an audio application, those having ordinary skill in art will appreciate that the subject matter described herein. For example, the subject matter described herein may be usefully employed in mobile communications devices (e.g., wireless phones, pagers, personal computers, embedded computers, and the like), fixed communications devices (e.g., wireless base stations and land line communications systems such as optical or electrical LANS, WANS, analog communications, analog networks and the like), recording devices (e.g., video or audio recording devices and the like), computational devices (e.g., computing systems such as personal, mini, workstation, and mainframe computing systems and the like), and sensing devices (e.g., infrared, ultraviolet, radio frequency, microwave sensing devices and the like).

[0087] The foregoing described embodiments depict different components contained within, or connected with, different other components. It is to be understood that such depicted architectures are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being “operably connected”, or “operably coupled”, to each other to achieve the desired functionality.

[0088] While particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that, based upon the teachings herein, changes and modifications may be made without departing from this invention and its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications as are within the true spirit and scope of this invention. Furthermore, it is to be understood that the invention is solely defined by the appended claims. It will be understood by those within the art that, in general, terms used herein, and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as “open” terms (e.g., the term “including” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having at least,” the term “includes” should be interpreted as “includes but is not limited to,” etc.). It will be further understood by those within the art that if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases “at least one” and “one or more” to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim recitation to inventions containing only one such recitation, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and/or “an” should typically be interpreted to mean “at least one” or “one or more”); the same holds true for the use of definite articles used to introduce claim recitations. In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should typically be interpreted to mean at least the recited number (e.g., the bare recitation of “two recitations,” without other modifiers, typically means at least two recitations, or two or more recitations).

[0089] From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.