Apparatus for adaptive reverse power control for spread-spectrum communications

[0001] This application is a continuation-in-part to U.S. patent application Ser. No. 08/956,740 filed on Oct. 23, 1997, which issued on Apr. 10, 2001 U.S. Pat. No. 6,215,778; which is a continuation of U.S. patent application Ser. No. 08/669,775 filed on Jun. 27, 1996, which issued on Aug. 25, 1998 as U.S. Pat. No. 5,799,010; which claims benefit of U.S. Provisional Application No. 60/000,775 filed on Jun. 30, 1995. This application is also a continuation-in-part to U.S. patent application Ser. No. 09/721,034 filed on Nov. 22, 2000; which is a continuation of U.S. patent application Ser. No. 09/003,104 filed on Jan. 6, 1998, which issued on Jan. 30, 2001 as U.S. Pat. No. 6,181,949; which is a continuation of U.S. patent application Ser. No. 08/670,162 filed on Jun. 27, 1996, which issued on Nov. 24, 1998 as U.S. Pat. No. 5,841,768. This application is also a continuation-in-part to U.S. patent application Ser. No. 09/304,286 filed on May 3, 1999 now U.S. Pat. No. 6,252,886; which is a continuation of U.S. patent application Ser. No. 08/671,068 filed on Jun. 27, 1996, which issued on Aug. 17, 1999 as U.S. Pat. No. 5,940,382. This application is also a continuation-in-part to U.S. patent application Ser. No. 09/354,042 filed on July 15, 1999; which is a continuation of U.S. patent application Ser. No. 08/671,067 filed Jun. 27, 1996, which issued on Sep. 14, 1999 as U.S. Pat. No. 5,953,346. This application is also a continuation-in-part to U.S. patent application Ser. No. 08/670,160 filed on Jun. 27, 1996. This application is also a continuation of U.S. patent application Ser. No. 09/079,600 filed on May 15, 1998; which is a continuation of U.S. patent application Ser. No. 08/671,221 filed on Jun. 27, 1996, which issued on May 19, 1998 as U.S. Pat. No. 5,754,803.

[0002] The present invention generally pertains to Code Division Multiple Access (CDMA) communications, also known as spread-spectrum communications. More particularly, the present invention pertains to a system and method for providing a high capacity, CDMA communications system which provides for one or more simultaneous user bearer channels over a given radio frequency, allowing dynamic allocation of bearer channel rate while rejecting multipath interference.

[0003] Providing quality telecommunication services to user groups which are classified as remote, such as rural telephone systems and telephone systems in underdeveloped countries, has proven to be a challenge in recent years. These needs have been partially satisfied by wireless radio services, such as fixed or mobile frequency division multiplex (FDM) systems, frequency division multiple access (FDMA) systems, time division multiplex (TDM) systems, time division multiple access (TDMA) systems, combination frequency and time division (FD/TDMA) systems, and other land mobile radio systems. Usually, these remote services are faced with more potential users than can be supported simultaneously by their frequency or spectral bandwidth capacity.

[0004] Recognizing these limitations, recent advances in wireless communications have used spread spectrum modulation techniques to provide simultaneous communication by multiple users. Spread spectrum modulation refers to modulating an information signal with a spreading code signal; the spreading code signal being generated by a code generator where the period Tc of the spreading code is substantially less than the period of the information data bit or symbol signal. The code may modulate the carrier frequency upon which the information has been sent, called frequency-hopped spreading, or may directly modulate the signal by multiplying the spreading code with the information data signal, called direct-sequence (DS) spreading. Spread-spectrum modulation produces a signal with bandwidth substantially greater than that required to transmit the information signal. Synchronous reception and despreading of the signal at the receiver recovers the original information. A synchronous demodulator in the receiver uses a reference signal to synchronize the despreading circuits to the input spread-spectrum modulated signal to recover the carrier and information signals. The reference signal can be a spreading code which is not modulated by an information signal. Such use of a synchronous spread-spectrum modulation and demodulation for wireless communication is described in U.S. Pat. No. 5,228,056 entitled SYNCHRONOUS SPREAD-SPECTRUM COMMUNICATIONS SYSTEM AND METHOD by Donald L. Schilling, which techniques are incorporated herein by reference.

[0005] Spread-spectrum modulation in wireless networks offers many advantages because multiple users may use the same frequency band with minimal interference to each user's receiver. Spread-spectrum modulation also reduces effects from other sources of interference. In addition, synchronous spread-spectrum modulation and demodulation techniques may be expanded by providing multiple message channels for a single user, each spread with a different spreading code, while still transmitting only a single reference signal to the user. Such use of multiple message channels modulated by a family of spreading codes synchronized to a pilot spreading code for wireless communication is described in U.S. Pat. No. 5,166,951 entitled HIGH CAPACITY SPREAD-SPECTRUM CHANNEL by Donald L. Schilling, which is incorporated herein by reference.

[0006] One area in which spread-spectrum techniques are used is in the field of mobile cellular communications to provide personal communication services (PCS). Such systems desirably support large numbers of users, control Doppler shift and fade, and provide high speed digital data signals with low bit error rates. These systems employ a family of orthogonal or quasi-orthogonal spreading codes, with a pilot spreading code sequence synchronized to the family of codes. Each user is assigned one of the spreading codes as a spreading function. Related problems of such a system are: supporting a large number of users with the orthogonal codes, handling reduced power available to remote units, and handling multipath fading effects. Solutions to such problems include using phased-array antennas to generate multiple steerable beams and using very long orthogonal or quasi-orthogonal code sequences. These sequences may be reused by cyclic shifting of the code synchronized to a central reference and diversity combining of multipath signals. Such problems associated with spread spectrum communications, and methods to increase the capacity of a multiple access, spread-spectrum system are described in U.S. Pat. No. 4,901,307 entitled SPREAD SPECTRUM MULTIPLE ACCESS COMMUNICATION SYSTEM USING SATELLITE OR TERRESTRIAL REPEATERS by Gilhousen et al. which is incorporated herein by reference.

[0007] The problems associated with the prior art systems focus around reliable reception and synchronization of the receiver despreading circuits to the received signal. The presence of multipath fading introduces a particular problem with spread spectrum receivers in that a receiver must somehow track the multipath components to maintain code-phase lock of the receiver's despreading means with the input signal. Prior art receivers generally track only one or two of the multipath signals, but this method is not satisfactory because the combined group of low power multipath signal components may actually contain far more power than the one or two strongest multipath components. The prior art receivers track and combine the strongest components to maintain a predetermined bit error rate (BER) of the receiver. Such a receiver is described, for example, in U.S. Pat. No. 5,109,390 entitled DIVERSITY RECEIVER IN A CDMA CELLULAR TELEPHONE SYSTEM by Gilhousen et al. A receiver that combines all multipath components, however, is able to maintain the desired BER with a signal power that is lower than that of prior art systems because more signal power is available to the receiver. Consequently, there is a need for a spread spectrum communication system employing a receiver that tracks substantially all of the multipath signal components, so that substantially all multipath signals may be combined in the receiver, and hence the required transmit power of the signal for a given BER may be reduced.

[0008] Another problem associated with multiple access, spread-spectrum communication systems is the need to reduce the total transmitted power of users in the system, since users may have limited available power. An associated problem requiring power control in spread-spectrum systems is related to the inherent characteristic of spread-spectrum systems that one user's spread-spectrum signal is received by another user's receiver as noise with a certain power level. Consequently, users transmitting with high levels of signal power may interfere with other users' reception. Also, if a user moves relative to another user's geographic location, signal fading and distortion require that the users adjust their transmit power level to maintain a particular signal quality. At the same time, the system should keep the power that the base station receives from all users relatively constant. Finally, because it is possible for the spread-spectrum system to have more remote users than can be supported simultaneously, the power control system should also employ a capacity management method which rejects additional users when the maximum system power level is reached.

[0009] Prior spread-spectrum systems have employed a base station that measures a received signal and sends an adaptive power control (APC) signal to the remote users. Remote users include a transmitter with an automatic gain control (AGC) circuit which responds to the APC signal. In such systems the base station monitors the overall system power or the power received from each user, and sets the APC signal accordingly. Such a spread-spectrum power control system and method is described in U.S. Pat. No. 5,299,226 entitled ADAPTIVE POWER CONTROL FOR A SPREAD SPECTRUM COMMUNICATION SYSTEM AND METHOD, and U.S. Pat. No. 5,093,840 entitled ADAPTIVE POWER CONTROL FOR A SPREAD SPECTRUM TRANSMITTER, both by Donald L. Schilling and incorporated herein by reference. This open loop system performance may be improved by including a measurement of the signal power received by the remote user from the base station, and transmitting an APC signal back to the base station to effectuate a closed loop power control method. Such closed loop power control is described, for example, in U.S. Pat. No. 5,107,225 entitled HIGH DYNAMIC RANGE CLOSED LOOP AUTOMATIC GAIN CONTROL CIRCUIT to Charles E. Wheatley, III et al. and incorporated herein by reference.

[0010] These power control systems, however, exhibit several disadvantages. First, the base station must perform complex power control algorithms, increasing the amount of processing in the base station. Second, the system actually experiences several types of power variation: variation in the noise power caused by the variation in the number of users and variations in the received signal power of a particular bearer channel. These variations occur with different frequency, so simple power control algorithms can be optimized to compensate for only one of the two types of variation. Finally, these power algorithms tend to drive the overall system power to a relatively high level. Consequently, there is a need for a spread-spectrum power control method that rapidly responds to changes in bearer channel power levels, while simultaneously making adjustments to all users' transmit power in response to changes in the number of users. Also, there is a need for an improved spread-spectrum communication system employing a closed loop power control system which minimizes the system's overall power requirements while maintaining a sufficient BER at the individual remote receivers. In addition, such a system should control the initial transmit power level of a remote user and manage total system capacity.

[0011] Spread-spectrum communication systems desirably should support large numbers of users, each of which has at least one communication channel. In addition, such a system should provide multiple generic information channels to broadcast information to all users and to enable users to gain access to the system. Using prior art spread-spectrum systems this could only be accomplished by generating large numbers of spreading code sequences.

[0012] Further, spread-spectrum systems should use sequences that are orthogonal or nearly orthogonal to reduce the probability that a receiver locks to the wrong spreading code sequence or phase. The use of such orthogonal codes and the benefits arising therefrom are outlined in U.S. Pat. No. 5,103,459 entitled SYSTEM AND METHOD FOR GENERATING SIGNAL WAVEFORMS IN A CDMA CELLULAR TELEPHONE SYSTEM, by Gilhousen et al. and U.S. Pat. No. 5,193,094 entitled METHOD AND APPARATUS FOR GENERATING SUPER-ORTHOGONAL CONVOLUTIONAL CODES AND THE DECODING THEREOF, by Andrew J. Viterbi, both of which are incorporated herein by reference. However, generating such large families of code sequences with such properties is difficult. Also, generating large code families requires generating sequences which have a long period before repetition. Consequently, the time a receiver takes to achieve synchronization with such a long sequence is increased. Prior art spreading code generators often combine shorter sequences to make longer sequences, but such sequences may no longer be sufficiently orthogonal. Therefore, there is a need for an improved method for reliably generating large families of code sequences that exhibit nearly orthogonal characteristics and have a long period before repetition, but also include the benefit of a short code sequence that reduces the time to acquire and lock the receiver to the correct code phase. In addition, the code generation method should allow generation of codes with any period, since the spreading code period is often determined by parameters used such as data rate or frame size.

[0013] Another desirable characteristic of spreading code sequences is that the transition of the user data values occur at a transition of the code sequence values. Since data typically has a period which is divisible by 2^N, such a characteristic usually requires the code-sequence to be an even length of 2^N. However, code generators, as is well known in the art, generally use linear feedback shift registers which generate codes of length 2^N−1. Some generators include a method to augment the generated code sequence by inserting an additional code value, as described, for example, in U.S. Pat. No. 5,228,054 entitled POWER-OF-TWO LENGTH PSEUDONOISE SEQUENCE GENERATOR WITH FAST OFFSET ADJUSTMENT by Timothy Rueth et al. and incorporated herein by reference. Consequently, the spread-spectrum communication system should also generate spreading code sequences of even length.

[0014] Finally, the spread-spectrum communication system should be able to handle many different types of data, such as FAX, voiceband data and ISDN, in addition to traditional voice traffic. To increase the number of users supported, many systems employ encoding techniques such as ADPCM to achieve “compression” of the digital telephone signal. FAX, ISDN and other data, however, require the channel to be a clear channel. Consequently, there is a need for a spread spectrum communication system that supports compression techniques that also dynamically modify the spread spectrum bearer channel between an encoded channel and a clear channel in response to the type of information contained in the user's signal.

[0015] The present invention is embodied in a multiple access, spread spectrum communication system which processes a plurality of information signals received simultaneously over telecommunication lines for simultaneous transmission over a radio frequency (RF) channel as a code-division-multiplexed (CDM) signal. The system includes a radio carrier station (RCS) which receives a call request signal that corresponds to a telecommunication line information signal, and a user identification signal that identifies a user to which the call request and information signal are addressed. The receiving apparatus is coupled to a plurality of code division multiple access (CDMA) modems, one of which provides a global pilot code signal and a plurality of message code signals, and each of the CDMA modems combines one of the plurality of information signals with its respective message code signal to provide a spread-spectrum processed signal. The plurality of message code signals of the plurality of CDMA modems are synchronized to the global pilot code signal. The system also includes assignment apparatus that is responsive to a channel assignment signal for coupling the respective information signals received on the telecommunication lines to indicated ones of the plurality of modems. The assignment apparatus is coupled to a time-slot exchange means. The system further includes a system channel controller coupled to a remote call-processor and to the time-slot exchange means. The system channel controller is responsive to the user identification signal, to provide the channel assignment signal. In the system, an RF transmitter is connected to all of the modems to combine the plurality of spread-spectrum processed message signals with the global pilot code signal to generate a CDM signal. The RF transmitter also modulates a carrier signal with the CDM signal and transmits the modulated carrier signal through an RF communication channel.

[0016] The transmitted CDM signal is received from the RF communication channel by a subscriber unit (SU) which processes and reconstructs the transmitted information signal assigned to the subscriber. The SU includes a receiving means for receiving and demodulating the CDM signal from the carrier. In addition, the SU comprises a subscriber unit controller and a CDMA modem which includes a processing means for acquiring the global pilot code and despreading the spread-spectrum processed signal to reconstruct the transmitted information signal.

[0017] The RCS and the SUs each contain CDMA modems for transmission and reception of telecommunication signals including information signals and connection control signals. The CDMA modem comprises a modem transmitter having: a code generator for providing an associated pilot code signal and for generating a plurality of message code signals; a spreading means for combining each of the information signals, with a respective one of the message code signals to generate spread-spectrum processed message signals; and a global pilot code generator which provides a global pilot code signal to which the message code signals are synchronized.

[0018] The CDMA modem also comprises a modem receiver having associated pilot code acquisition and tracking logic. The associated pilot code acquisition logic includes an associated pilot code generator; a group of associated pilot code correlators for correlating code-phase delayed versions of the associated pilot signal with a receive CDM signal for producing a despread associated pilot signal. The code phase of the associated pilot signal is changed responsive to an acquisition signal value until a detector indicates the presence of the despread associated pilot code signal by changing the acquisition signal value. The associated pilot code signal is synchronized to the global pilot signal. The associated pilot code tracking logic adjusts the associated pilot code signal in phase responsive to the acquisition signal so that the signal power level of the despread associated pilot code signal is maximized. Finally, the CDMA modem receiver includes a group of message signal acquisition circuits. Each message signal acquisition circuit includes a plurality of receive message signal correlators for correlating one of the local receive message code signals with the CDM signal to produce a respective despread receive message signal.

[0019] To generate large families of nearly mutually orthogonal codes used by the CDMA modems, the present invention includes a code sequence generator. The code sequences are assigned to a respective logical channel of the spread-spectrum communication system, which includes In-phase (I) and quadrature (Q) transmission over RF communication channels. One set of sequences is used as pilot sequences which are code sequences transmitted without modulation by a data signal. The code sequence generator circuit includes a long code sequence generator including a linear feedback shift register, a memory which provides a short, even code sequence, and a plurality of cyclic shift, feedforward sections which provide other members of the code family which exhibit minimal correlation with the code sequence applied to the feedforward circuit. The code sequence generator further includes a group of code sequence combiners for combining each phase shifted version of the long code sequence with the short, even code sequence to produce a group, or family, of nearly mutually orthogonal codes.

[0020] Further, the present invention includes several methods for efficient utilization of the spread-spectrum channels. First, the system includes a bearer channel modification system which comprises a group of message channels between a first transceiver and second transceiver. Each of the group of message channels supports a different information signal transmission rate. The first transceiver monitors a received information signal to determine the type of information signal that is received, and produces a coding signal relating to the coding signal. If a certain type of information signal is present, the first transceiver switches transmission from a first message channel to a second message channel to support the different transmission rate. The coding signal is transmitted by the first transceiver to the second transceiver, and the second transceiver switches to the second message channel to receive the information signal at a different transmission rate.

[0021] Another method to increase efficient utilization of the bearer message channels is the method of idle-code suppression used by the present invention. The spread-spectrum transceiver receives a digital data information signal including a predetermined flag pattern corresponding to an idle period. The method includes the steps of: 1) delaying and monitoring the digital data signal; 2) detecting the predetermined flag pattern; 3) suspending transmission of the digital data signal when the flag pattern is detected; and 4) transmitting the data signal as a spread-spectrum signal when the flag pattern is not detected.

[0022] The present invention includes a system and method for closed loop automatic power control (APC) for the RCS and SUs of the spread-spectrum communication system. The SUs transmit spread-spectrum signals, the RCS acquires the spread-spectrum signals, and the RCS detects the received power level of the spread-spectrum signals plus any interfering signal including noise. The APC system includes the RCS and a plurality of SUs, wherein the RCS transmits a plurality of forward channel information signals to the SUs as a plurality of forward channel spread-spectrum signals having a respective forward transmit power level, and each SU transmits to the base station at least one reverse spread-spectrum signal having a respective reverse transmit power level and at least one reverse channel spread-spectrum signal which includes a reverse channel information signal.

[0023] The APC includes an automatic forward power control (AFPC) system, and an automatic reverse power control (ARPC) system. The AFPC system operates by measuring, at the SU, a forward signal-to-noise ratio of the respective forward channel information signal, generating a respective forward channel error signal corresponding to a forward error between the respective forward signal-to-noise ratio and a pre-determined signal-to-noise value, and transmitting the respective forward channel error signal as part of a respective reverse channel information signal from the SU to the RCS. The RCS includes a plural number of AFPC receivers for receiving the reverse channel information signals and extracting the forward channel error signals from the respective reverse channel information signals. The RCU also adjusts the respective forward transmit power level of each one of the respective forward spread-spectrum signals responsive to the respective forward error signal.

[0024] The ARPC system operates by measuring, in the RCS, a reverse signal-to-noise ratio of each of the respective reverse channel information signals, generating a respective reverse channel error signal representing an error between the respective reverse channel signal-to-noise ratio and a respective predetermined signal-to-noise value, and transmitting the respective reverse channel error signal as a part of a respective forward channel information signal to the SU. Each SU includes an ARPC receiver for receiving the forward channel information signal and extracting the respective reverse error signal from the forward channel information signal. The SU adjusts the reverse transmit power level of the respective reverse spread-spectrum signal responsive to the respective reverse error signal.

[0117] The system of the present invention provides local-loop telephone service using radio links between one or more base stations and multiple remote subscriber units. In the exemplary embodiment, a radio link is described for a base station communicating with a fixed subscriber unit (FSU), but the system is equally applicable to systems including multiple base stations with radio links to both FSUs and mobile subscriber units (MSUs). Consequently, the remote subscriber units are referred to herein as subscriber units (SUs).

[0118] Referring to FIG. 1, base station (BS) 101 provides call connection to a local exchange (LE) 103 or any other telephone network switching interface, such as a private branch exchange (PBX) and includes a radio carrier station (RCS) 104. One or more RCSs 104, 105, 110 connect to a radio distribution unit (RDU) 102 through links 131, 132, 137, 138, 139, and RDU 102 interfaces with LE 103 by transmitting and receiving call set-up, control, and information signals through telco links 141, 142, 150. SUs 116, 119 communicate with the RCS 104 through radio links 161, 162, 163, 164, 165. Alternatively, another embodiment of the invention includes several SUs and a “master” SU with functionality similar to the RCS 104. Such an embodiment may or may not have connection to a local telephone network.

[0119] The radio links 161 to 165 operate within the frequency bands of the DCS1800 standard (1.71-1.785 Ghz and 1.805-1.880 GHz); the US-PCS standard (1.85-1.99 Ghz); and the CEPT standard (2.0-2.7 GHz). Although these bands are used in described embodiment, the invention is equally applicable to the entire UHF to SHF bands, including bands from 2.7 GHz to 5 GHz. The transmit and receive bandwidths are multiples of 3.5 MHz starting at 7 MHz, and multiples of 5 MHz starting at 10 MHz, respectively. The described system includes bandwidths of 7, 10, 10.5, 14 and 15 MHz. In the exemplary embodiment of the invention, the minimum guard band between the uplink and downlink is 20 MHz, and is desirably at least three times the signal bandwidth. The duplex separation is between 50 to 175 MHz, with the described invention using 50, 75, 80, 95, and 175 MHz. Other frequencies may also be used.

[0120] Although the described embodiment uses different spread-spectrum bandwidths centered around a carrier for the transmit and receive spread-spectrum channels, the present method is readily extended to systems using multiple spread-spectrum bandwidths for the transmit channels and multiple spread-spectrum bandwidths for the receive channels. Alternatively, because spread-spectrum communication systems have the inherent feature that one user's transmission appears as noise to another user's despreading receiver, an embodiment may employ the same spread-spectrum channel for both the transmit and receive path channels. In other words, uplink and downlink transmissions can occupy the same frequency band. Furthermore, the present method may be readily extended to multiple CDMA frequency bands, each conveying a respectively different set of messages, uplink, downlink or uplink and downlink.

[0121] The spread binary symbol information is transmitted over the radio links 161 to 165 using quadrature phase shift keying (QPSK) modulation with Nyquist Pulse Shaping in the present embodiment, although other modulation techniques may be used, including, but not limited to, offset QPSK (OQPSK), minimum shift keying (MSK). Gaussian phase shift keying (GPSK) and M-ary phase shift keying (MPSK)

[0122] The radio links 161 to 165 incorporate Broadband Code Division Multiple Access (B-CDMA™) as the mode of transmission in both the uplink and downlink directions. CDMA (also known as spread spectrum) communication techniques used in multiple access systems are well-known, and are described in U.S. Pat. No. 5,228,056 entitled SYNCHRONOUS SPREAD-SPECTRUM COMMUNICATION SYSTEM AND METHOD by Donald T Schilling. The system described utilizes the direct sequence (DS) spreading technique. The CDMA modulator performs the spread-spectrum spreading code sequence generation, which can be a pseudonoise (PN) sequence; and complex DS modulation of the QPSK signals with spreading code sequences for the in-phase (I) and quadrature (Q) channels. Pilot signals are generated and transmitted with the modulated signals, and pilot signals of the present embodiment are spreading codes not modulated by data. The pilot signals are used for synchronization, carrier phase recovery and for estimating the impulse response of the radio channel. Each SU includes a single pilot generator and at least one CDMA modulator and demodulator, together known as a CDMA modem. Each RCS 104, 105, 110 has a single pilot generator plus sufficient CDMA modulators and demodulators for all of the logical channels in use by all SUs.

[0123] The CDMA demodulator despreads the signal with appropriate processing to combat or exploit multipath propagation effects. Parameters concerning the received power level are used to generate the automatic power control (APC) information which, in turn, is transmitted to the other end of the communication link. The APC information is used to control transmit power of the automatic forward power control (AFPC) and automatic reverse power control (ARPC) links. In addition, each RCS 104, 105 and 110 can perform maintenance power control (MPC), in a manner similar to APC, to adjust the initial transmit power of each SU 111, 112, 115, 117 and 118. Demodulation is coherent where the pilot signal provides the phase reference.

[0124] The described radio links support multiple traffic channels with data rates of 8, 16, 32, 64, 128, and 144 kbs. The physical channel to which a traffic channel is connected operates with a 64k symbol/sec rate. Other data rates may be supported, and forward error correction (FEC) coding can be employed. For the described embodiment, FEC with coding rate of ½ and constraint length 7 is used. Other rates and constraint lengths can be used consistent with the code generation techniques employed.

[0125] Diversity combining at the radio antennas of RCS 104, 105 and 110 is not necessary because CDMA has inherent frequency diversity due to the spread bandwidth. Receivers include adaptive matched filters (AMFs) (not shown in FIG. 1) which combine the multipath signals. In the present embodiment, the exemplary AMFs perform maximal ratio combining.

[0126] Referring to FIG. 1, RCS 104 interfaces to RDU 102 through links 131, 132, 137, 139 with, for example, 1.544 Mb/s DS1, 2.048 Mb/s E1; or HDSL formats to receive and send digital data signals. While these are typical telephone company standardized interfaces, the present invention is not limited to these digital data formats only. The exemplary RCS line interface (not shown in FIG. 1) translates the line coding (such as HDB3, B8ZS, AMI) and extracts or produces framing information, performs alarms and facility signaling functions, as well as channel specific loop-back and parity check functions. The interfaces for this description provide 64 kbs PCM encoded or 32 kbs ADPCM encoded telephone traffic channels or ISDN channels to the RCS for processing. Other ADPCM encoding techniques can be used consistent with the sequence generation techniques.

[0127] The system of the present invention also supports bearer rate modification between the RCS 104 and each SU 111, 112, 115, 117 and 118 communicating with the RCS 104 in which a CDMA message channel supporting 64 kbs may be assigned to voiceband data or FAX when rates above 4.8 kbs are present. Such 64 kbs bearer channel is considered an unencoded channel. For ISDN, bearer rate modification may be done dynamically, based upon the D channel messages.

[0128] In FIG. 1, each SU 111, 112, 115, 117 and 118 either includes or interfaces with a telephone unit 170, or interfaces with a local switch (PBX) 171. The input from the telephone unit may include voice, voiceband data and signaling. The SU translates the analog signals into digital sequences, and may also include a data terminal 172 or an ISDN interface 173. The SU can differentiate voice input, voiceband data or FAX and digital data. The SU encodes voice data with techniques such as ADPCM at 32 kbs or lower rates, and detects voiceband data or FAX with rates above 4.8 kbs to modify the traffic channel (bearer rate modification) for unencoded transmission. Also, A-law, u-law or no compounding of the signal may be performed before transmission. For digital data, data compression techniques, such as idle flag removal, may also be used to conserve capacity and minimize interference

[0129] The transmit power levels of the radio interface between RCS 104 and SUs 111, 112, 115, 117 and 118 are controlled using two different closed loop power control methods. The automatic forward power control (AFPC) method determines the downlink transmit power level, and the automatic reverse power control (ARPC) method determines the Uplink transmit power level. The logical control channel by which SU 111 and RCS 104, for example, transfer power control information operates at least a 16 kHz update rate. Other embodiments may use a faster or slower update rate, for example 64 kHz. These algorithms ensure that the transmit power of a user maintains an acceptable bit-error rate (BER), maintains the system power at a minimum to conserve power and maintains the power level of all SUs 111, 112, 115, 117 and 118 received by RCS 104 at a nearly equal level.

[0130] In addition, the system uses an optional maintenance power control method during the inactive mode of a SU. When SU 111 is inactive or powered-down to conserve power, the unit occasionally activates to adjust its initial transmit power level setting in response to a maintenance power control signal from RCS 104. The maintenance power signal is determined by the RCS 104 by measuring the received power level of SU 111 and present system power level and, from this, calculates the necessary initial transmit power. The method shortens the channel acquisition time of SU 111 to begin a communication. The method also prevents the transmit power level of SU 111 from becoming too high and interfering with other channels during the initial transmission before the closed loop power control reduces the transmit power.

[0131] RCS 104 obtains synchronization of its clock from an interface line such as, but not limited to, E1, T1, or HDSL interfaces. RCS 104 can also generate its own internal clock signal from an oscillator which may be regulated by a global positioning system (GPS) receiver. RCS 104 generates a global pilot code, a channel with a spreading code but no data modulation, which can be acquired by remote SUs 111 through 118. All transmission channels of the RCS are synchronized to the pilot channel, and spreading code phases of code generators (not shown) used for logical communication channels within RCS 104 are also synchronized to the pilot channel's spreading code phase. Similarly, SUs 111 through 118 which receive the global pilot code of RCS 104 synchronize the spreading and despreading code phases of the code generators (not shown) of the SUs to the global pilot code.

[0132] RCS 104, SU 111 and RDU 102 may incorporate system redundancy of system elements and automatic switching between internal functional system elements upon a failure event to prevent loss or drop-out of a radio link, power supply, traffic channel or group of traffic channels.

[0133] A ‘channel’ of the prior art is usually regarded as a communications path which is part of an interface and which can be distinguished from other paths of that interface without regard to its content. However, in the case of CDMA, separate communications paths are distinguished only by their content. The term ‘logical channel’ is used to distinguish the separate data streams, which are logically equivalent to channels in the conventional sense. All logical channels and sub-channels of the present invention are mapped to a common 64 kilo-symbols per second (ksym/s) QPSK stream. Some channels are synchronized to associated pilot codes which are generated from, and perform a similar function to the system global pilot code (GPC). The system pilot signals are not, however, considered logical channels.

[0134] Several logical communication channels are used over the RF communication link between the RCS and SU. Each logical communication channel either has a fixed, pre-determined spreading code or a dynamically assigned spreading code. For both pre-determined and assigned codes, the code phase is synchronized with the pilot code. Logical communication channels are divided into two groups: the global channel (GC) group includes channels which are either transmitted from the base station RCS to all remote SUs or from any SU to the RCS of the base station regardless of the SU's identity. The channels in the GC group may contain information of a given type for all users including those channels used by SUs to gain system access. Channels in the assigned channels (AC) group are those channels dedicated to communication between the RCS and a particular SU.

[0135] The global channels (GC) group provides for 1) broadcast control logical channels, which provide point-to-multipoint services for broadcasting messages to all SUs and paging messages to SUs; and 2) access control logical channels which provide point-to-point services on global channels for SUs to access the system and obtain assigned channels. The RCS of the present invention has multiple access control logical channels, and one broadcast control group. An SU of the present invention has at least one access control channel and at least one broadcast control logical channel.

[0136] The global logical channels controlled by the RCS are the fast broadcast channel (FBCH) which broadcasts fast changing information concerning which services and which access channels are currently available, and the slow broadcast channel (SBCH) which broadcasts slow changing system information and paging messages. The access channel (AXCH) is used by the SUs to access an RCS and gain access to assigned channels. Each AXCH is paired with a control channel (CTCH). The CTCH is used by the RCS to acknowledge and reply to access attempts by SUs. The long access pilot (LAXPT) is transmitted synchronously with AXCH to provide the RCS with a time and phase reference. An assigned channel (AC) group contains the logical channels that control a single telecommunication connection between the RCS and a SU. The functions developed when an AC group is formed include a pair of power control logical message channels for each of the uplink and downlink connections, and depending on the type of connection, one or more pairs of traffic channels. The bearer control function performs the required forward error control, bearer rate modification, and encryption functions.

[0137] Each SU 111, 112, 115, 117 and 118 has at least one AC group formed when a telecommunication connection exists, and each RCS 104, 105 and 110 has multiple AC groups formed, one for each connection in progress. An AC group of logical channels is created for a connection upon successful establishment of the connection. The AC group includes encryption, FEC coding and multiplexing on transmission, and FEC decoding, decryption and demultiplexing on reception.

[0138] Each AC group provides a set of connection oriented point-to-point services and operates in both directions between a specific RCS, for example, RCS 104 and a specific SU, for example, SU 111. An AC group formed for a connection can control more than one bearer over the RF communication channel associated with a single connection. Multiple bearers are used to carry distributed data such as, but not limited to, ISDN. An AC group can provide for the duplication of traffic channels to facilitate switch over to 64 kbs PCM for high speed facsimile and modem services for the bearer rate modification function.

[0139] The assigned logical channels formed upon a successful call connection and included in the AC group are a dedicated signaling channel [order wire (OW)], an APC channel, and one or more traffic channels (TRCH) which are bearers of 8, 16, 32, or 64 kbs depending on the service supported. For voice traffic, moderate rate coded speech, ADPCM or PCM can be supported on the traffic channels. For ISDN service types, two 64 kbs TRCHs form the B channels and a 16 kbs TRCH forms the D channel. Alternatively, the APC subchannel may either be separately modulated on its own CDMA channel, or may be time division multiplexed with a traffic channel or OW channel.

[0140] Each SU 111, 112, 115, 117 and 118 of the present invention supports up to three simultaneous traffic channels. The mapping of the three logical channels for TRCHs to the user data is shown below in Table 1:

[0141]

TABLE 1
Mapping of service types to the three available TRCH channels
Service	TRCH(0)	TRCH(1)	TRCH(2)
16 kbs POTS	TRCH/16	not used	not used
32 + 64 kbs POTS (during	TRCH/32	TRCH/64	not used
BCM)
32 kbs POTS	TRCH/32	not used	not used
64 kbs POTS	not used	TRCH/64	not used
ISDN D	not used	not used	TRCH/16
ISDN B + D	TRCH/64	not used	TRCH/16
ISDN 2B + D	TRCH/64	TRCH /64	TRCH/16
Digital LL @ 64 kbs	TRCH/64	not used	not used
Digital LL @ 2 × 64 kbs	TRCH/64	TRCH/64	not used
Analog LL @ 64 kbs	TRCH/64	not used	not used

[0142] The APC data rate is sent at 64 kbs. The APC logical channel is not FEC coded to avoid delay and is transmitted at a relatively low power level to minimize capacity used for APC. Alternatively, the APC and OW may be separately modulated using complex spreading code sequences or they may be time division multilplexed.

[0143] The OW logical channel is FEC coded with a rate ½ convolutional code. This logical channel is transmitted in bursts when signaling data is present to reduce interference. After an idle period, the OW signal begins with at least 35 symbols prior to the start of the data frame. For silent maintenance call data, the OW is transmitted continuously between frames of data. Table 2 summarizes the logical channels used in the exemplary embodiment:

[0144]

TABLE 2
Logical Channels and sub-channels of the B-CDMA Air Interface
			Direction
			(forward
Channel		Brief	or	Bit	Max
name	Abbr.	Description	reverse)	rate	BER	Power level	Pilot
Global Channels
Fast	FBCH	Broadcasts	F	16	1e-4	Fixed	GLPT
Broadcast		fast-changing		kbs
Channel		system
		information
Slow	SBCH	Broadcasts	F	16	1e-7	Fixed	GLPT
Broadcast		paging		kbs
Channel		messages to
		FSUs and
		slow-changing
		system
		information
Access	AXCH(i)	For initial	R	32	1e-7	Controlled	LAXPT(i)
Channels		access		kbs		by APC
		attempts by
		FSUs
Control	CTCH(i)	For granting	F	32	1e-7	Fixed	GLPT
Channels		access		kbs
Assigned Channels
16 kbs	TRCH/16	General POTS	F/R	16	1e-4	Controlled	F-GLPT
POTS		use		kbs		by APC	R-ASPT
32 kbs	TRCH/32	General POTS	F/R	32	1e-4	Controlled	F-GLPT
POTS		use		kbs		by APC	R-ASPT
64 kbs	TRCH/64	POTS use for	F/R	64	1e-4	Controlled	F-GLPT
POTS		in-band		kbs		by APC	R-ASPT
		modems/fax
D channel	TRCH/16	ISDN D	F/R	16	1e-7	Controlled	F-GLPT
		channel		kbs		by APC	R-ASPT
Order	OW	assigned	F/R	32	1e-7	Controlled	F-GLPT
wire		signaling		kbs		by APC	R-ASPT
channel		channel
APC	APC	carries APC	F/R	64	2e-1	Controlled	F-GLPT
channel		commands		kbs		by APC	R-ASPT

[0145] The CDMA code generators used to encode the logical channels of the present invention employ linear shift registers (LSRs) with feedback logic which is a method well known in the art. The code generators of the present embodiment of the invention generate 64 synchronous unique sequences. Each RF communication channel uses a pair of these sequences for complex spreading (in-phase and quadrature) of the logical channels, so the generator gives 32 complex spreading sequences. The sequences are generated by a single seed which is initially loaded into a shift register circuit.

[0146] The spreading code period of the present invention is defined as an integer multiple of the symbol duration, and the beginning of the code period is also the beginning of the symbol. The relation between bandwidths and the symbol lengths chosen for the exemplary embodiment of the present invention is:

[0147]

	BW (MHZ)	L (chips/symbol)
	7	91
	10	130
	10.5	133
	14	182
	15	195

[0148] The spreading code length is also a multiple of 64 and of 96 for ISDN frame support. The spreading code is a sequence of symbols, called chips or chip values. The general methods of generating pseudorandom sequences using Galois Field mathematics is known to those skilled in the art; however, a unique set or family of code sequences has been derived for the present invention. First, the length of the LFSR to generate a code sequence is chosen, and the initial value of the register is called a “seed”. Second, the constraint is imposed that no code sequence generated by a code seed may be a cyclic shift of another code sequence generated by the same code seed. Finally, no code sequence generated from one seed may be a cyclic shift of a code sequence generated by another seed. It has been determined that the spreading code length of chip values of the present invention is:
128×233,415=29,877,120  Equation (1)
The spreading codes are generated by combining a linear sequence of period 233415 and a nonlinear sequence of period 128.

[0149] The FBCH channel of the exemplary embodiment is an exception because it is not coded with the 128 length sequence, so the FBCH channel spreading code has period 233415.

[0150] The nonlinear sequence of length 128 is implemented as a fixed sequence loaded into a shift register with a feed-back connection. The fixed sequence can be generated by an m-sequence of length 127 padded with an extra logic 0, 1, or random value as is well known in the art.

[0151] The linear sequence of length L=233415 is generated using an LFSR circuit with 36 stages. The feedback connections correspond to a irreducible polynomial h(n) of degree 36. The polynomial h(x) chosen for the exemplary embodiment of the present invention is
h(x)=x³⁶+x³⁵+x³⁰+x²⁸+x²⁶+x²⁵+x²²+x²⁰+x¹⁹+x¹⁷+x¹⁶+x¹⁵+x¹⁴+x¹²+x¹¹+x⁹x⁸+x⁴+x³+x²+1
or, in binary notation
h(x)=(1100001010110010110111101101100011101)  Equation (2)

[0152] A group of “seed” values for a LFSR representing the polynomial h(x) of Equation (2) which generates code sequences that are nearly orthogonal with each other is determined. The first requirement of the seed values is that the seed values do not generate two code sequences which are simply cyclic shifts of each other.

[0153] The seeds are represented as elements of GF(2³⁶) which is the field of residue classes modulo h(x). This field has a primitive element δ=x²+x+1. The binary representation of δ is:
δ=000000000000000000000000000000000111  Equation (3)

[0154] Every element of GF(2³⁶) can also be written as a power of δ reduced modulo h(x). Consequently, the seeds are represented as powers of δ, the primitive element.

[0155] The solution for the order of an element does not require a search of all values; the order of an element divides the order of the field (GF(2³⁶)). When δ is any element of GF(2³⁶) with
x^e≡1  Equation (4)
for some e, then e|2³⁶−1. Therefore, the order of any element in GF(2³⁶) divides 2³⁶−1. Using these constraints, it has been determined that a numerical search generates a group of seed values, n, which are powers of δ, the primitive element of h(x).

[0156] The present invention includes a method to increase the number of available seeds for use in a CDMA communication system by recognizing that certain cyclic shifts of the previously determined code sequences may be used simultaneously. The round trip delay for the cell sizes and bandwidths of the present invention are less than 3000 chips. In one embodiment of the present invention, sufficiently separated cyclic shifts of a sequence can be used within the same cell without causing ambiguity for a receiver attempting to determine the code sequence. This method enlarges the set of sequences available for use. By implementing the tests previously described, a total of 3879 primary seeds were determined through numerical computation. These seeds are given mathematically as:
δⁿ modulo h(x)  Equation (5)
where 3879 values of n, with δ=(00, . . . 00111) as in (3), is a series incrementing by 1, starting at 1 and continuing to 1101, resuming at 2204 and continuing to 3305, resuming at 4408 and continuing to 5509, and resuming at 6612 and ending at 7184.

[0157] When all primary seeds are known, all secondary seeds of the present invention are derived from the primary seeds by shifting them multiples of 4095 chips modulo h(x). Once a family of seed values is determined, these values are stored in memory and assigned to logical channels as necessary. Once assigned, the initial seed value is simply loaded into LFSR to produce the required spreading code associated with the seed value.

[0158] Rapid acquisition of the correct code phase by a spread-spectrum receiver is improved by designing spreading codes which are faster to detect. It should be noted that spreading code, code sequence, spreading code sequence, chip code, chip sequence or chip code sequence may be used interchangeably to refer to a moduling signal used to modulate an information signal whereby the period of the modulation signal is substantially less than the period of the information signal. For simplicity, the term spreading code will be used. The present embodiment of the invention includes a new method of generating spreading codes that have rapid acquisition properties by using one or more of the following methods. First, a long code may be constructed from two or more short codes. The new implementation uses many spreading codes, one or more of which are rapid acquisition sequences of length L that have average acquisition phase searches r=log 2L. Sequences with such properties are well known to those practiced in the art. The average number of acquisition test phases of the resulting long sequence is a multiple of r=log 2L rather than half of the number of phases of the long sequence.

[0159] Second, a method of transmitting complex valued spreading codes (in-phase (I) and quadrature (Q) sequences) in a pilot spreading code signal may be used rather than transmitting real valued sequences. Two or more separate spreading codes may be transmitted over the complex channels. If the codes have different phases, an acquisition may be done by acquisition circuits in parallel over the different spreading codes when the relative phase shift between the two or more code channels is known. For example, for two spreading codes, one can be sent on an in phase (I) channel and one on the quadrature (Q) channel. To search the spreading codes, the acquisition detection means searches the two channels, but begins the Q channel with an offset equal to one-half of the spreading code length. With code length of N, the acquisition means starts the search at N/2 on the Q channel. The average number of tests to find acquisition is N/2 for a single code search, but searching the I and phase delayed Q channel in parallel reduces the average number of tests to N/4. The codes sent on each channel could be the same code, the same code with one channel's code phase delayed or different spreading codes.

[0160] The long complex spreading codes used for the exemplary system of the present invention have a number of chips after which the code repeats. The repetition period of the spreading code is called an epoch. To map the logical channels to CDMA spreading codes, the present invention uses an epoch and sub-epoch structure. The code period for the CDMA spreading code to modulate logical channels is 29877120 chips/code period, which is the same number of chips for all bandwidths. The code period is the epoch of the present invention, and Table 3 below defines the epoch duration for the supported chip rates. In addition, two sub-epochs are defined over the spreading code epoch and are 233415 chips and 128 chips long.

[0161] The 233415 chip sub-epoch is referred to as a long sub-epoch, and is used for synchronizing events on the RF communication interface such as encryption key switching and changing from global to assigned codes. The 128 chip short epoch is defined for use as an additional timing reference. The highest symbol rate used with a single CDMA code is 64 ksym/s. There is always an integer number of chips in a symbol duration for the supported symbol rates 64, 32, 16, and 8 ksym/s.

[0162]

TABLE 3
Bandwidths, Chip Rates, and Epochs
		number of	128 chip	233415 chip
	Chip Rate,	chips in a	sub-epoch	sub-epoch	Epoch
Bandwidth	Complex	64 kbit/sec	duration*	duration*	duration
(MHz)	(Mchip/sec)	symbol	(ms)	(ms)	(sec)
7	5.824	91	21.978	40.078	5.130
10	8.320	130	15.385	28.055	3.591
10.5	8.512	133	15.038	27.422	3.510
14	11.648	182	10.989	20.039	2.565
15	12.480	195	10.256	18.703	2.394
*numbers in these columns are rounded to 5 digits.

[0163] The complex spreading codes are designed such that the beginning of the code epoch coincides with the beginning of a symbol for all of the bandwidths supported. The present invention supports bandwidths of 7, 10, 10.5, 14, and 15 MHz. Assuming nominal 20% roll-off, these bandwidths correspond to the following chip rates in Table 4.

[0164]

TABLE 4
Supported Bandwidths and Chip Rates for CDMA.
	Rc (Complex	Excess BW,		Factorization
BW (MHz)	Mchips/sec)	%	L:(Rc/L) = 64k	of L
7	5.824	20.19	91	7X13
10	8.320	20.19	130	2X5X13
10.5	8.512	23.36	133	7X19
14	11.648	20.19	182	2X7X13
15	12.480	20.19	195	3X5X13

The number of chips in an epoch is:
 N=29877120=2⁷×3³×5×7×13×19  Equation (6)

[0165] If interleaving is used, the beginning of an interleaver period coincides with the beginning of the sequence epoch. The spreading sequences generated using the method of the present invention can support interleaver periods that are multiples of 1.5 ms for various bandwidths.

[0166] Cyclic sequences of the prior art are generated using LFSR circuits. However, this method does not generate sequences of even length. One embodiment of the spreading code generator using the code seeds generated previously is shown in FIG. 2a, FIG. 2b, and FIG. 2c. The present invention uses a 36 stage LFSR 201 to generate a sequence of period N′=233415=3³×5×7×13×19, which is C_o in FIG. 2a. In FIGS. 2a, 2b, and 2csymbol ⊕ represents a binary addition (EXCLUSIVE-OR). A spreading code generator designed as above generates the in-phase and quadrature parts of a set of complex sequences. The tap connections and initial state of the 36 stage LFSR determine the sequence generated by this circuit. The tap coefficients of the 36 stage LFSR are determined such that the resulting sequences have the period 233415. Note that the tap connections shown in FIG. 2a correspond to the polynomial given in Equation (2). Each resulting sequence is then overlaid by binary addition with the 128 length sequence C* to obtain the epoch period 29877120.

[0167] FIG. 2b shows a feed forward (FF) circuit 202 which is used in the code generator. The signal X[n−1] is output of the chip delay 211, and the input of the chip delay 211 is X[n]. The code chip C[n] is formed by the logical adder 212 from the input X[n] and X[n−1]. FIG. 2c shows the complete spreading code generator. From the LFSR 201, output signals go through a chain of up to 63 single stage FFs 203 cascaded as shown. The output of each FF is overlaid with the short, even code sequence C* period 128=2⁷ which is stored in code memory 222 and which exhibits spectral characteristics of a pseudorandom sequence to obtain the epoch N=29877120. This sequence of 128 is determined by using an m-sequence (PN sequence) of length 127=2⁷−1 and adding a bit-value, such as logic 0, to the sequence to increase the length to 128 chips. The even code sequence C* is input to the even code shift register 221, which is a cyclic register, that continually outputs the sequence. The short sequence is then combined with the long sequence using an EXCLUSIVE-OR operation 213, 214, 220.

[0168] As shown in FIG. 2c, up to 63 spreading codes C_o through C₆₃ are generated by tapping the output signals of FFs 203 and logically adding the short sequence C* in binary adders 213, 214, and 220, for example. One skilled in the art would realize that the implementation of FF 203 will create a cumulative delay effect for the spreading codes produced at each FF stage in the chain. This delay is due to the nonzero electrical delay in the electronic components of the implementation. The timing problems associated with the delay can be mitigated by inserting additional delay elements into the FF chain in one version of the embodiment of the invention. The FF chain of FIG. 2c with additional delay elements is shown in FIG. 2d.

[0169] The code-generators in the exemplary embodiment of the present invention are configured to generate either global codes or assigned codes. Global codes are CDMA codes that can be received or transmitted by all users of the system. Assigned codes are CDMA codes that are allocated for a particular connection. When a set of spreading codes are generated from the same generator as described, only the seed of the 36 stage LFSR is specified to generate a family of spreading codes. Spreading codes for all of the global codes are generated using the same LFSR circuit. Therefore, once an SU has synchronized to the global pilot signal from an RCS and knows the seed for the LFSR circuit for the global channel codes, it can generate not only the pilot spreading code but also all other global codes used by the RCS.

[0170] The signal that is up converted to RF is generated as follows. The output signals of the above shift register circuits are converted to an antipodal sequence (0 maps into +1, 1 maps into −1). The logical channels are initially converted to QPSK signals, which are mapped as constellation points as is well known in the art. The in-phase and quadrature channels of each QPSK signal form the real and imaginary parts of the complex data value. Similarly, two spreading codes are used to form complex spreading chip values. The complex data are spread by being multiplied by the complex spreading code. Similarly, the received complex data is correlated with the conjugate of the complex spreading code to recover despread data.

[0171] Short codes are used for the initial ramp-up process when a SU accesses an RCS. The period of the short codes is equal to the symbol duration and the start of each period is aligned with a symbol boundary. Both SU and RCS derive the real and imaginary parts of the short codes from the last eight feed-forward sections of the code generator producing the global codes for that cell.

[0172] The short codes that are in use in the exemplary embodiment of the invention are updated every 3 ms. Other update times that are consistent with the symbol rate may be used. Therefore, a change-over occurs every 3 ms starting from the epoch boundary. At a change-over, the next symbol length portion of the corresponding feed-forward output becomes the short code. When the SU needs to use a particular short code, it waits until the first 3 ms boundary of the next epoch and stores the next symbol length portion output from the corresponding FF section. This shall be used as the short code until the next change-over, which occurs 3 ms later.

[0173] The signals represented by these short codes are known as short access channel pilots (SAXPTs).

[0174] The exact relationship between the spreading codes and the CDMA logical channels and pilot signals is documented in Table 5a and Table 5b. Those signal names ending in ‘-CH’ correspond to logical channels. Those signal names ending in ‘-PT’ correspond to pilot signals, which are described in detail below.

[0175]

TABLE 5a
Spreading code sequences and global CDMA codes
			Logical Channel
	Sequence	Quadrature	or Pilot Signal	Direction
	C0	I	FBCH	Forward (F)
	C1	Q	FBCH	F
	C2⊕C*	I	GLPT	F
	C3⊕C*	Q	GLPT	F
	C4⊕C*	I	SBCH	F
	C5⊕C*	Q	SBCH	F
	C6⊕C*	I	CICH (0)	F
	C7⊕C*	Q	CTCH (0)	F
	C8⊕C*	I	APCH (1)	F
	C9⊕C*	Q	APCH (1)	F
	C10⊕C*	I	CTCH (1)	F
	C11⊕C*	Q	CTCH (1)	F
	C12⊕C*	I	APCH (1)	F
	C13⊕C*	Q	APCH (1)	F
	C14⊕C*	I	CTCH (2)	F
	C15⊕C*	Q	CTCH (2)	F
	C16⊕C*	I	APCH (2)	F
	C17⊕C*	Q	APCH (2)	F
	C18⊕C*	I	CTCH (3)	F
	C19⊕C*	Q	CTCH (3)	F
	C20⊕C*	I	APCH (3)	F
	C21⊕C*	Q	APCH (3)	F
	C22⊕C*	I	reserved	—
	C23⊕C*	Q	reserved	—
	. . .	. . .	. . .	. . .
	. . .	. . .	. . .	. . .
	. . .	. . .	. . .	. . .
	C40⊕C*	I	reserved	—
	C41⊕C*	Q	reserved	—
	C42⊕C*	I	AXCH(3)	Reverse (R)
	C43⊕C*	Q	AXCH(3)	R
	C44⊕C*	I	LAXPT(3)	R
			SAXPT(3) seed
	C45⊕C*	Q	LAXPT(3)	R
			SAXPT(3) seed
	C46⊕C*	I	AXCH(2)	R
	C47⊕C*	Q	AXCH(2)	R
	C48⊕C*	I	LAXPT(2)	R
			SAXPT(2) seed
	C49⊕C*	Q	LAXPT(2)	R
			SAXPT(2) seed
	C50⊕C*	I	AXCH(1)	R
	C51⊕C*	Q	AXCH(l)	R
	C52⊕C*	I	LAXPT(1)	R
			SAXPT(1) seed
	C53⊕C*	Q	LAXPT(1)	R
			SAXPT(1) seed
	C54⊕C*	I	AXCH(0)	R
	C55⊕C*	Q	AXCH(0)	R
	C56⊕C*	I	LAXPT(0)	R
			SAXPT(0) seed
	C57⊕C*	Q	LAXPT(0)	R
			SAXPT(0) seed
	C58⊕C*	I	IDLE
	C59⊕C*	Q	IDLE
	C60⊕C*	I	AUX	R
	C61⊕C*	Q	AUX	R
	C62⊕C*	I	reserved
	C63⊕C*	Q	reserved

[0176]

TABLE 5b
Spreading code sequences and assigned CDMA codes.
			Logical Channel
	Sequence	Quadrature	or Pilot Signal	Direction
	C0⊕C*	I	ASPT	Reverse (R)
	C1⊕C*	Q	ASPT	R
	C2⊕C*	I	APCH	R
	C3⊕C*	Q	APCH	R
	C4⊕C*	I	OWCH	R
	C5⊕C*	Q	OWCH	R
	C6⊕C*	I	TRCH(0)	R
	C7⊕C*	Q	TRCH(0)	R
	C8⊕C*	I	TRCH(1)	R
	C9⊕C*	Q	TRCH(1)	R
	C10⊕C*	I	TRCH(2)	R
	C11⊕C*	Q	TRCH(2)	R
	C12⊕C*	I	TRCH(3)	R
	C13⊕C*	Q	TRCH(3)	R
	C14⊕C*	I	reserved	—
	C15⊕C*	Q	reserved	—
	. . .	. . .	. . .	. . .
	. . .	. . .	. . .	. . .
	C44⊕C*	I	reserved	—
	C45⊕C*	Q	reserved	—
	C46⊕C*	I	TRCH(3)	Forward (F)
	C47⊕C*	Q	TRCH(3)	F
	C48⊕C*	I	TRCH(2)	F
	C49⊕C*	Q	TRCH(2)	F
	C50⊕C*	I	TRCH(1)	F
	C51⊕C*	Q	TRCH(1)	F
	C52⊕C*	I	TRCH(O)	F
	C53⊕C*	Q	TRCH(O)	F
	C54⊕C*	I	OWCH	F
	C55⊕C*	Q	OWCH	F
	C56⊕C*	I	APCH	F
	C57⊕C*	Q	APCH	F
	C58⊕C*	I	IDLE	—
	C59⊕C*	Q	IDLE	—
	C60⊕C*	I	reserved	—
	C61⊕C*	Q	reserved	—
	C62⊕C*	I	reserved	—
	C63⊕C*	Q	reserved	—

[0177] For global codes, the seed values for the 36 bit shift register are chosen to avoid using the same code, or any cyclic shift of the same code, within the same geographical area to prevent ambiguity or harmful interference. No assigned code is equal to, or a cyclic shift of, a global code.

[0178] The pilot signals are used for synchronization, carrier phase recovery and for estimating the impulse response of the radio channel. The RCS 104 transmits a forward link pilot carrier reference as a complex pilot code sequence to provide time and phase reference for all SUs 111, 112, 115, 117 and 118 in its service area. The power level of the global pilot (GLPT) signal is set to provide adequate coverage over the whole RCS service area, which area depends on the cell size. With only one pilot signal in the forward link, the reduction in system capacity due to the pilot energy is negligible.

[0179] The SUs 111, 112, 115, 117 and 118 each transmit a pilot carrier reference as a quadrature modulated (complex-valued) pilot spreading code sequence to provide a time and phase reference to the RCS for the reverse link. The pilot signal transmitted by the SU of one embodiment of the invention is 6 dB lower than the power of the 32 kbs POTS traffic channel. The reverse pilot channel is subject to APC. The reverse link pilot associated with a particular connection is called the assigned pilot (ASPT). In addition, there are pilot signals associated with access channels. These are called the long access channel pilots (LAXPTs). Short access channel pilots (SAXPTs) are also associated with the access channels and used for spreading code acquisition and initial power ramp-up. All pilot signals are formed from complex codes, as defined below: $\begin{array}{c}\mathrm{GLPT}\left(\mathrm{forward}\right)=\left\{C_2\oplus C_{*}\right)+j·\left(C_3\oplus C_{*}\right)\}·\left\{\left(1\right)+j·\left(0\right)\right\}\\ \mathrm{ }\left\{\mathrm{Complex}\mathrm{Code}\right\}·\left\{\mathrm{Carrier}\right\}\end{array}$

[0180] The complex pilot signals are de-spread by multiplication with conjugate spreading codes: {(C₂⊕C*)−j.(C₃⊕C*)}. By contrast, traffic channels are of the form: $\begin{array}{c}{\mathrm{TRCH}}_n(\mathrm{forward}/\mathrm{reverse}=\left\{\left(C_k\oplus C_{*}\right)+j·\left(C_1\oplus C_{*}\right)\right\}·\left\{\left(\pm 1\right)+j\left(\pm 1\right)\right\}\\ \mathrm{ }\left\{\mathrm{Complex}\mathrm{Codes}\right\}·\left\{\mathrm{Data}\mathrm{Symbol}\right\}\end{array}$
which thus form a constellation set at $\frac{\pi }{4}$
radians with respect to the pilot signal constellations. The GLPT constellation is shown in FIG. 3a, and the TRCH_n traffic channel constellation is shown in FIG. 3b.

[0181] The FBCH is a global forward link channel used to broadcast dynamic information about the availability of services and AXCHs. Messages are sent continuously over this channel, and each message lasts approximately 1 ms. The FBCH message is 16 bits long, repeated continuously, and is epoch aligned. The FBCH is formatted as defined in Table 6.

[0182]

TABLE 6
FBCH format
Bit	Definition
0	Traffic Light 0
1	Traffic Light 1
2	Traffic Light 2
3	Traffic Light 3
4-7	service indicator bits
8	Traffic Light 0
9	Traffic Light 1
10	Traffic Light 2
11	Traffic Light 3
12-15	service indicator bits

[0183] For the FBCH, bit 0 is transmitted first. As used in Table 6, a traffic light corresponds to an access channel (AXCH) and indicates whether the particular access channel is currently in use (a red) or not in use (a green). A logic ‘1’ indicates that the traffic light is green, and a logic ‘0’ indicates the traffic light is red. The values of the traffic light bits may change from octet to octet and each 16 bit message contains distinct service indicator bits which describe the types of services that are available for the AXCHs.

[0184] One embodiment of the present invention uses service indicator bits as follows to indicate the availability of services or AXCHs. The service indicator bits {4,5,6,7,12,13,14,15} taken together may be an unsigned binary number, with bit 4 as the MSB and bit 15 as the LSB. Each service type increment has an associated nominal measure of the capacity required, and the FBCH continuously broadcasts the available capacity. This is scaled to have a maximum value equivalent to the largest single service increment possible. When a SU requires a new service or an increase in the number of bearers it compares the capacity required to that indicated by the FBCH and then considers itself blocked if the capacity is not available. The FBCH and the traffic channels are aligned to the epoch.

[0185] Slow broadcast information frames contain system or other general information that is available to all SUs and paging information frames contain information about call requests for particular SUs. Slow broadcast information frames and paging information frames are multiplexed together on a single logical channel which forms the slow broadcast channel (SBCH). As previously defined, the code epoch is a sequence of 29,877,120 chips having an epoch duration which is a function of the chip rate defined in Table 7 below. In order to facilitate power saving, the channel is divided into N “Sleep” cycles, and each cycle is subdivided into M slots, which are 19 ms long, except for 10.5 Mhz bandwidth which has slots of 18 ms.

[0186]

TABLE 7
SBCH Channel Format Outline
	Spreading
	Code	Epoch	Cycles/	Cycle	Slots/	Slot
Bandwidth	Rate	Length	Epoch	Length	Cycle	Length
(MHz)	(MHz)	(ms)	N	(ms)	M	(ms)
7.0	5.824	5130	5	1026	54	19
10.0	8.320	3591	3	1197	63	19
10.5	8.512	3510	3	1170	65	18
14.0	11.648	2565	3	855	45	19
15.0	12.480	2394	2	1197	63	19

[0187] Sleep cycle slot #1 is always used for slow broadcast information. Slots #2 to #M-1 are used for paging groups unless extended slow broadcast information is inserted. The pattern of cycles and slots in one embodiment of the present invention run continuously at 16 kbs.

[0188] Within each sleep cycle the SU powers-up the receiver and re-acquires the pilot code. It then achieves carrier lock to a sufficient precision for satisfactory demodulation and Viterbi decoding. The settling time to achieve carrier lock may be up to 3 slots in duration. For example, an SU assigned to Slot #7 powers up the receiver at the start of slot #4. Having monitored its slot the SU will have either recognized its paging address and initiated an access request, or failed to recognize its paging address in which case it reverts to the sleep mode. Table 8 shows duty cycles for the different bandwidths, assuming a wake-up duration of 3 slots.

[0189]

TABLE 8
Sleep-Cycle Power Saving
Bandwidth (MHz)	Slots/Cycle	Duty Cycle
7.0	54	7.4%
10.0	63	6.3%
10.5	65	6.2%
14.0	45	8.9%
15.0	63	6.3%

[0190] Three CDMA spreading code tracking methods in multipath fading environments are described which track the code phase of a received multipath spread-spectrum signal. The first is the prior art tracking circuit which simply tracks the spreading code phase with the highest detector output signal value, the second is a tracking circuit that tracks the median value of the code phase of the group of multipath signals, and the third is the centroid tracking circuit which tracks the code-phase of an optimized, least mean squared weighted average of the multipath signal components. The following describes the algorithms by which the spreading code phase of the received CDMA signal is tracked.

[0191] A tracking circuit has operating characteristics that reveal the relationship between the time error and the control voltage that drives a voltage controlled oscillator (VCO) of a spreading code phase tracking circuit. When there is a positive timing error, the tracking circuit generates a negative control voltage to offset the timing error. When there is a negative timing error, the tracking circuit generates a positive control voltage to offset the timing error. When the tracking circuit generates a zero value, this value corresponds to the perfect time alignment called the ‘lock-point’.

[0192] FIG. 3c shows the basic tracking circuit. Received signal r(t) is applied to matched filter 301, which correlates r(t) with a local code-sequence c(t) generated by code generator 303. The output signal of the matched filter x(t) is sampled at the sampler 302 to produce samples x[nT] and x[nT+T/2]. The samples x[nT] and x[nT+T/2] are used by a tracking circuit 304 to determine if the phase of the spreading code c(t) of the code generator 303 is correct. The tracking circuit 304 produces an error signal e(t) as an input to the code generator 303. The code generator 303 uses this signal e(t) as an input signal to adjust the code-phase it generates.

[0193] In a CDMA system, the signal transmitted by the reference user is written in the low-pass representation as: $\begin{array}{cc}s\left(t\right)=\sum _{k=-\infty }^{\infty }{C}_k{P}_{\mathrm{Tc}}\left(t-{\mathrm{kT}}_c\right)& \text{Equation (7)}\end{array}$
where c_k represents the spreading code coefficients, P_Tc(t) represents the spreading code chip waveform and T_c is the chip duration. Assuming that the reference user is not transmitting data so that only the spreading code modulates the carrier. Referring to FIG. 3c, the received signal is: $\begin{array}{cc}r\left(t\right)=\sum _{i=1}^M{a}_{i}s\left(t-{\tau }_i\right)& \text{Equation (8)}\end{array}$
Here, a_i is due to fading effect of the multipath channel on the i-th path and τ_i is the random time delay associated with the same path. The receiver passes the received signal through a matched filter, which is implemented as a correlation receiver and is described below. This operation is done in two steps: first the signal is passed through a chip matched filter and sampled to recover the spreading code chip values; then this spreading code is correlated with the locally generated spreading code.

[0194] FIG. 3c shows the chip matched filter 301, matched to the chip waveform P_Tc(t), and the sampler 302. Ideally, the signal x(t) at the output terminal of the chip matched filter 301 is: $\begin{array}{cc}x\left(t\right)=\sum _{i=k}^M\sum _{k=-\infty }^{\infty }{a}_i{c}_{k}g\left(t-{\tau }_i-k{T}_c\right)& \text{Equation (9)}\end{array}$
where:
g(t)=P_Tc(t)*h_R(t)  Equation (10)
M is the number of multipath components. Here, h_R(t) is the impulse response of the chip matched filter 301 and ‘*’ denotes convolution. The order of the summations can be rewritten as: $\begin{array}{cc}x\left(t\right)=\sum _{k=-8}^{\infty }{c}_{k}f\left(t-k{T}_c\right)\text{where:}& \text{Equation (11)}\\ f\left(t\right)=\sum _{i=1}^M{a}_{i}g\left(t-{\tau }_i\right)& \text{Equation (12)}\end{array}$
In the multipath channel described above, the sampler 302 samples the output signal of the chip matched filter 301 to produce x(nT) at the maximum power level points of g(t). In practice, however, the waveform g(t) is severely distorted because of the effect of the multipath signal reception, and a perfect time alignment of the signals is not available.

[0195] When the multipath distortion in the channel is negligible and a perfect estimate of the timing is available, i.e., a₁=1, t₁=0, and a_i=0, i=2, . . . , M, the received s r(t)=s(t). Then, with this ideal channel model, the output of the chip matched filter becomes: $\begin{array}{cc}x\left(t\right)=\sum _{k=-\infty }^{\infty }{c}_{k}g\left(t-k{T}_c\right)& \text{Equation (13)}\end{array}$

[0196] When there is multipath fading, however, the received spreading code waveform is distorted, and has a number of local maxima that can change from one sampling interval to another depending on the channel characteristics. For multipath fading channels with quickly changing channel characteristics, it is not practical to try to locate the maximum of the waveform f(t) in every chip period interval. Instead, a time reference may be obtained from the characteristics of f(t) that may not change as quickly. Three tracking methods are described based on different characteristics of f(t).

[0197] Prior art tracking methods include a code tracking circuit in which the receiver attempts to determine the timing of the maximum matched filter output value of the chip waveform occurs and samples the signal accordingly. However, in multipath fading channels, the receiver despread code waveform can have a number of local maxima, especially in a mobile environment. In the following, f(t) represents the received signal waveform of the spreading code chip convolved with the channel impulse response. The frequency response characteristic of f(t) and the maximum of this characteristic can change rather quickly making it impractical to track the maximum of f(t).

[0198] Define τ to be the time estimate that the tracking circuit calculates during a particular sampling interval. Also, define the following error function as: $\begin{array}{cc}\varepsilon \{\int \underset{\left\{t:\tau -t>\delta \right\}}{f\left(t\right)dt}\tau -t>\delta \varepsilon =0\tau -t<\delta & \text{Equation (14)}\end{array}$
The tracking circuits of the prior art calculate a value of the input signal that minimizes the error ε. One can write: $\begin{array}{cc}\min \varepsilon =1-\max \tau {\int }_{t-\delta }^{\tau +\delta }f\left(t\right)& \text{Equation (15)}\end{array}$

[0199] Assuming f(τ) has a smooth shape in the values given, the value of τ for which f(τ) is maximum minimizes the error ε, so the tracking circuit tracks the maximum point of f(t).

[0200] The median weighted tracking method of one embodiment of the present invention, minimizes the absolute weighted error, defined as: $\begin{array}{cc}\varepsilon ={\int }_{-\infty }^{\infty }t-\tau f\left(t\right)dt& \text{Equation (16)}\end{array}$
This tracking method calculates the ‘median’ signal value of f(τ) by collecting information from all paths, where f(τ) is as in Equation 12. In a multipath fading environment, the waveform f(τ) can have multiple local maxima, but only one median. To minimize ε, the derivative of Equation (16) is taken with respect to τ and the result is equated to zero, which provides: $\begin{array}{cc}{\int }_{-\infty }^{\tau }f\left(t\right)dt={\int }_{\tau }^{\infty }f\left(t\right)dt& \text{Equation (17)}\end{array}$
The value of τ that satisfies Equation (17) is called the ‘median’ of f(t). Therefore, the median tracking method of the present embodiment tracks the median of f(t).

[0201] FIG. 4 shows an implementation of the tracking circuit based on minimizing the absolute weighted error defined above. The signal x(t) and its one-half chip offset version x(t+T/2) are sampled by the A/D 401 at a rate 1/T. The following Equation determines the operating characteristic of the circuit in FIG. 4: $\begin{array}{cc}\varepsilon \tau =\sum _{n=1}^{2L}f\left(\tau -nT/2\right)-f\left(\tau +nT/2\right)& \text{Equation (18)}\end{array}$

[0202] Tracking the median of a group of multipath signals keeps the received energy of the multipath signal components substantially equal on the early and late sides of the median point of the correct locally generated spreading code phase c_n. The tracking circuit consists of an A/D 401 which samples an input signal x(t) to form the half-chip offset samples. The half chip offset samples are grouped into an early set of samples and a late set of samples. The first correlation bank adaptive matched filter 402 multiplies each early sample by the spreading code phases c(n+1), c(n+2), . . . , c(n+L), where L is small compared to the code length and approximately equal to half the number of chips of delay between the earliest and latest multipath signal. The output of each correlator is applied to a respective first sum-and-dump bank 404. The magnitudes of the output values of the L sum-and-dumps are calculated in the calculator 406 and then summed in summer 408 to give an output value proportional to the signal energy in the early multipath signals. Similarly, a second correlation bank adaptive matched filter 403 operates on the late samples, using code phases c(n−1), c(n−2), . . . , c(n−L), and each output signal is applied to a respective sum-and-dump circuit in an integrator 405. The magnitudes of the L sum-and-dump output signals are calculated in calculator 407 and then summed in summer 409 to give a value for the late multipath signal energy. Finally, the subtractor 410 calculates the difference and produces error signal ε(t) of the early and late signal energy values.

[0203] The tracking circuit adjusts by means of error signal ε(t) the locally generated code phases c(t) to cause the difference between the early and late values to tend toward 0.

[0204] The optimal spreading code tracking circuit of one embodiment of the present invention is called the squared weighted tracking (or centroid) circuit. Defining t to denote the time estimate that the tracking circuit calculates, based on some characteristic of f(t), the centroid tracking circuit minimizes the squared weighted error defined as: $\begin{array}{cc}\varepsilon ={\int }_{-\infty }^{\infty }{t-\tau }^{2}f\left(t\right)dt& \mathrm{Equation}\left(19\right)\end{array}$
This function inside the integral has a quadratic form, which has a unique minimum. The value of t that minimizes e can be found by taking the derivative of the above Equation 19 with respect to t and equating to zero, which gives: $\begin{array}{cc}{\int }_{-\infty }^{\infty }\left(-2t+2\tau \right)f\left(t\right)dt=0& \text{Equation (20)}\end{array}$
Therefore, the value of t that satisfies Equation (21) is: $\begin{array}{cc}\tau -\frac{1}{\beta }{\int }_{-\infty }^{\infty }tf\left(t\right)dt=0& \text{Equation (21)}\end{array}$
is the timing estimate that the tracking circuit calculates, where β is a constant value.

[0205] Based on these observations, a realization of an exemplary tracking circuit which minimizes the squared weighted error is shown in FIG. 5a. The following Equation determines the error signal e(t) of the centroid tracking circuit: $\begin{array}{cc}\varepsilon \left(\tau \right)=\sum _{n=1}^{2L}n\left[f\left(\tau -nT/2\right)-f\left(\tau +nT/2\right)\right]=0& \text{Equation (22)}\end{array}$
The value that satisfies ε(t)=0 is the perfect estimate of the timing.

[0206] The early and late multipath signal energy on each side of the centroid point are equal. The centroid tracking circuit shown in FIG. 5a consists of an A/D converter 501 which samples an input signal x(t) to form the half-chip offset samples. The half chip offset samples are grouped as an early set of samples and a late set of samples. The first correlation bank adaptive matched filter 502 multiplies each early sample and each late sample by the positive spreading code phases c(n+1), c(n+2), . . . , c(n+L), where L is small compared to the code length and approximately equal to half the number of chips of delay between the earliest and latest multipath signal. The output signal of each correlator is applied to a respective one of L sum-and-dump circuits of the first sum and dump bank 504. The magnitude value of each sum-and-dump circuit of the sum and dump bank 504 is calculated by the respective calculator in the calculator bank 506 and applied to a corresponding weighting amplifier of the first weighting bank 508. The output signal of each weighting amplifier represents the weighted signal energy in a multipath component signal.

[0207] The weighted early multipath signal energy values are summed in sample adder 510 to give an output value proportional to the signal energy in the group of multipath signals corresponding to positive code phases which are the early multipath signals. Similarly, a second correlation bank adaptive matched filter 503 operates on the late samples, using the negative spreading code phases c(n−1), c(n−2), . . . , c(n−L); each output signal is provided to a respective sum-and-dump circuit of discrete integrator 505. The magnitude value of the L sum-and-dump output signals are calculated by the respective calculator of calculator bank 507 and then weighted in weighting bank 509. The weighted late multipath signal energy values are summed in sample adder 511 to give an energy value for the group of multipath signals corresponding to the negative code phases which are the late multipath signals. Finally, the adder 512 calculates the difference of the early and late signal energy values to produce error sample value ε(t).

[0208] The tracking circuit of FIG. 5a produces error signal ε(t) which is used to adjust the locally generated code phase c(nT) to keep the weighted average energy in the early and late multipath signal groups equal. The embodiment shown uses weighting values that increase as the distance from the centroid increases. The signal energy in the earliest and latest multipath signals is probably less than the multipath signal values near the centroid. Consequently, the difference calculated by the adder 510 is more sensitive to variations in delay of the earliest and latest multipath signals.

[0209] In this embodiment of the tracking method, the tracking circuit adjusts the sampling phase to be “optimal” and robust to multipath. Let f(t) represent the received signal waveform as in Equation 12 above. The particular method of optimizing starts with a delay locked loop with an error signal ε(t) that drives the loop. The function ε(t) must have only one zero at τ=τ₀ where τ₀ is optimal. The optimal form for ε(τ) has the canonical form: $\begin{array}{cc}\varepsilon \left(\tau \right)={\int }_{-\infty }^{\infty }w\left(t,\tau \right){f\left(t\right)}^{2}dt& \text{Equation (23)}\end{array}$
where w(t, t) is a weighting function relating f(t) to the error ε(T), and the relationship indicated by Equation (24) also holds: $\begin{array}{cc}\varepsilon \left(\tau +{\tau }_0\right)={\int }_{-\infty }^{\infty }w\left(t,\tau +{\tau }_0\right){f\left(t\right)}^{2}dt& \text{Equation (24)}\end{array}$

[0210] It follows from Equation (24) that w(t, τ) is equivalent to w(t−τ). Considering the slope M of the error signal in the neighborhood of a lock point τ₀: $\begin{array}{cc}{M=\frac{d\varepsilon \left(\tau \right)}{d\tau }}_{\mathrm{\tau 0}}=-{\int }_{-\infty }^{\infty }{w}^{\prime }\left(t-{\tau }_0\right)g\left(t\right)dt& \text{Equation (25)}\end{array}$
where w′(t, τ) is the derivative of w(t, τ) with respect to τ, and g(t) is the average of |f(t)|².

[0211] The error ε(t) has a deterministic part and a noise part. Let z denote the noise component in ε(t), then |z|² is the average noise power in the error function ε(t). Consequently, the optimal tracking circuit maximizes the ratio $\begin{array}{cc}F=\frac{M^2}{{z}^2}& \text{Equation (26)}\end{array}$

[0212] The implementation of the quadratic detector is now described. The discrete error value e of an error signal ε(t) is generated by performing the operation
ε=y^TBy  Equation (27)
where the vector y represents the received signal components yi, i=0, 1, . . . L−1, as shown in FIG. 5b. The matrix B is an L by L matrix and the elements are determined by calculating values such that the ratio F of Equation (26) is maximized. The quadratic detector described above may be used to implement the centroid tracking system described above with reference to FIG. 5a. For this implementation, the vector y is the output signal sum and dump circuits 504: y={f(τ−LT), f(τ−LT+T/2), f(τ−(L−1)T), . . . f(τ), f(τ+T/2), f(τ+T), . . . f(τ+LT)} and the matrix B is set forth in Table 9.

[0213]

TABLE 9
B matrix for quadratic form of Centroid Tracking System
L	0	0	0	0	0	0	0	0	0	0
0	L-1/2	0	0	0	0	0	0	0	0	0
0	0	L-1	0	0	0	0	0	0	0	0
.	.	.	.	.	.	.	.	.	.	.
.	.	.	.	.	.	.	.	.	.	.
.	.	.	.	.	.	.	.	.	.	.
0	0	0	0	1/2	0	0	0	0	0	0
0	0	0	0	0	0	0	0	0	0	0
0	0	0	0	0	0	−1/2	0	0	0	0
.	.	.	.	.	.	.	.	.	.	.
.	.	.	.	.	.	.	.	.	.	.
.	.	.	.	.	.	.	.	.	.	.
0	0	0	0	0	0	0	0	−L + 1	0	0
0	0	0	0	0	0	0	0	0	−L + 1/2	0
0	0	0	0	0	0	0	0	0	0	−L

[0214] The value of L in the previous section determines the minimum number of correlators and sum-and-dump elements. L is chosen as small as possible without promising the functionality of the tracking circuit.

[0215] The multipath characteristic of the channel is such that the received chip waveform f(t) is spread over QT_c seconds, or the multipath components occupy a time period of Q chips duration. The value of L chosen is L=Q. Q is found by measuring the particular RF channel transmission characteristics to determine the earliest and latest multipath component signal propagation delay. QT_c is the difference between the earliest and latest multipath component arrival time at a receiver.

[0216] An embodiment of the present invention uses an adaptive vector correlator (AVC) to estimate the channel impulse response and to obtain a reference value for coherent combining of received multipath signal components. The described embodiment employs an array of correlators to estimate the complex channel response affecting each multipath component. The receiver compensates for the channel response and coherently combines the received multipath signal components. This approach is referred to as maximal ratio combining.

[0217] Referring to FIG. 6, the input signal x(t) to the system includes interference noise of other message channels, multipath signals of the message channels, thermal noise, and multipath signals of the pilot signal. The signal is provided to AVC 601 which, in the exemplary embodiment, includes a despreading means 602, channel estimation means for estimating the channel response 604, correction means for correcting a signal for effects of the channel response 603 and adder 605. The AVC despreading means 602 is composed of multiple code correlators, with each correlator using a different phase of the pilot code c(t) provided by the pilot code generator 608. The output signal of this despreading means corresponds to a noise power level if the local pilot code of the despreading means is not in phase with the input code signal. Alternatively, it corresponds to a received pilot signal power level plus noise power level if the phases of the input pilot code and locally generated pilot code are the same. The output signals of the correlators of the despreading means are corrected for the channel response by the correction means 603 and are applied to the adder 605 which collects all multipath pilot signal power. The channel response estimation means 604 receives the combined pilot signal and the output signals of the despreading means 602, and provides a channel response estimate signal, w(t), to the correction means 603 of the AVC, and the estimate signal w(t) is also available to the adaptive matched filter (AMF) described below. The output signal of the despreading means 602 is also provided to the acquisition decision means 606 which decides, based on a particular algorithm such as a sequential probability ratio test (SPRT), if the present output levels of the despreading circuits correspond to synchronization of the locally generated spreading code to the desired input code phase. If the detector finds no synchronization, then the acquisition decision means sends a control signal a(t) to the local pilot code generator 608 to offset its phase by one or more chip period. When synchronization is found, the acquisition decision means informs tracking circuit 607, which achieves and maintains a close synchronization between the received and locally generated spreading codes.

[0218] An exemplary implementation of the pilot AVC used to despread the pilot spreading code is shown in FIG. 7. The described embodiment assumes that the input signal x(τ) has been sampled with sampling period T to form samples x(nT+τ), and is composed of interference noise of other message channels, multipath signals of message channels, thermal noise and multipath signals of the pilot code. The signal x(nT+τ) is applied to L correlators, where L is the number of code phases over which the uncertainty within the multipath signals exists. Each correlator 701, 702, 703 comprises a multiplier 704, 705, 706, which multiples the input signal with a particular phase of the pilot spreading code signal c((n+i)T) and sum-and-dump circuits 708, 709, 710. The output signal of each multiplier 704, 705, 706 is applied to a respective sum-and dump circuit 708, 709, 710 to perform discrete integration. Before summing the signal energy contained in the outputs of the correlators, the AVC compensates for the channel response and the carrier phase rotation of the different multipath signals. Each output of each sum-and-dump 708, 709, 710 is multiplied with a derotation phaser [complex conjugate of ep(nT)] from digital phase lock loop (DPLL) 721 by the respective multiplier 714, 715, 716 to account for the phase and frequency offset of the carrier signal. The pilot rake AMF calculates the weighting factors wk, k=1, . . . , L, for each multipath signal by passing the output of each multiplier 714, 715, 716 through a low pass filter (LPF) 711, 712, 713. Each despread multipath signal is multiplied by its corresponding weighting factor in a respective multiplier 717, 718, 719. The output signals of the multipliers 717, 718, 719 are summed in a master adder 720, and the output signal p(nT) of the accumulator 720 consists of the combined despread multipath pilot signals in noise. The output signal p(nT) is also input to the DPLL 721 to produce the error signal ep(nT) for tracking of the carrier phase.

[0219] FIGS. 8a and 8b show alternate embodiments of the AVC which can be used for detection and multipath signal component combining. The message signal AVCs of FIGS. 8a and 8b use the weighting factors produced by the pilot AVC to correct the message data multipath signals. The spreading code signal, c(nT) is the spreading code spreading sequence used by a particular message channel and is synchronous with the pilot spreading code signal. The value L is the number of correlators in the AVC circuit.

[0220] The circuit of FIG. 8a calculates the decision variable Z which is given by: $\begin{array}{cc}\begin{array}{c}Z=w_1\sum _{i=1}^{N}x\left(iT+\tau \right)c\left(iT\right)+\\ w_2\sum _{i=1}^{N}x\left(iT+\tau \right)c\left(\left(i+1\right)T\right)+\dots +\\ w_L\sum _{i=1}^{L}x\left(iT+\tau \right)+c\left(\left(i+L\right)T\right)\end{array}& \text{Equation (28)}\end{array}$
where N is the number of chips in the correlation window. Equivalently, the decision statistic is given by: $\begin{array}{cc}\begin{array}{c}Z=x\left(T+\tau \right)\sum _{i=1}^L{w}_{1}c\left(iT\right)\\ x\left(2T+\tau \right)\sum _{i=1}^L{w}_{1}c\left(\left(i+1\right)T\right)+\dots +\\ x\left(NT+\tau \right)\sum _{i=1}^L{w}_{N}c\left(\left(i+N\right)T\right)\\ =\sum _{k=1}^{N}x\left(kT-\tau \right)\sum _{i=1}^L{w}_{k}c\left(\left(i+k-1\right)T\right)\end{array}& \text{Equation (29)}\end{array}$
The alternative implementation that results from Equation (29) is shown in FIG. 8b.

[0221] Referring to FIG. 8a, the input signal x(t) is sampled to form x(nT+t), and is composed of interference noise of other message channels, multipath signals of message channels, thermal noise, and multipath signals of the pilot code. The signal x(nT+t) is applied to L correlators, where L is the number of code phases over which the uncertainty within the multipath signals exists. Each correlator 801, 802, 803 comprises a multiplier 804, 805, 806, which multiples the input signal by a particular phase of the message channel spreading code signal, and a respective sum-and-dump circuit 808, 809, 810. The output signal of each multiplier 804, 805, 806 is applied to a respective sum-and dump circuit 808, 809, 810 which performs discrete integration. Before summing the signal energy contained in the output signals of the correlators, the AVC compensates for the different multipath signals. Each despread multipath signal and its corresponding weighting factor, which is obtained from the corresponding multipath weighting factor of the pilot AVC, are multiplied in a respective multiplier 817, 818, 819. The output signals of multipliers 817, 818, 819 are summed in a master adder 820, and the output signal z(nT) of the accumulator 820 consists of sampled levels of a despread message signal in noise.

[0222] The alternative embodiment of the invention includes a new implementation of the AVC despreading circuit for the message channels which performs the sum-and-dump for each multipath signal component simultaneously. The advantage of this circuit is that only one sum-and dump circuit and one adder is necessary. Referring to FIG. 8b, the message code sequence generator 830 provides a message code sequence to shift register 831 of length L. The output signal of each register 832, 833, 834, 835 of the shift register 831 corresponds to the message code sequence shifted in phase by one chip. The output value of each register 832, 833, 834, 835 is multiplied in multipliers 836, 837, 838, 839 with the corresponding weighting factor w_k, k=1, . . . , L obtained from the pilot AVC. The output signals of the L multipliers 836, 837, 838, 839 are summed by the adding circuit 840. The adding circuit output signal and the receiver input signal x(nT+τ) are then multiplied in the multiplier 841 and integrated by the sum-and-dump circuit 842 to produce message signal z(nT).

[0223] A third embodiment of the adaptive vector correlator is shown in FIG. 8c. The embodiment shown uses the least mean square (LMS) statistic to implement the vector correlator and determines the decoration factors for each multipath component from the received multipath signal. The AVC of FIG. 8c is similar to the exemplary implementation of the Pilot AVC used to despread the pilot spreading code shown in FIG. 7. The digital phase locked loop 721 is replaced by the phase locked loop 850 having voltage controlled oscillator 851, loop filter 852, limiter 853 and imaginary component separator 854. The difference between the corrected despread output signal ido and an ideal despread output signal is provided by adder 855, and the difference signal is a despread error value ide which is further used by the decoration circuits to compensate for errors in the decoration factors.

[0224] In a multipath signal environment, the signal energy of a transmitted symbol is spread out over the multipath signal components. The advantage of multipath signal addition is that a substantial portion of signal energy is recovered in an output signal from the AVC. Consequently, a detection circuit has an input signal from the AVC with a higher signal-to-noise ratio (SNR), and so can detect the presence of a symbol with a lower bit-error ratio (BER). In addition, measuring the output of the AVC is a good indication of the transmit power of the transmitter, and a good measure of the system's interference noise.

[0225] One embodiment of the current invention includes an adaptive matched filter (AMF) to optimally combine the multipath signal components in a received spread spectrum message signal. The AMF is a tapped delay line which holds shifted values of the sampled message signal and combines these after correcting for the channel response. The correction for the channel response is done using the channel response estimate calculated in the AVC which operates on the pilot sequence signal. The output signal of the AMF is the combination of the multipath components which are summed to give a maximum value. This combination corrects for the distortion of multipath signal reception. The various message despreading circuits operate on this combined multipath component signal from the AMF. FIG. 8d shows an exemplary embodiment of the AMF. The sampled signal from the A/D converter 870 is applied to the L-stage delay line 872. Each stage of this delay line 872 holds the signal corresponding to a different multipath signal component. Correction for the channel response is applied to each delayed signal component by multiplying the component in the respective multiplier of multiplier bank 874 with the respective weighting factor w₁, w₂, . . . , w_L from the AVC corresponding to the delayed signal component. All weighted signal components are summed in the adder 876 to give the combined multipath component signal y(t).

[0226] The combined multipath component signal y(t) does not include the correction due to phase and frequency offset of the carrier signal. The correction for the phase and frequency offset of the carrier signal is made to y(t) by multiplying y(t) with carrier phase and frequency correction (derotation phaser) in multiplier 878. The phase and frequency correction is produced by the AVC as described previously. FIG. 8d shows the correction as being applied before the despreading circuits 880, but alternate embodiments of the invention can apply the correction after the despreading circuits.

[0227] One consequence of determining the difference in code phase between the locally generated pilot code sequence and a received spreading code sequence is that an approximate value for the distance between the base station and a subscriber unit can be calculated. If the SU has a relatively fixed position with respect to the RCS of the base station, the uncertainty of received spreading code phase is reduced for subsequent attempts at re-acquisition by the SU or RCS. The time required for the base station to acquire the access signal of a SU that has gone “off-hook” contributes to the delay between the SU going off-hook and the receipt of a dial tone from the PSTN. For systems that require a short delay, such as 150 msec for dial tone after off-hook is detected, a method which reduces the acquisition and bearer channel establishment time is desirable. One embodiment of the present invention uses such a method of reducing re-acquisition by use of virtual locating. Additional details of this technique are described in Section XXXXIII hereinafter entitled “Virtual Locating Of A Fixed Subscriber Unit To Reduce Re-Acquisition Time”.

[0228] The RCS acquires the SU CDMA signal by searching only those received code phases corresponding to the largest propagation delay of the particular system. In other words, the RCS assumes that all SUs are at a predetermined, fixed distance from the RCS. The first time the SU establishes a channel with the RCS, the normal search pattern is performed by the RCS to acquire the access channel. The normal method starts by searching the code phases corresponding to the longest possible delay, and gradually adjusts the search to the code phases with the shortest possible delay. However, after the initial acquisition, the SU can calculate the delay between the RCS and the SU by measuring the time difference between sending a short access signal to the RCS and receiving an acknowledgment signal, and using the received global pilot channel as a timing reference. The SU can also receive the delay value by having the RCS calculate the round trip delay difference from the code phase difference between the global pilot code generated at the RCS and the received assigned pilot code from the SU, and then sending the SU the value on a predetermined control channel. Once the round trip delay is known to the SU, the SU may adjust the code phase of the locally generated assigned pilot and spreading codes by adding the delay required to make the SU appear to the RCS to be at the predetermined fixed distance from the RCS. Although the method is explained for the largest delay, a delay corresponding to any predetermined location in the system can be used.

[0229] A second advantage of the method of reducing re-acquisition by virtual locating is that a conservation in SU power use can be achieved. Note that a SU that is “powered down” or in a sleep mode needs to start the bearer channel acquisition process with a low transmit power level and ramp-up power until the RCS can receive its signal in order to minimize interference with other users. Since the subsequent re-acquisition time is shorter, and because the SU's location is relatively fixed in relation to the RCS, the SU can ramp-up transmit power more quickly because the SU will wait a shorter period of time before increasing transmit power. The SU waits a shorter period because it knows, within a small error range, when it should receive a response from the RCS if the RCS has acquired the SU signal.

[0230] The Radio Carrier Station (RCS) of the present invention acts as a central interface between the SU and the remote processing control network element, such as a radio distribution unit (RDU). The interface to the RDU of the present embodiment follows the G.704 standard and an interface according to a modified version of DECT V5.1, but the present invention can support any interface that can exchange call control and traffic channels. The RCS receives information channels from the RDU including call control data, and traffic channel data such as, but not limited to, 32 kbs ADPCM, 64 kbs PCM and ISDN, as well as system configuration and maintenance data. The RCS also terminates the CDMA radio interface bearer channels with SUs, which channels include both control data, and traffic channel data. In response to the call control data from either the RDU or a SU, the RCS allocates traffic channels to bearer channels on the RF communication link and establishes a communication connection between the SU and the telephone network through an RDU.

[0231] As shown in FIG. 9, the RCS receives call control and message information data into the MUXs 905, 906 and 907 through interface lines 901, 902 and 903. Although E1 format is shown, other similar telecommunication formats can be supported in the same manner as described below. The MUXs shown in FIG. 9 may be implemented using circuits similar to that shown in FIG. 10. The MUX shown in FIG. 10 includes system clock signal generator 1001 consisting of phase locked oscillators (not shown) which generate clock signals for the line PCM highway 1002 (which is part of PCM highway 910), and high speed bus (HSB) 970; and the MUX controller 1010 which synchronizes the system clock 1001 to interface line 1004. It is contemplated that the phase lock oscillators can provide timing signals for the RCS in the absence of synchronization to a line. The MUX line interface 1011 separates the call control data from the message information data. Referring to FIG. 9, each MUX provides a connection to the wireless access controller (WAC) 920 through the PCM highway 910. The MUX controller 1010 also monitors the presence of different tones present in the information signal by means of tone detector 1030. Additionally, the MUX Controller 1010 provides the ISDN D channel network signaling locally to the RDU.

[0232] The MUX line interface 1011, such as a FALC 54, includes an E1 interface 1012 which consists of a transmit connection pair (not shown) and a receive connection pair (not shown) of the MUX connected to the RDU or central office (CO) ISDN switch at the data rate of 2.048 Mbps. The transmit and receive connection pairs are connected to the E1 interface 1012 which translates differential tri-level transmit/receive encoded pairs into levels for use by the framer 1015. The line interface 1011 uses internal phase-locked-loops (not shown) to produce E1-derived 2.048 MHz and 4.096 MHz clocks as well as an 8 KHz frame-sync pulse. The line interface can operate in clock-master or clock-slave mode. While the exemplary embodiment is shown as using an E1 interface, it is contemplated that other types of telephone lines which convey multiple calls may be used, for example, T1 lines or lines which interface to a private branch exchange (PBX).

[0233] The line interface framer 1015 frames the data streams by recognizing the framing patterns on channel-1 (time-slot 0) of the incoming line, inserts and extracts service bits and generates/checks line service quality information.

[0234] As long as a valid E1 signal appears at the E1 interface 1012, the FALC 54, recovers a 2.048 MHz PCM clock signal from the E1 line. This clock, via system clock 1001, is used system wide as a PCM highway clock signal. If the E1 line fails, the FALC 54 continues to deliver a PCM clock derived from an oscillator signal o(t) connected to the sync input (not shown) of the FALC 54. This PCM clock serves the RCS system until another MUX with an operational E1 line assumes responsibility for generating the system clock signals.

[0235] The framer 1015 generates a received frame sync pulse, which in turn can be used to trigger the PCM Interface 1016 to transfer data onto the line PCM highway 1002 and into the RCS system for use by other elements. Since all E1 lines are frame synchronized, all line PCM highways are also frame synchronized. From this 8 kHz PCM Sync pulse, the system clock signal generator 1001 of the MUX uses a phase locked loop (not shown) to synthesize the PN×2 clock (e.g., 15.96 MHz)(W₀(t)). The frequency of this clock signal is different for different transmission bandwidths as described in Table 7.

[0236] The MUX includes a MUX controller 1010, such as a 25 MHz quad integrated communications controller, containing a microprocessor 1020, program memory 1021, and time division multiplexer (TDM) 1022. The TDM 1022 is coupled to receive the signal provided by the framer 1015, and extracts information placed in time slots 0 and 16. The extracted information governs how the MUX controller 1010 processes the link access protocol—D (LAPD) data link. The call control and bearer modification messages, such as those defined as V5.1 network layer messages, are either passed to the WAC, or used locally by the MUX controller 1010.

[0237] The RCS line PCM highway 1002 is connected to and originates with the framer 1015 through PCM Interface 1016, and comprises of a 2.048 MHz stream of data in both the transmit and receive direction. The RCS also contains a high speed bus (HSB) 970 which is the communication link between the MUX, WAC, and MIUs. The HSB 970 supports a data rate of, for example, 100 Mbit/sec. Each of the MUX, WAC, and MIU access the HSB using arbitration. The RCS of the present invention also can include several MUXs requiring one board to be a “master” and the rest “slaves”. Details on the implementation of the HSB may be found in Section XXXXIV hereinafter entitled PARALLEL PACKETIZED INTERMODULE ARBITRATED HIGH SPEED CONTROL AND DATA BUS.

[0238] Referring to FIG. 9, the wireless access controller (WAC) 920 is the RCS system controller which manages call control functions and interconnection of data streams between the MUXs 905, 906, 907, modem interface units (MIUs) 931, 932, 933. The WAC 920 also controls and monitors other RCS elements such as the VDC 940, RF 950, and power amplifiers 960. The WAC 920 as shown in FIG. 11, allocates bearer channels to the modems on each MIU 931, 932, 933 and allocates the message data on line PCM Highway 910 from the MUXs 905, 906, 907 to the modems on the MIUs 931, 932, 933. This allocation is made through the System PCM Highway 911 by means of a time slot interchange on the WAC 920. If more than one WAC is present for redundancy purposes, the WACs determines the master-slave relationship with a second WAC. The WAC 920 also generates messages and paging information responsive to call control signals from the MUXs 905, 906, 907 received from a remote processor, such as an RDU; generates broadcast data which is transmitted to the MIU master modem 934; and controls the generation by the MIU MM 934 of the Global system Pilot spreading code sequence. The WAC 920 also is connected to an external network manager (NM) 980 for crafts person or user access.

[0239] Referring to FIG. 11, the WAC includes a time-slot interchanger (TSI) 1101 which transfers information from one time slot in a line PCM highway or system PCM highway to another time slot in either the same or different line PCM highway or system PCM highway. The TSI 1101 is connected to the WAC controller 1111 of FIG. 11 which controls the assignment or transfer of information from one time slot to another time slot and stores this information in memory 1120. The exemplary embodiment of the invention has four PCM Highways 1102, 1103, 1104, 1105 connected to the TSI. The WAC also is connected to the HSB 970, through which WAC communicates to a second WAC (not shown), to the MUXs and to the MIUs.

[0240] Referring to FIG. 11, the WAC 920 includes a WAC controller 1111 employing, for example, a microprocessor 1112, such as a Motorola MC 68040 and a communications processor 1113, such as the Motorola MC68360 QUICC communications processor, and a clock oscillator 1114 which receives a clock synch signal wo(t) from the system clock generator. The clock generator is located on a MUX (not shown) to provide timing to the WAC controller 1111. The WAC controller 1111 also includes memory 1120 including flash PROM 1121 and SRAM memory 1122. The flash PROM 1121 contains the program code for the WAC controller 1111 and is reprogrammable for new software programs downloaded from an external source. The SRAM 1122 is provided to contain the temporary data written to and read from memory 1120 by the WAC controller 1111.

[0241] A low speed bus 912 is connected to the WAC 920 for transferring control and status signals between the RF transmitter/receiver 950, VDC 940, RF 950 and power amplifier 960 as shown in FIG. 9. The control signals are sent from the WAC 920 to enable or disable the RF transmitters/receiver 950 or power amplifier 960, and the status signals are sent from the RF transmitters/receiver 950 or power amplifier 960 to monitor the presence of a fault condition.

[0242] The exemplary RCS contains at least one MIU 931, which is shown in FIG. 12 and now described in detail. The MIU of the exemplary embodiment includes six CDMA modems, but the invention is not limited to this number of modems. The MIU includes a system PCM highway 1201 connected to each of the CDMA Modems 1210, 1211, 1212, 1215 through a PCM Interface 1220, a control channel bus 1221 connected to MIU controller 1230 and each of the CDMA modems 1210, 1211, 1212, 1213, an MIU clock signal generator (CLK) 1231, and a modem output combiner 1232. The MIU provides the RCS with the following functions: the MIU controller receives CDMA channel assignment instructions from the WAC and assigns a modem to a user information signal which is applied to the line interface of the MUX and a modem to receive the CDMA channel from the SU; it also combines the CDMA transmit modem data for each of the MIU CDMA modems; multiplexes I and Q transmit message data from the CDMA modems for transmission to the VDC; receives analog I and Q receive message data from the VDC; distributes the I and Q data to the CDMA modems; transmits and receives digital AGC data; distributes the AGC data to the CDMA modems; and sends MIU board status and maintenance information to the WAC 920.

[0243] The MIU controller 1230 of the exemplary embodiment of the present invention contains one communication microprocessor 1240, such as the MC68360 “QUICC” processor, and includes a memory 1242 having a Flash PROM memory 1243 and a SRAM memory 1244. Flash PROM 1243 is provided to contain the program code for the microprocessors 1240, and the memory 1243 is downloadable and reprogrammable to support new program versions. SRAM 1244 is provided to contain the temporary data space needed by the MC68360 microprocessor 1240 when the MIU controller 1230 reads or writes data to memory

[0244] The MIU CLK circuit 1231 provides a timing signal to the MIU controller 1230, and also provides a timing signal to the CDMA modems. The MIU CLK circuit 1231 receives, and is synchronized to, the system clock signal wo(t). The controller clock signal generator 1213 also receives and synchronizes to the spreading code clock signal pn(t) which is distributed to the CDMA modems 1210, 1211, 1212, 1215 from the MUX.

[0245] The RCS of the present embodiment includes a system modem 1210 contained on one MIU. The system modem 1210 includes a broadcast spreader (not shown) and a pilot generator (not shown). The broadcast modem provides the broadcast information used by the exemplary system, and the broadcast message data is transferred from the MIU controller 1230 to the system modem 1210. The system modem also includes four additional modems (not shown) which are used to transmit the signals CT1 through CT4 and AX1 through AX4. The system modem 1210 provides unweighted I and Q broadcast message data signals which are applied to the VDC. The VDC adds the broadcast message data signal to the MIU CDMA modem transmit data of all CDMA modems 1210, 1211, 1212, 1215 and the global pilot signal.

[0246] The pilot generator (PG) 1250 provides the global pilot signal which is used by the present invention, and the global pilot signal is provided to the CDMA modems 1210, 1211, 1212, 1215 by the MIU controller 1230. However, other embodiments of the present invention do not require the MIU controller to generate the global pilot signal, but include a global pilot signal generated by any form of CDMA spreading code generator. In the described embodiment of the invention, the unweighted I and Q global pilot signal is also sent to the VDC where it is assigned a weight, and added to the MIU CDMA modem transmit data and broadcast message data signal.

[0247] System timing in the RCS is derived from the E1 interface. There are four MUXs in an RCS, three of which (905, 906 and 907) are shown in FIG. 9. Two MUXs are located on each chassis. One of the two MUXs on each chassis is designated as the master, and one of the masters is designated as the system master. The MUX which is the system master derives a 2.048 MHz PCM clock signal from the E1 interface using a phase-locked loop (not shown). In turn, the system master MUX divides the 2.048 Mhz PCM clock signal in frequency by 16 to derive a 128 KHz reference clock signal. The 128 KHz reference clock signal is distributed from the MUX that is the system master to all the other MUXs. In turn, each MUX multiplies the 128 KHz reference clock signal in frequency to synthesize the system clock signal which has a frequency that is twice the frequency of the PN-clock signal. The MUX also divides the 128 KHz clock signal in frequency by 16 to generate the 8 KHz frame synch signal which is distributed to the MIUs. The system clock signal for the exemplary embodiment has a frequency of 11.648 Mhz for a 7 MHz bandwidth CDMA channel Each MUX also divides the system clock signal in frequency by 2 to obtain the PN-clock signal and further divides the PN-clock signal in frequency by 29 877 120 (the PN sequence length) to generate the PN-synch signal which indicates the epoch boundaries. The PN-synch signal from the system master MUX is also distributed to all MUXs to maintain phase alignment of the internally generated clock signals for each MUX. The PN-synch signal and the frame synch signal are aligned. The two MUXs that are designated as the master MUXs for each chassis then distribute both the system clock signal and the PN-clock signal to the MIUs and the VDC.

[0248] The PCM highway interface 1220 connects the system PCM highway 911 to each CDMA modem 1210, 1211, 1212, 1215. The WAC controller transmits modem control information, including traffic message control signals for each respective user information signal to the MIU controller 1230 through the HSB 970. Each CDMA modem 1210, 1211, 1212, 1215 receives a traffic message control signal, which includes signaling information, from the MIU controller 1111. Traffic message control signals also include call control (CC) information and spreading code and despreading code sequence information.

[0249] The MIU also includes the transmit data combiner 1232 which adds weighted CDMA modem transmit data including in-phase (I) and quadrature (Q) modem transmit data from the CDMA modems 1210, 1211, 1212, 1215 on the MIU. The I modem transmit data is added separately from the Q modem transmit data. The combined I and Q modem transmit data output signal of the transmit data combiner 1232 is applied to the I and Q multiplexer 1233 that creates a single CDMA transmit message channel composed of the I and Q modem transmit data multiplexed into a digital data stream.

[0250] The receiver data input Circuit (RDI) 1234 receives the analog differential I and Q Data from the video distribution circuit (VDC) 940 shown in FIG. 9 and distributes analog differential I and Q data to each of the CDMA modems 1210, 1211, 1212, 1215 of the MIU. The automatic gain control (AGC) distribution circuit 1235 receives the AGC data signal from the VDC and distributes the AGC data to each of the CDMA modems of the MIU. The TRL circuit 1233 receives the traffic lights information and similarly distributes the Traffic light data to each of the Modems 1210, 1211, 1212, 1215.

[0251] The CDMA modem provides for generation of CDMA spreading codes and synchronization between transmitter and receiver. It also provides four full duplex channels (TR0, TR1, TR2, TR3) programmable to 64, 32, 16, and 8 ksym/sec. each, for spreading and transmission at a specific power level. The CDMA modem measures the received signal strength to allow automatic power control, it generates and transmits pilot signals, and encodes and decodes using the signal for forward error correction (FEC). The modem in an SU also performs transmitter spreading code pulse shaping using an FIR filter. The CDMA modem is also used by the subscriber unit (SU), and in the following discussion those features which are used only by the SU are distinctly pointed out. The operating frequencies of the CDMA modem are given in Table 10.

[0252]

TABLE 10
Operating Frequencies
	Bandwidth	Chip Rate	Symbol Rate	Gain
	(MHz)	(MHz)	(KHz)	(Chips/Symbol)
	7	5.824	64	91
	10	8.320	64	130
	10.5	8.512	64	133
	14	11.648	64	182
	15	12.480	64	195

Each CDMA modem 1210, 1211, 1212, 1215 of FIG. 12, and as shown in FIG. 13, is composed of a transmit section 1301 and a receive section 1302. Also included in the CDMA modem is a control center 1303 which receives control messages CNTRL from the external system. These messages are used, for example, to assign particular spreading codes, activate the spreading or despreading or to assign transmission rates. In addition, the CDMA modem has a code generator means 1304 used to generate the various spreading and despreading codes used by the CDMA modem. The transmit section 1301 is for transmitting the input information and control signals m_i(t), i=1, 2, . . . I as spread-spectrum processed user information signals sc_j(t), j=1, 2, . . . J. The transmit section 1301 receives the global pilot code from the code generator 1304 which is controlled by the control means 1303. The spread spectrum processed user information signals are ultimately added to other similar processed signals and transmitted as CDMA channels over the CDMA RF forward message link, for example to the SUs. The receive section 1302 receives CDMA channels as r(t) and despreads and recovers the user information and control signals rc_k(t), k=1, 2, . . . K transmitted over the CDMA RF reverse message link, for example to the RCS from the SUs.

[0253] Referring to FIG. 14, the code generator means 1304 includes transmit timing control logic 1401 and spreading code PN-generator 1402, and the transmit section 1301 includes modem input signal receiver (MISR) 1410, convolution encoders 1411, 1412, 1413, 1414, spreaders 1420, 1421, 1422, 1423, 1424 and combiner 1430. The transmit section 1301 receives the message data channels MESSAGE, convolutionally encodes each message data channel in the respective convolutional encoder 1411, 1412, 1413, 1414, modulates the data with random spreading code sequence in the respective spreader 1420, 1421, 1422, 1423, 1424, and combines modulated data from all channels, including the pilot code received in the described embodiment from the code generator, in the combiner 1430 to generate I and Q components for RF transmission. The transmitter section 1301 of the present embodiment supports four (TR0, TR1, TR2, TR3) 64, 32, 16, 8 kbs programmable channels. The message channel data is a time multiplexed signal received from the PCM highway 1201 through PCM interface 1220 and input to the MISR 1410.

[0254] FIG. 15 is a block diagram of an exemplary MISR 1410. For the exemplary embodiment of the present invention, a counter is set by the 8 KHz frame synchronization signal MPCMSYNC and is incremented by 2.048 MHz MPCMCLK from the timing circuit 1401. The counter output is compared by comparator 1502 against TRCFG values corresponding to slot time location for TR0, TR1, TR2, TR3 message channel data; and the TRCFG values are received from the MIU controller 1230 in MCTRL. The comparator sends count signal to the registers 1505, 1506, 1507 and 1508 which clocks message channel data into buffers 1510, 1511, 1512, 1513 using the TXPCNCLK timing signal derived from the system clock. The message data is provided from the signal MSGDAT from the PCM highway signal MESSAGE when enable signals TR0EN, TR1EN, TR2EN and TR3EN from timing control logic 1401 are active. In further embodiments, MESSAGE may also include signals that enable registers depending upon an encryption rate or data rate. If the counter output is equal to one of the channel location addresses, the specified transmit message data in registers 1510, 1511, 1512, 1513 are input to the convolutional encoders 1411, 1412, 1413, 1414 shown in FIG. 14.

[0255] The convolutional encoder enables the use of forward error correction (FEC) techniques, which are well known in the art. FEC techniques depend on introducing redundancy in generation of data in encoded form. Encoded data is transmitted and the redundancy in the data enables the receiver decoder device to detect and correct errors. One embodiment of the present invention employs convolutional encoding. Additional data bits are added to the data in the encoding process and are the coding overhead. The coding rate is expressed as the ratio of data bits transmitted to the total bits (code data+redundant data) transmitted and is called the rate “R” of the code.

[0256] Convolution codes are codes where each code bit is generated by the convolution of each new uncoded bit with a number of previously coded bits. The total number of bits used in the encoding process is referred to as the constraint length (K) of the code. In convolutional coding, data is clocked into a shift register of K bits length so that an incoming bit is clocked into the register, and it and the existing K−1 bits are convolutionally encoded to create a new symbol. The convolution process consists of creating a symbol consisting of a module-2 sum of a certain pattern of available bits, always including the first bit and the last bit in at least one of the symbols.

[0257] FIG. 16 shows the block diagram of a K=7, R=½ convolution encoder suitable for use as the encoder 1411 shown in FIG. 14. This circuit encodes the TR0 channel as used in one embodiment of the present invention. Seven-bit register 1601 with stages Q1 through Q7 uses the signal TXPNCLK to clock in TR0 data when the TR0EN signal is asserted. The output value of stages Q1, Q2, Q3, Q4, Q6, and Q7 are each combined using EXCLUSIVE-OR Logic 1602, 1603 to produce respective I and Q channel FEC data for the TR0 channel FECTR0DI and FECTR0DQ.

[0258] Two output symbol streams FECTR0DI and FECTR0DQ are generated. The FECTR0DI symbol stream is generated by EXCLUSIVE OR logic 1602 of shift register outputs corresponding to bits 6, 5, 4, 3, and 0, (Octal 171) and is designed as In phase component “I” of the transmit message channel data. The symbol stream FECTR0DQ is likewise generated by EXCLUSIVE-OR logic 1603 of shift register outputs from bits 6, 43, 1 and 0, (Octal 133) and is designated as Quadrature component “Q” of the transmit message channel data. Two symbols are transmitted to represent a single encoded bit creating the redundancy necessary to enable error correction to take place on the receiving end.

[0259] Referring to FIG. 14, the shift enable clock signal for the transmit message channel data is generated by the control timing logic 1401. The convolutionally encoded transmit message channel output data for each channel is applied to the respective spreader 1420, 1421, 1422, 1423, 1424 which multiplies the transmit message channel data by its preassigned spreading code from code generator 1402. This spreading code is generated by control 1303 as previously described, and is called a random pseudonoise signature code (PN-code).

[0260] The output signal of each spreader 1420, 1421, 1422, 1423, 1424 is a spread transmit data channel. The operation of the spreader is as follows: the spreading of channel output (I+jQ) multiplied by a random sequence (PNI+jPNQ) yields the in-phase component I of the result being composed of (I xor PNI) and (−Q xor PNQ). Quadrature component Q of the result is (Q xor PNI) and (I xor PNQ). Since there is no channel data input to the pilot channel logic (I=1, Q values are prohibited), the spread output signal for pilot channels yields the respective sequences PNI for I component and PNQ for Q component.

[0261] The combiner 1430 receives the I and Q spread transmit data channels and combines the channels into an I modem transmit data signal (TXIDAT) and a Q modem transmit data signal (TXQDAT). The I-spread transmit data and the Q spread transmit data are added separately.

[0262] For an SU, the CDMA modem transmit section 1301 includes the FIR filters to receive the I and Q channels from the combiner to provide pulse shaping, close-in spectral control and x/sin (x) correction for the transmitted signal. Separate but identical FIR filters receive the I and Q spread transmit data streams at the chipping rate, and the output signal of each of the filters is at twice the chipping rate. The exemplary FIR filters are 28 tap even symmetrical filters, which upsample (interpolate) by 2. The upsampling occurs before the filtering, so that 28 taps refers to 28 taps at twice the chipping rate, and the upsampling is accomplished by setting every other sample a zero. Exemplary coefficients are shown in Table 11.

[0263]

TABLE 11
Coefficient Values
Coeff. No.:	0	1	2	3	4	5	6	7	8	9	10	11	12	13
Value:	3	−11	−34	−22	19	17	−32	−19	52	24	−94	−31	277	468
Coeff. No.	14	15	16	17	18	19	20	21	22	24	25	26	27
Value	277	−31	−94	24	52	−19	−32	17	19	−22	−34	−11

[0264] Referring to FIGS. 9 and 12, the RF receiver 950 of the present embodiment accepts analog input I and Q CDMA channels, which are transmitted to the CDMA modems 1210, 1211, 1212, 1215 through the MIUs 931, 932, 933 from the VDC 940. These I and Q CMDA channel signals are sampled by the CDMA modem receive section 1302 (shown in FIG. 13) and converted to I and Q digital receive message signal using an analog to digital (A/D) converter 1730, shown in FIG. 17. The sampling rate of the A/D converter of the exemplary embodiment of the present invention is equivalent to the despreading code rate. The I and Q digital receive message signals are then despread with correlators using six different complex spreading code sequences corresponding to the despreading code sequences of the four channels (TR0, TR1, TR2, TR3), APC information and the pilot code.

[0265] Time synchronization of the receiver to the received signal is separated into two phases; there is an initial acquisition phase and then a tracking phase after the signal timing has been acquired. The initial acquisition is done by shifting the phase of the locally generated pilot code sequence relative to the received signal and comparing the output of the pilot despreader to a threshold. The method used is called sequential search. Two thresholds (match and dismiss) are calculated from the auxiliary despreader. Once the signal is acquired, the search process is stopped and the tracking process begins. The tracking process maintains the code generator 1304 (shown in FIGS. 13 and 17) used by the receiver in synchronization with the incoming signal. The tracking loop used is the delay-locked loop (DLL) and is implemented in the acquisition & track 1701 and the IPM 1702 blocks of FIG. 17.

[0266] In FIG. 13, the modem controller 1303 implements the phase lock loop (PLL) as a software algorithm in SW PLL logic 1724 of FIG. 17 that calculates the phase and frequency shift in the received signal relative to the transmitted signal. The calculated phase shifts are used to derotate the phase shifts in rotate and combine blocks 1718, 1719, 1720, 1721 of the multipath data signals for combining to produce output signals corresponding to receive channels TR0′, TR1′, TR2′, TR3′. The data is then Viterbi decoded in Viterbi decoders 1713, 1714, 1715, 1716 to remove the convolutional encoding in each of the received message channels.

[0267] FIG. 17 indicates that the Code Generator 1304 provides the code sequences Pn_i(t), i=1, 2, . . . I used by the receive channel despreaders 1703, 1704, 1705, 1706, 1707, 1708, 1709. The code sequences generated are timed in response to the SYNK signal of the system clock signal and are determined by the CCNTRL signal from the modem controller 1303 shown in FIG. 13. Referring to FIG. 17, the CDMA modem receiver section 1302 includes adaptive matched filter (AMF) 1710, channel despreaders 1703, 1704, 1705, 1706, 1707, 1708, 1709, pilot AVC 1711, auxiliary AVC 1712, Viterbi decoders 1713, 1714, 1715, 1716, modem output interface (MOI) 1717, rotate and combine logic 1718, 1719, 1720, 1721, AMF weight generator 1722, and quantile estimation logic 1723.

[0268] In another embodiment of the invention, the CDMA modem receiver also includes a bit error integrator to measure the BER of the channel and idle code insertion logic between the Viterbi decoders 1713, 1714, 1715, 1716 and the MOI 1717 to insert idle codes in the event of loss of the message data.

[0269] The AMF 1710 resolves multipath interference introduced by the air channel. The exemplary AMF 1710 uses an 11 stage complex FIR filter as shown in FIG. 18. The received I and Q digital message signals are received at the register 1820 from the A/D 1730 of FIG. 17 and are multiplied in multipliers 1801, 1802, 1803, 1810, 1811 by I and Q channel weights W1 to W11 received from AMF weight generator 1722 of FIG. 17. In the exemplary embodiment, the A/D 1730 provides the I and Q digital receive message signal data as 2's complement values, 6 bits for I and 6 bits for Q which are clocked through an 11 stage shift register 1820 responsive to the receive spreading-code clock signal RXPNCLK. The signal RXPNCLK is generated by the timing section 1401 of code generation logic 1304. Each stage of the shift register is tapped and complex multiplied in the multipliers 1801, 1802, 1803, 1810, 1811 by individual (6-bit I and 6-bit Q) weight values to provide 11 tap-weighted products which are summed in adder 1830, and limited to 7-bit I and 7-bit Q values.

[0270] The CDMA modem receive section 1302 (shown in FIG. 13) provides independent channel despreaders 1703, 1704, 1705, 1706, 1707, 1708, 1709 (shown in FIG. 17) for despreading the message channels. The described embodiment despreads 7 message channels, each despreader accepting a 1-bit I b 1-bit Q despreading code signal to perform a complex correlation of this code against a 8-bit I by 8-bit Q data input. The 7 despreaders correspond to the 7 channels: traffic channel 0 (TR0′), TR1′, TR2′, TR3′, AUX (a spare channel), APC and pilot (PLT).

[0271] The pilot AVC 1711 shown in FIG. 19 receives the I and Q pilot spreading code sequence values PCI and PCQ into shift register 1920 responsive to the timing signal RXPNCLK, and includes 11 individual despreaders 1901 through 1911 each correlating the I and Q digital receive message signal data with a one chip delayed version of the same pilot code sequence. Signals OE1, OE2, . . . OE11 are used by the modem control 1303 to enable the despreading operation. The output signals of the despreaders are combined in combiner 1920 forming correlation signal DSPRDAT of the Pilot AVC 1711, which is received by the ACQ & track logic 1701 (shown in FIG. 17), and ultimately by modem controller 1303 (shown in FIG. 13). The ACQ & track logic 1701 uses the correlation signal value to determine if the local receiver is synchronized with its remote transmitter.

[0272] The auxiliary AVC 1712 also receives the I and Q digital receive message signal data and, in the described embodiment, includes four separate despreaders 2001, 2002, 2003, 2004 as shown in FIG. 20. Each despreader receives and correlates the I and Q digital receive message data with delayed versions of the same despreading code sequence PARI and PARQ which are provided by code generator 1304 input to and contained in shift register 2020. The output signals of the despreaders 2001, 2002, 2003, 2004 are combined in combiner 2030 which provides noise correlation signal ARDSPRDAT. The auxiliary AVC spreading code sequence does not correspond to any transmit spreading code sequence of the system. Signals OE1, OE2, . . . OE4 are used by the modem control 1303 to enable the despreading operation. The Auxiliary AVC 1712 provides a noise correlation signal ARDSPRDAT from which quantile estimates are calculated by the Quantile estimator 1733, and provides a noise level measurement to the ACQ & Track logic 1701 (shown in FIG. 17) and modem controller 1303 (shown in FIG. 13).

[0273] Each despread channel output signal corresponding to the received message channels TR0′, TR1′, TR2′, and TR3′ is input to a corresponding Viterbi decoder 1713, 1714, 1715, 1716 shown in FIG. 17 which performs forward error correction on convolutionally encoded data. The Viterbi decoders of the exemplary embodiment have a constraint length of K=7 and a rate of R=½. The decoded despread message channel signals are transferred from the CDMA modem to the PCM Highway 1201 through the MOI 1717. The operation of the MOI is essentially the same as the operation of the MISR of the transmit section 1301 (shown in FIG. 13) except in reverse.

[0274] The CDMA modem receiver section 1302 implements several different algorithms during different phases of the acquisition, tracking and despreading of the receive CDMA message signal.

[0275] When the received signal is momentarily lost (or severely degraded) the idle code insertion algorithm inserts idle codes in place of the lost or degraded receive message data to prevent the user from hearing loud noise bursts on a voice call. The idle codes are sent to the MOI 1717 (shown in FIG. 17) in place of the decoded message channel output signal from the Viterbi decoders 1713, 1714, 1715, 1716. The idle code used for each traffic channel is programmed by the Modem Controller 1303 by writing the appropriate pattern IDLE to the MOI, which in the present embodiment is a 8 bit word for a 64 kbs stream, 4 bit word for a 32 kbs stream.

[0276] The acquisition and tracking algorithms are used by the receiver to determine the approximate code phase of a received signal, synchronize the local modem receiver despreaders to the incoming pilot signal, and track the phase of the locally generated pilot code sequence with the received pilot code sequence. Referring to FIGS. 13 and 17, the algorithms are performed by the modem controller 1303, which provides clock adjust signals to code generator 1304. These adjust signals cause the code generator for the despreaders to adjust locally generated code sequences in response to measured output values of the pilot rake 1711 and quantile values from quantile estimators 1723B. Quantile values are noise statistics measured from the in-phase and quadrature channels from the output values of the AUX vector correlator 1712 (shown in FIG. 17). Synchronization of the receiver to the received signal is separated into two phases; an initial acquisition phase and a tracking phase. The initial acquisition phase is accomplished by clocking the locally generated pilot spreading code sequence at a higher or lower rate than the received signal's spreading code rate, sliding the locally generated pilot spreading code sequence and performing sequential probability ratio test (SPRT) on the output of the pilot vector correlator 1711. The tracking phase maintains the locally generated spreading code pilot sequence in synchronization with the incoming pilot signal. Details of the quantile estimators 1723B may be found in U.S. Pat. No. 5,535,238 entitled “ADAPTIVE POWER CONTROL FOR A SPREAD SPECTRUM COMMUNICATIONS SYSTEM” which is incorporated by reference herein for its teachings on adaptive power control systems.

[0277] The SU cold acquisition algorithm is used by the SU CDMA modem when it is first powered up, and therefore has no knowledge of the correct pilot spreading code phase, or when an SU attempts to reacquire synchronization with the incoming pilot signal but has taken an excessive amount of time. The cold acquisition algorithm is divided into two sub-phases. The first subphase consists of a search over the length 233415 code used by the FBCH. Once this sub-code phase is acquired, the pilot's 233415×128 length code is known to within an ambiguity of 128 possible phases. The second subphase is a search of these remaining 128 possible phases. In order not to lose synch with the FBCH, in the second phase of the search, it is desirable to switch back and forth between tracking of the FBCH code and attempting acquisition of the pilot code.

[0278] The RCS acquisition of short access pilot (SAXPT) algorithm is used by an RCS CDMA modem to acquire the SAXPT pilot signal of an SU. Additional details of this technique are described in Section XXXXII hereinafter entitled “A Method Of Controlling Initial Power Ramp-Up In CDMA Systems By Using Short Codes” filed on even date herewith and herein incorporated by reference. The algorithm is a fast search algorithm because the SAXPT is a short code sequence of length N, where N=chips/symbol, and ranges from 45 to 195, depending on the system's bandwidth. The search cycles through all possible phases until acquisition is complete.

[0279] The RCS acquisition of the long access pilot (LAXPT) algorithm begins immediately after acquisition of SAXPT. The SU's code phase is known within a multiple of a symbol duration, so in the exemplary embodiment of the invention there may be 7 to 66 phases to search within the round trip delay from the RCS. This bound is a result of the SU pilot signal being synchronized to the RCS global pilot signal.

[0280] The re-acquisition algorithm begins when loss of code lock (LOL) occurs. A Z-search algorithm is used to speed the process on the assumption that the code phase has not drifted far from where it was the last time the system was locked. The RCS uses a maximum width of the Z-search windows bounded by the maximum round trip propagation delay.

[0281] The pre-track period immediately follows the acquisition or re-acquisition algorithms and immediately precedes the tracking algorithm. Pre-track is a fixed duration period during which the receive data provided by the modem is not considered valid. The pre-track period allows other modem algorithms, such as those used by the ISW PLL 1724, ACQ & tracking, AMF weight GEN 1722, to prepare and adapt to the current channel. The pre-track period is two parts. The first part is the delay while the code tracking loop pulls in. The second part is the delay while the AME tap weight calculations are performed by the AMF weight gen 1722 to produce settled weighting coefficients. Also in the second part of the pre-track period, the carrier tracking loop is allowed to pull in by the SW PLL 1724, and the scalar quantile estimates are performed in the quantile estimator 1723A.

[0282] The tracking process is entered after the pre-track period ends. This process is actually a repetitive cycle and is the only process phase during which receive data provided by the modem may be considered valid. The following operations are performed during this phase: AMF tap weight update, carrier tracking, code tracking, vector quantile update, scalar quantile update, code lock check, derotation and symbol summing and power control (forward and reverse)

[0283] If LOL is detected, the modem receiver terminates the track algorithm and automatically enters the reacquisition algorithm. In the SU, a LOL causes the transmitter to be shut down. In the RCS, LOL causes forward power control to be disabled with the transmit power held constant at the level immediately prior to loss of lock. It also causes the return power control information being transmitted to assume a 010101 . . . pattern, causing the SU to hold its transmit power constant. This can be performed using the signal lock check function which generates the reset signal to the acquisition and tracking circuit 1701.

[0284] Two sets of quantile statistics are maintained, one by quantile estimator 1723B and the other by the scalar quantile estimator 1723A. Both are used by the modem controller 1303. The first set is the “vector” quantile information, so named because it is calculated from the vector of four complex values generated by the AUX AVC receiver 1712. The second set is the scalar quantile information, which is calculated from the single complex value AUX signal that is output from the AUX despreader 1707. The two sets of information represent different sets of noise statistics used to maintain a pre-determined probability of false alarm (P_fa). The vector quantile data is used by the acquisition and reacquisition algorithms implemented by the modem controller 1303 to determine the presence of a received signal in noise, and the scalar quantile information is used by the code lock check algorithm.

[0285] For both the vector and scalar cases, quantile information consists of calculated values of lambda0 through lambda2, which are boundary values used to estimate the probability distribution function (p.d.f.) of the despread receive signal and determine whether the modem is locked to the PN code. The aux_power value used in the following C-subroutine is the magnitude squared of the AUX signal output of the scalar correlator array for the scalar quantiles, and the sum of the magnitudes squared for the vector case. In both cases the quantiles are then calculated using the following C-subroutine:

[0286]

	for (n = 0; n < 3; n++) {
	lambda [n] += (lambda [n] < Aux_Power) ? CG[n] : GM[n];
	}

where CG[n] are positive constants and GM[n] are negative constants, (different values are used for scalar and vector quantiles).

[0287] During the acquisition phase, the search of the incoming pilot signal with the locally generated pilot code sequence employs a series of sequential tests to determine if the locally generated pilot code has the correct code phase relative to the received signal. The search algorithms use the sequential probability ratio test (SPRT) to determine whether the received and locally generated code sequences are in phase. The speed of acquisition is increased by parallelism resulting from having a multi-fingered receiver. For example, in the described embodiment of the invention the main pilot rake 1711 has a total of 11 fingers representing a total phase period of 11 chip periods. For acquisition 8 separate SPRTs are implemented, with each SPRT observing a 4 chip window. Each window is offset from the previous window by one chip, and in a search sequence any given code phase is covered by 4 windows. If all 8 of the SPRT tests are rejected, then the set of windows is moved by 8 chips. If any of the SPRT's is accepted, then the code phase of the locally generated pilot code sequence is adjusted to attempt to center the accepted SPRT's phase within the pilot AVC. It is likely that more than one SPRT reaches the acceptance threshold at the same time. A table lookup is used cover all 256 possible combinations of accept/reject and the modem controller uses the information to estimate the correct center code phase within the pilot rake 1711. Each SPRT is implemented as follows (all operations occur at 64 k symbol rate): Denote the fingers' output level values as I_Finger[n] and Q_Finger[n], where n=0 . . . 10 (inclusive, 0 is earliest (most advanced) finger), then the power of each window is: $\mathrm{Power}\mathrm{Window}\left[i\right]\sum _{n=0}^{10}\left(I{\mathrm{\_Finger}}^2\left[n\right]+Q{\mathrm{\_Finger}}^2\left[n\right]\right)$
To implement the SPRT's the modem controller then performs for each of the windows the following calculations which are expressed as a pseudo-code subroutine:

[0288]

	/* find bin for Power */
	tmp = SIGMA[0];
	for (k = ; k< 3; k++) {
	if (Power > lambda [k]) tmp = SIGMA[k+1];
	}
	test_statistic += tmp; /* update statistic */
	if(test_statistic > ACCEPTANCE_THRESHOLD)you've got ACQ;
	else if (test_statistic < DISMISSAL_THRESHOLD) {
	forget this code phase;
	} else keep trying - get more statistics;

where lambda[k] are as defined in the above section on quantile estimation, and SIGMA[k], ACCEPTANCE_THRESHOLD and DISMISSAL_THRESHOLD are predetermined constants. Note that SIGMA[k] is negative for values for low values of k, and positive for right values of k, such that the acceptance and dismissal thresholds can be constants rather than a function of how many symbols worth of data have been accumulated in the statistic.
where f(t)=q(t) *h_R(t) and z(t)=n(t)*h_R(t).

[0289] In the exemplary receiver, samples of the received signal are taken at the chip rate, that is to say, 1/T_c. These samples, x(mT_c+τ′), are processed by an array of correlators that compute, during the r^th correlation period, the quantities given by Equation (33): $\begin{array}{cc}{v}_k^{\left(r\right)}=\sum _{m=rL}^{rL+L-1}x\left(m{T}_c+{\tau }^{\prime }\right)C_{m+k}^{*}& \text{Equation (33)}\end{array}$
These quantities are composed of a noise component w_k^(r) and a deterministic component y_k^(r) given by Equation (34):
y_k^(r)=E[v_k^(r)]=Lf(kT_c+τ′−τ)  Equation (34)
In the sequel, the time index r may be suppressed for ease of writing, although it is to be noted that the function f(t) changes slowly with time.

[0290] The samples are processed to adjust the sampling phase, τ′, in an optimum fashion for further processing by the receiver, such as matched filtering. This adjustment is described below. To simplify the representation of the process, it is helpful to describe it in terms of the function f(t+τ), where the time-shift, τ, is to be adjusted. It is noted that the function f(t+τ) is measured in the presence of noise. Thus, it may be problematical to adjust the phase τ′ based on measurements of the signal f(t+τ). To account for the noise, the function v(τ): v(t)=f(t)+m(t) is introduced, where the term m(t) represents a noise process. The system processor may be derived based on considerations of the function v(t).

[0291] The process is non-coherent and therefore is based on the envelope power function |v(t+τ)|². The functional e(τ′) given in Equation (35) is helpful for describing the process:

[0292] The modem controller determines which bin delimited by the values of lambda[k] the power level falls into which allows the modem controller to develop an approximate statistic.

[0293] For the present algorithm, the control voltage is formed as ε=y^TBy, where y is a vector formed from the complex valued output values of the pilot vector correlator 1711, and B is a matrix consisting of the constant values pre-determined to maximize the operating characteristics while minimizing the noise as described previously with reference to the quadratic detector.

[0294] To understand the operation of the quadratic detector, it is useful to consider the following. A spread spectrum signal, s(t) is passed through a multipath channel with an impulse response h_c(t). The baseband spread signal is described by Equation (30): $\begin{array}{cc}s\left(t\right)=\sum _i{C}_{i}p\left(t-i{T}_c\right)& \text{Equation (30)}\end{array}$
where C_i is a complex spreading code symbol, p(t) is a predefined chip pulse and T_c is the chip time spacing, where T_c=1/R_c and R_c is the chip rate.

[0295] The received baseband signal is represented by Equation (31): $\begin{array}{cc}r\left(t\right)=\sum _i{C}_{i}q\left(t-i{T}_c-\tau \right)+n\left(t\right)& \text{Equation (31)}\end{array}$
where q(t)=p(t)*h_c(t), t is an unknown delay and n(t) is additive noise. The received signal is processed by a filter, h_R(t), so the waveform, x(t), to be processed is given by Equation (32): $\begin{array}{cc}x\left(t\right)=\sum _i{C}_{i}f\left(t-i{T}_c-\tau \right)+z\left(t\right)& \text{Equation (32)}\end{array}$ $\begin{array}{cc}\begin{array}{c}e\left({\tau }^{\prime }\right)={\int }_{-\infty }^0{v\left(t+{\tau }^{\prime }-\tau \right)}^{2}dt-\\ {\int }_0^{\infty }{v\left(t+{\tau }^{\prime }-\tau \right)}^{2}dt\end{array}& \mathrm{Equation}\left(35\right)\end{array}$
The shift parameter is adjusted for e(τ′)=0, which occurs when the energy on the interval (−∞, τ′−τ] equals that on the interval [τ′−τ, ∞). The error characteristic is monotonic and therefore has a single zero crossing point. This is the desirable quality of the functional. A disadvantage of the functional is that it is ill-defined because the integrals are unbounded when noise is present. Nevertheless, the functional e(τ′) may be cast in the form given by Equation (36): $\begin{array}{cc}e\left({\tau }^{\prime }\right)={\int }_{-\infty }^{\infty }w\left(t\right){v\left(t+{\tau }^{\prime }-\tau \right)}^{2}dt& \mathrm{Equation}\left(36\right)\end{array}$
where the characteristic function w(t) is equal to sgn(t), the signum function.

[0296] To optimize the characteristic function w(t), it is helpful to define a figure of merit, F, as set forth in Equation (37): $\begin{array}{cc}F=\frac{{\left[\stackrel{\_}{e\left({\tau }_0^{\prime }+T_A\right)-e\left({\tau }_0^{\prime }-T_A\right)}\right]}^2}{\mathrm{VAR}\left\{e\left({\tau }_0^{\prime }\right)\right\}}& \text{Equation (37)}\end{array}$
The numerator of F is the numerical slope of the mean error characteristic on the interval [−T_A, T_A] surrounding the tracked value, τ₀′. The statistical mean is taken with respect to the noise as well as the random channel, h_c(t). It is desirable to specify a statistical characteristic of the channel in order to perform this statistical average. For example, the channel may be modeled as a wide sense stationary uncorrelated scattering (WSSUS) channel with impulse response h_c(t) and a white noise process U(t) that has an intensity function g(t) as shown in Equation (38):
h_c(t)=√{square root over (g(t)U(t))}{square root over (g(t)U(t))}  Equation (38)
The variance of e(τ) is computed as the mean square value of the fluctuation: $\begin{array}{cc}e\left({\tau }^{\prime }\right)=e\left(\tau \right)-\langle e\left(\tau \right)\rangle & \mathrm{Equation}\left(39\right)\end{array}$
where <e(τ)> is the average of e(τ) with respect to the noise.

[0297] Optimization of the figure of merit F with respect to the function w(t) may be carried out using well-known variational methods of optimization. Once the optimal w(t) is determined, the resulting processor may be approximated accurately by a quadratic sample processor which is derived as follows. By the sampling theorem, the signal v(t), bandlimited to a bandwidth W may be expressed in terms of its samples as shown in Equation (40):
v(t)=Σv(k/W)sinc[(Wt−k)π]  Equation (40)
substituting this expansion into Equation 36 results in an infinite quadratic form in the samples v(k/W+τ′−τ). Making the assumption that the signal bandwidth equals the chip rate allows the use of a sampling scheme that is clocked by the chip clock signal to be used to obtain the samples. These samples, v_k are represented by Equation (41):
v_k=v(kT_c+τ′−τ)  Equation (41)
This assumption leads to a simplification of the implementation. It is valid if the aliasing error is small.

[0298] In practice, the quadratic form that is derived is truncated. An example normalized B matrix is given below in Table 12. For this example, an exponential delay spread profile g(t)=exp(−t/τ) is assumed with τ equal to one chip. An aperture parameter T_A equal to one and one-half chips has also been assumed. The underlying chip pulse has a raised cosine spectrum with a 20% excess bandwidth.

[0299]

TABLE 12
Example B Matrix
0	0	0	0	0	0	0	0	0	0	0
0	0	−0.1	0	0	0	0	0	0	0	0
0	−0.1	0.22	0.19	−0.19	0	0	0	0	0	0
0	0	0.19	1	0.45	−0.2	0	0	0	0	0
0	0	−0.19	0.45	0.99	0.23	0	0	0	0	0
0	0	0	−0.2	0.23	0	−0.18	0.17	0	0	0
0	0	0	0	0	−0.18	−0.87	−0.42	0.18	0	0
0	0	0	0	0	0.17	−0.42	−0.92	−0.16	0	0
0	0	0	0	0	0	0.18	−0.16	−0.31	0	0
0	0	0	0	0	0	0	0	0	−0.13	0
0	0	0	0	0	0	0	0	0	0	0

Code tracking is implemented via a loop phase detector that is implemented as follows. The vector y is defined as a column vector which represents the 11 complex output level values of the pilot AVC 1711, and B denotes an 11×11 symmetric real valued coefficient matrix with pre-determined values to optimize performance with the non-coherent pilot AVC output values y. The output signal e of the phase detector is given by Equation (42):
e=y^TBy  Equation (42)
The following calculations are then performed to implement a proportional plus integral loop filter and the VCO:

• [0300] x[n]=x[n−1]+be
• [0301] z[n]=z[n−1]+x[n]+ae
  for b and a which are constants chosen from modeling the system to optimize system performance for the particular transmission channel and application, and where x[n] is the loop filter's integrator output value and z[n] is the VCO output value. The code phase adjustments are made by the modem controller the following C-subroutine:
• [0302] if(z>zmx) {
• [0303] delay phase 1/16 chip;
• [0304] z−=zmax;
• [0305] } else if (z<−zmax) {
• [0306] advance phase 1/16 chip;
• [0307] z+=zmax;
• [0308] }

[0309] A different delay phase could be used in the above pseudo-code consistant with the present invention.

[0310] The AMF tap-weight update algorithm of the AMF weight gen 1722 occurs periodically to de-rotate and scale the phase of each finger value of the pilot rake 1711 by performing a complex multiplication of the pilot AVC finger value with the complex conjugate of the current output value of the carrier tracking loop and applying the product to a low pass filter and form the complex conjugate of the filter values to produce AMF tap-weight values, which are periodically written into the AMF filters of the CDMA modem.

[0311] The lock check algorithm, shown in FIG. 17, is implemented by the modem controller 1303 performing SPRT operations on the output signal of the scalar correlator array. The SPRT technique is the same as that for the acquisition algorithms, except that the acceptance and rejection thresholds are changed to increase the probability of detection of lock.

[0312] Carrier tracking is accomplished via a second order loop that operates on the pilot output values of the scalar correlated array. The phase detector output is the hard limited version of the quadrature component of the product of the (complex valued) pilot output signal of the scalar correlated array and the VCO output signal. The loop filter is a proportional plus integral design. The VCO is a pure summation, accumulated phase error φ, which is converted to the complex phaser cos φ+j sin φ using a look-up table in memory.

[0313] The previous description of acquisition and tracking algorithm focuses on a non-coherent method because the acquisition and tracking algorithm described requires non-coherent acquisition following by non-coherent tracking because during acquisition a coherent reference is not available until the AMF, pilot AVC, aux AVC, and DPLL are in an equilibrium state. However, it is known in the art that coherent tracking and combining is always optimal because in non-coherent tracking and combining the output phase information of each pilot AVC finger is lost. Consequently, another embodiment of the invention employs a two step acquisition and tracking system, in which the previously described non-coherent acquisition and tracking algorithm is implemented first, and then the algorithm switches to a coherent tracking method. The coherent combining and tracking method is similar to that described previously, except that the error signal tracked is of the form:
ε=y^TAy  Equation (43)
where y is defined as a column vector which represents the 11 complex output level values of the pilot AVC 1711, and A denotes an 11×11 symmetric real valued coefficient matrix with pre-determined values to optimize performance with the coherent pilot AVC outputs y. An exemplary A matrix is shown below. $\begin{array}{cc}A=\begin{array}{ccccccccccc}1& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0\\ 0& 1& 0& 0& 0& 0& 0& 0& 0& 0& 0\\ 0& 0& 1& 0& 0& 0& 0& 0& 0& 0& 0\\ 0& 0& 0& 1& 0& 0& 0& 0& 0& 0& 0\\ 0& 0& 0& 0& 1& 0& 0& 0& 0& 0& 0\\ 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0\\ 0& 0& 0& 0& 0& 0& -1& 0& 0& 0& 0\\ 0& 0& 0& 0& 0& 0& 0& -1& 0& 0& 0\\ 0& 0& 0& 0& 0& 0& 0& 0& -1& 0& 0\\ 0& 0& 0& 0& 0& 0& 0& 0& 0& -1& 0\\ 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& -1\end{array}& \text{Equation (44)}\end{array}$

[0314] Referring to FIG. 9, the video distribution controller board (VDC) 940 of the RCS is connected to each MIU 931, 932, 933 and the RF transmitter/receivers 950. The VDC 940 is shown in FIG. 21. The data combiner circuitry (DCC) 2150 includes a data demultiplexer 2101, data summer 2102, FIR filters 2103, 2104 and a driver 2111. The DCC 2150 1) receives the weighted CDMA modem I and Q data signal MDAT from each of the MIUs 931, 932, 933, 2) sums the I and Q data with the digital bearer channel data from each MIU 931, 932, 933, 3) and sums the result with the broadcast data message signal BCAST and the global pilot spreading code GPILOT provided by the master MIU modem 1210, 4) band shapes the summed signals for transmission, and 5) produces analog data signal for transmission to the RF transmitter/receiver.

[0315] FIR filters 2103, 2104 are used to modify the MIU CDMA transmit I and Q modem data before transmission. The WAC transfers FIR filter coefficient data through the serial port link 912 through the VDC controller 2120 and to the FIR filters 2103, 2104. Each FIR filter 2103, 2104 is configured separately. The FIR Filters 2103, 2104 employ upsampling to operate at twice the chip rate so zero data values are sent after every MIU CDMA transmit modem DATI and DATQ value to produce FTXI and FTXQ.

[0316] The VDC 940 distributes the AGC signal AGCDATA from the AGC 1750 of the MIUs 931, 932, 933 to the RF transmitter/receiver 950 through the distribution interface (DI) 2110. The VDC DI 2110 receives data RXI and RXQ from the RF transmitter/receiver and distributes the signal as VDATAI and VDATAQ to MIUs 931, 932, 933.

[0317] Referring to FIG. 21, the VDC 940 also includes a VDC controller 2120 which monitors status and fault information signals MIUSTAT from MIUs and connects to the serial link 912 and HSBS 970 to communicate with WAC 920 shown in FIG. 9. The VDC controller 2120 includes a microprocessor, such as an Intel 8032 microcontroller, an oscillator (not shown) providing timing signals, and memory (not shown). The VDC controller memory includes a flash PROM (not shown) to contain the controller program code for the 8032 microprocessor, and an SRAM (not shown) to contain the temporary data written to and read from memory by the microprocessor.

[0318] Referring to FIG. 9, the present invention includes a RF transmitter/receiver 950 and power amplifier section 960. Referring to FIG. 22, the RF transmitter/receiver 950 is divided into three sections: the transmitter module 2201, the receiver module 2202, and the frequency synthesizer 2203. Frequency synthesizer 2203 produces a transmit carrier frequency TFREQ and a receive carrier frequency RFREQ in response to a frequency control signal FREQCTRL received from the WAC 920 on the serial link 912. In the transmitter module 2201, the input analog I and Q data signals TXI and TXQ from the VDC are applied to the quadrature modulator 2220, which also receives a transmit carrier frequency signal TFREQ from the frequency synthesizer 2203 to produce a quadrature modulated transmit carrier signal TX. The analog transmit carrier modulated signal, an upconverted RF signal, TX is then applied to the transmit power amplifier 2252 of the power amplifier 960. The amplified transmit carrier signal is then passed through the high power passive components (HPPC) 2253 to the Antenna 2250, which transmits the upconverted RF signal to the communication channel as a CDMA RF signal. In one embodiment of the invention, the transmit power amplifier 2252 comprises eight amplifiers of approximately 60 watts peak-to-peak each.

[0319] The HPPC 2253 comprises a lightning protector, an output filter, a 10 dB directional coupler, an isolator, and a high power termination attached to the isolator.

[0320] A receive CDMA RF signal is received at the antenna 2250 from the RF channel and passed through the HPPC 2253 to the receive power amplifier 2251. The receive power amplifier 2251 includes, for example, a 30 watt power transistor driven by a 5 watt transistor. The RF receive module 2202 has quadrature modulated receive carrier signal RX from the receive power amplifier. The receive module 2202 includes a quadrature demodulator 2210 which takes the receive carrier modulated signal RX and the receive carrier frequency signal RFREQ from the frequency synthesizer 2203, synchronously demodulates the carrier and provides analog I and Q channels. These channels are filtered to produce the signals RXI and RXQ, which are transferred to the VDC 940.

[0321] FIG. 23 shows the subscriber unit (SU) of one embodiment of the present invention. As shown, the SU includes an RF section 2301 including a RF modulator 2302, RF demodulator 2303 and splitter/isolator 2304 which receive global and assigned logical channels including traffic and control messages and global pilot signals in the forward link CDMA RF channel signal, and transmit assigned channels and reverse pilot signals in the reverse link CDMA RF channel. The forward and reverse links are received and transmitted respectively through antenna 2305. The RF section employs, in one exemplary embodiment, a conventional dual conversion superheterodyne receiver having a synchronous demodulator responsive to the signal ROSC. Selectivity of such a receiver is provided by a 70 MHz transversal SAW filter (not shown). The RF modulator includes a synchronous modulator (not shown) responsive to the carrier signal TOSC to produce a quadrature modulated carrier signal. This signal is stepped up in frequency by an offset mixing circuit (not shown).

[0322] The SU further includes a subscriber line interface 2310, including the functionality of a control (CC) generator, a data interface 2320, an ADPCM encoder 2321, an ADPCM decoder 2322, an SU controller 2330, an SU clock signal generator 2331, memory 2332 and a CDMA modem 2340, which is essentially the same as the CDMA modem 1210 described above with reference to FIG. 13. It is noted that data interface 2320, ADPCM encoder 2321 and ADPCM decoder 2322 are typically provided as a standard ADPCM encoder/decoder chip.

[0323] The forward link CDMA RF channel signal is applied to the RF demodulator 2303 to produce the forward link CDMA signal. The forward link CDMA signal is provided to the CDMA modem 2340, which acquires synchronization with the global pilot signal, produces global pilot synchronization signal to the clock 2331, to generate the system timing signals, and despreads the plurality of logical channels. The CDMA modem 2340 also acquires the traffic messages RMESS and control messages RCTRL and provides the traffic message signals RMESS to the data interface 2320 and receive control message signals RCTRL to the SU controller 2330.

[0324] The receive control message signals RCTRL include a subscriber identification signal, a coding signal and bearer modification signals. The RCTRL may also include control and other telecommunication signaling information. The receive control message signal RCTRL is applied to the SU controller 2330, which verifies that the call is for the SU from the subscriber identification value derived from RCTRL. The SU controller 2330 determines the type of user information contained in the traffic message signal from the coding signal and bearer rate modification signal. If the coding signal indicates the traffic message is ADPCM coded, the traffic message RVMESS is sent to the ADPCM decoder 2322 by sending a select message to the data interface 2320. The SU controller 2330 outputs an ADPCM coding signal and bearer rate signal derived from the coding signal to the ADPCM decoder 2322. The traffic message signal RVMESS is the input signal to the ADPCM decoder 2322, where the traffic message signal is converted to a digital information signal RINF in response to the values of the input ADPCM coding signal.

[0325] If the SU controller 2330 determines the type of user information contained in the traffic message signal from the coding signal is not ADPCM coded, then RDMESS passes through the ADPCM encoder transparently. The traffic message RDMESS is transferred from the data interface 2320 directly to the interface controller (IC) 2312 of the subscriber line interface 2310.

[0326] The digital information signal RINF or RDMESS is applied to the subscriber line interface 2310, including a interface controller (IC) 2312 and line interface (LI) 2313. For the exemplary embodiment the IC is an extended PCM interface controller (EPIC) and the LI is a subscriber line interface circuit (SLIC) for POTS which corresponds to RINF type signals and a ISDN Interface for ISDN which corresponds to RDMESS type signals. The EPIC and SLIC circuits are well known in the art. The subscriber line interface 2310 converts the digital information signal RINF or RDMESS to the user defined format. The user defined format is provided to the IC 2312 from the SU Controller 2330. The LI 2310 includes circuits for performing such functions as A-law or μ-law conversion, generating dial tone and generating or interpreting signaling bits. The line interface also produces the user information signal to the SU user 2350 as defined by the subscriber line interface, for example POTS voice, voiceband data or ISDN data service.