US 6,940,729 B2Grant
Integrated circuit stacking system and method
Issue Date:2005-09-06
•3 Claims
•17 Drawing Sheets
Abstract
The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The invention provides techniques and structures for aggregating chip scale-packaged integrated circuits (CSPs) or leaded packages with other CSPs or with monolithic or stacked leaded packages into modules that conserve PWB or other board surface area. The present invention can be used to advantage with CSP or leaded packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element IC and a support element IC are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two IC elements. A portion of the flex circuit connected to the support element is folded over the base element to dispose the support element above the base element while reducing the overall footprint occupied by the two ICs. The flex circuit connects the ICs and provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations in modules provided for high-density memories, high capacity computing, or applications where small size is valued.
Metadata
Assignee
- Staktek Group L.P.
Inventors
- James W. Cady
- James Wilder
- David L. Roper
- Russell Rapport
- James Douglas Wehrly, Jr.
- Jeffrey Alan Buchle
Application Information
Application Number:US 10/136,890
Filing Date:2002-05-02
Priority Date:2001-10-26
Art Unit:2827
Patent Drawings (17 sheets)
Description
Related Applications
[0001] This application is a continuation-in-part of U.S. application Ser. No. 10/005,581, filed Oct. 26, 2001, pending, which is hereby incorporated by reference for all purposes.
Technical Field
[0002] The present invention relates to aggregating integrated circuits and, in particular, to stacking dissimilar integrated circuits.
Background of the Invention
[0003] A variety of techniques are used to stack packaged integrated circuits. Some methods require special packages, while other techniques stack conventional packages. In some stacks, the leads of the packaged integrated circuits are used to create a stack, while in other systems, added structures such as rails provide all or part of the interconnection between packages. In still other techniques, flexible conductors with certain characteristics are used to selectively interconnect packaged integrated circuits.
[0004] One major package configuration employed during the past decade has encapsulated an integrated circuit (IC) in a plastic surround typically having a rectangular configuration. The enveloped integrated circuit is connected to the application environment through leads emergent from the edge periphery of the plastic encapsulation. Such “leaded packages” have been the constituent elements most commonly employed by techniques for stacking packaged integrated circuits.
[0005] Leaded packages play an important role in electronics, but efforts to miniaturize electronic components and assemblies have driven development of technologies that preserve circuit board surface area. Because leaded packages have leads emergent from peripheral sides of the package, leaded packages occupy more than a minimal amount of circuit board surface area. Consequently, alternatives to leaded packages have recently gained market share.
[0006] One family of alternative packages is identified generally by the term “chip scale packaging” or CSP. These differ from leaded packages in that the CSP packages provide connection to an integrated circuit through a set of contacts (often embodied as “bumps,” “spheres,” or “balls”) arrayed across a major surface of the package. Instead of leads emergent from a peripheral side of the package, contacts are placed on a major surface and typically emerge from the planar bottom surface of the package.
[0007] The goal of CSP is to occupy as little area as possible and, preferably, approximately the area of the encapsulated IC. Therefore, CSP contacts do not typically extend beyond the outline perimeter of the package. The absence of “leads” on package sides renders most stacking techniques devised for leaded packages inapplicable for CSP stacking.
[0008] CSP has enabled reductions in size and weight parameters for many applications. CSP is a broad category that can include a variety of packages from larger than chip scale to die-sized packages such as the die-sized ball grid array (DSBGA) described in proposed JEDEC standard 95-1 for DSBGA.
[0009] To meet the continuing demands for cost and form factor reduction with increasing memory capacities, CSP technologies that aggregate integrated circuits in CSP technology have recently been developed. For example, Sharp, Hitachi, Mitsubishi and Intel recently undertook support of what are called the S-CSP specifications for flash and SRAM applications. Those S-CSP specifications describe, however, stacking multiple die within a single chip scale package and do not provide a technology for stacking chip scale packages. Stacking integrated circuits within a single package requires specialized technology that includes reformulation of package internals and significant expense with possible supply chain vulnerabilities.
[0010] There are several known techniques for stacking packages articulated in chip scale technology. The assignee of the present invention has developed previous systems for aggregating FBGA packages in space saving topologies. The assignee of the present invention has systems for stacking BGA packages on a DIMM in a RAMBUS environment.
[0011] In U.S. Pat. No. 6,205,654 B1, owned by the assignee of the present invention, a system for stacking ball grid array packages that employs lead carriers to extend connectable points out from the packages is described. Other known techniques add structures to a stack of BGA-packaged ICs. Still others aggregate CSPs on a DIMM with angular placement of the packages. Such techniques provide alternatives, but require topologies of added cost and complexity.
[0012] U.S. Pat. No. 6,262,895 B1 to Forthun (the “Forthun patent”) purports to disclose a technique for stacking chip scale packaged ICs. The Forthun patent discloses a “package” that exhibits a flex circuit wrapped partially about a CSP. The flex circuit is said to have pad arrays on upper and lower surfaces of the flex.
[0013] The flex circuit of the Forthun “package” has a pad array on its upper surface and a pad array centrally located upon its lower surface. On the lower surface of the flex there are third and fourth arrays on opposite sides from the central lower surface pad array. To create the package of Forthun, a CSP contacts the pad array located on the upper surface of the flex circuit. As described in the Forthun patent, the contacts on the lower surface of the CSP are pushed through “slits” in the upper surface pads and advanced through the flex to protrude from the pads of the lower surface array and, therefore, the bottom surface of the package. Thus, the contacts of the CSP serve as the contacts for the package. The sides of the flex are partially wrapped about the CSP to adjacently place the third and fourth pad arrays above the upper major surface of the CSP to create from the combination of the third and fourth pad arrays, a fifth pad array for connection to another such package. Thus, as described in the Forthun disclosure, a stacked module of CSPs created with the described packages will exhibit a flex circuit wrapped about each CSP in the module.
[0014] Most previous known methods for stacking aggregate similarly packaged integrated circuits. What is needed are methods and structures for stacking dissimilar packages and circuits in thermally efficient, reliable structures.
Summary of the Invention
[0015] The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The invention provides techniques and structures for aggregating chip scale-packaged integrated circuits (CSPs) or leaded packages with other CSPs or with monolithic or stacked leaded packages into modules that conserve PWB or other board surface area. The present invention can be used to advantage with CSP or leaded packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. Although the present invention is applied most frequently to packages that contain one die, it may be employed with packages that include more than one integrated circuit die.
[0016] In a preferred embodiment devised in accordance with the present invention, a base element IC and a support element IC are aggregated through a flex circuit having two conductive layers that are patterned to selectively connect the two IC elements. Simpler embodiments may use a one conductive layer flex. A portion of the flex circuit connected to the support element is folded over the base element to dispose the support element above the base element while reducing the overall footprint occupied by the two ICs. The flex circuit connects the ICs and provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB).
[0017] The present invention may be employed to advantage in numerous configurations and combinations in modules provided for high-density memories, high capacity computing, or particular applications where small size is valued.
Summary of the Drawings
[0018] FIG. 1 is an elevation view of module 10 devised in accordance with a preferred embodiment of the present invention.
[0019] FIG. 2 is an elevation view of module 10 devised in accordance with an alternative preferred embodiment of the present invention.
[0020] FIG. 3 is an elevation view of module 10 devised in accordance with an alternative preferred embodiment of the present invention.
[0021] FIG. 4 is an elevation view of module 10 devised in accordance with an alternative preferred embodiment of the present invention.
[0022] FIG. 5 is an elevation view of module 10 devised in accordance with an alternative preferred embodiment of the present invention.
[0023] FIG. 6 is an elevation view of module 10 devised in accordance with an alternative preferred embodiment of the present invention.
[0024] FIG. 7 is still another view of an alternative embodiment devised in accordance with the invention.
[0025] FIG. 8 depicts, in enlarged view, the area marked “A” in FIG. 1.
[0026] FIG. 9 is an enlarged detail of an exemplar connection in a preferred embodiment of the present invention.
[0027] FIG. 10 is an elevation view of a preferred embodiment devised in accordance with the present invention.
[0028] FIG. 11 is an enlarged depiction of a part of the view of FIG. 10.
[0029] FIG. 12 depicts, in enlarged view, the area marked “B” in FIG. 11.
[0030] FIG. 13 depicts in enlarged view, an alternative connection strategy between constituent elements of the module and a flex in a preferred embodiment in accordance with the present invention.xxx
[0031] FIG. 14 is an enlarged depiction of an exemplar area around a base flex contact in a preferred embodiment of the present invention.
[0032] FIG. 15 depicts an exemplar first conductive layer of a flex employed in a preferred embodiment of the invention.
[0033] FIG. 16 depicts an exemplar second conductive layer of a flex employed in a preferred embodiment of the invention.
Description of Preferred Embodiments
[0034] FIG. 1 is an elevation view of module 10 devised in accordance with a preferred embodiment of the present invention. FIG. 1 depicts a three-element preferred embodiment of the invention. The invention may, however, be employed with greater or fewer than three IC elements. Module 10 is comprised of a base element 12 and support elements 14 and 16. In the depicted embodiment, base element 12 and support elements 14 and 16 are shown as CSP devices, but the invention is not limited to arrangements of CSPs and may be employed to aggregate a variety of package types. Base element 12 and support elements 14 and 16 each have, in the depicted embodiment, upper surfaces 18 and lower surfaces 20 and peripheral or lateral sides 22. Lateral sides 22 may be in the character of sides or may, if the CSP is especially thin, be in the character of an edge. For example, in addition to the well known leaded and CSP packages, the present invention may be employed with packaged ICs that do not exhibit what would be considered a lateral side 22 such as, for example, die that are packaged to have edge-wise protective layers or coatings and a connective structure across the bottom surface of the die while leaving uncovered the upper surface of the die. Such packages are employed in DRAM circuitry and may be aggregated using the present invention.
[0035] The invention is employed to advantage with a variety of combinations of packages including leaded and CSP and other configurations of packaged ICs. CSPs of a variety of types and configurations such as, for example, those that are larger than die-sized, as well those that are at or near die size as well as the variety of ball grid array packages known in the art may be employed to advantage by the invention. Collectively, these will be known herein as chip scale packaged integrated circuits (CSPs) and some preferred embodiments will be described in terms of CSPs, but the particular configurations used in the explanatory figures are not, however, to be construed as limiting. For example, the elevation view of FIG. 1 is depicted with CSPs of a particular profile, but it should be understood that the figures are exemplary only. Later figures show embodiments of the invention that employ CSPs of other configurations aggregated with leaded packages as an example of some of the many alternative IC package configurations and combinations with which the invention may be employed. The system of the invention may also be employed with leaded packages while the module itself presents an array of bumps or balls to the application environment.
[0036] The invention may be employed to advantage with many of the wide range of CSP and leaded package configurations available in the art. One preferred embodiment of the invention employs a CSP microprocessor as base element 12 and memory circuits packaged in a variety of configurations as support elements 14 and 16, but those of skill in the art will recognize that the invention may be employed to advantage with logic and computing circuits where reduction of PWB or other board surface area consumption is desired.
[0037] Typical CSPs, such as, for example, ball-grid-array (“BGA”), micro-ball-grid array (“μBGA”), and fine-pitch ball grid array (“FBGA”) packages have an array of connective contacts embodied, for example, as bumps, solder balls, or balls that extend from lower surface 20 of a plastic casing in any of several patterns and pitches. An external portion of the connective contacts is often finished with a ball of solder. Shown in FIG. 1 are CSP contacts 26 along lower surfaces 20 of elements 12, 14, and 16. Contact with the integrated circuit within the respective packages is provided by CSP contacts 26.
[0038] FIG. 1 depicts base element 12 and support elements 14 and 16 in a stacked disposition with upper major surfaces of the constituent elements being proximally located in this back to back configuration. Between upper sides 18 of support elements 14 and 16 and upper side 18 of base element 12 is shown adhesive layer 24 shown in exaggerated scale for clarity of depiction. CSP contacts 26 are emergent from lower side 20 of base element 12 and support elements 14 and 16. Module contacts 28 are shown depicted along the bottom of module 10 and provide connection for the module to a PWB or PCB or other mounting site.
[0039] In FIG. 1 , flex circuit (“flex”, “flex circuit”, “flexible circuit structure”) 30 is shown partially wrapped about base element 12 and support elements 14 and 16. Any flexible or conformable substrate with a multiple internal layer connectivity capability may be used as a flex circuit in the invention. Some embodiments may employ more than one flex. The entire flex circuit may be flexible or, as those of skill in the art will recognize, a PCB structure made flexible in certain areas to allow conformability in some areas and rigid in other areas for planarity along contact surfaces may be employed as an alternative flex circuit in the present invention. For example, structures known as rigid-flex may be employed.
[0040] Support elements 14 and 16 are preferably fixed to upper surface 18 of base element 12 by adhesive 24 which is shown as a tape adhesive, but may be a liquid adhesive or may be placed in discrete locations across the package. Preferably, adhesive 24 is thermally conductive. Adhesives that include a flux may be used to advantage in assembly of module 10. Layer 24 may also be a thermally conductive medium to encourage heat flow between the elements of module 10. Alternatively, a mechanical clamp or clamps may be used to hold the base and support elements together. Differing embodiments of the invention will place one or more support elements in a stacked disposition relative to a base element. The contacts for the module itself may be closer to either the base element or the support element(s) of the module although more typically and preferably, the module contacts will be closer to the base element. The support elements may also extend over the edges of the base element or may be disposed within the perimeter of the base element.
[0041] Flex circuit 30 is, in a preferred embodiment, a multi-layer flexible circuit structure that has at least two conductive layers. Other embodiments may employ, if the circuit is simple enough, a flex with one conductive layer. Preferably, the conductive layers are copper. The use of plural conductive layers provides connection advantages that simplify the interconnection schemes used to interconnect elements 12, 14 and 16. Multiple conductive layers also provide the opportunity, when there is sufficient routing area available, to manage capacitance and inductance issues better than a single conductive layer.
[0042] FIG. 2 shows a module 10 devised in accordance with an alternative preferred embodiment of the invention. FIG. 2 illustrates the aggregation of a leaded package device having leads 31 (i.e., as support element 16 in this embodiment) with base element 12 and support element 14. FIG. 2 further depicts the placement of flex 30 attached to the upper side of base element 12 with the placement of support elements 14 and 16 in a position relatively above flex 30 rather than below as earlier shown in FIG. 1. Flex 30 is preferably attached to upper side 18 of base element 12 with a thermally conductive adhesive depicted by reference 25 in FIG. 2. A conformal media 32 is indicated in FIG. 2 as being placed between CSP contacts 26 to assist in creating conformality of structural areas of module 10. Preferably, conformal media 32 is thermally conductive and is placed along the lower surface 20 of base element 12 although to preserve clarity of the view, its placement between only a few CSP contacts 26 of base element 12 is shown in the FIG. 2.
[0043] FIG. 3 depicts another alternative embodiment of the present invention. Shown are base element 12 and support element 14. In the place of previously shown single package support element 16 is leaded stack 17, consisting of upper IC 19 and lower IC 21. In this embodiment, stack 17 is configured in conformity with a product of the assignee of the present invention but is intended to be an exemplar and not a limiting configuration. FIG. 4 illustrates an alternative preferred embodiment of the present invention in which a base element 12 is aggregated with a leaded support element 16. FIG. 5 depicts an alternative preferred embodiment of the present invention. Shown in FIG. 5 is a back-to-back embodiment with base element 12 having mounted upon its upper side 18, a support element 16 configured in CSP.
[0044] FIG. 6 depicts a preferred embodiment of the present invention that employs a CSP base element 12 and CSP support elements 14 and 16 interconnected with flex 30. Heat sink 34 is disposed between base element 12 and support elements 14 and 16. As shown in FIG. 6 , heat sink 34 is in contact with a portion of casing 36 of an application in which module 10 is employed.xxx
[0045] FIG. 7 illustrates an alternative preferred embodiment of the invention employed to aggregate leaded packages. Depicted base element 12 is a leaded device while support element 16 is also a leaded device.
[0046] FIG. 8 depicts in enlarged view, the area marked “A” in FIG. 1. FIG. 8 illustrates the connection between example CSP contacts 26 and module contacts 28 through flex 30. A depicted preferred construction for flex 30 is shown in FIG. 8 to be comprised of multiple layers. Flex 30 has a first outer surface 40 and a second outer surface 42. Flex circuit 30 has at least two conductive layers interior to first and second outer surfaces 40 and 42. There may be more than two conductive layers in flex 30. Further, two flex circuits may supplant flex 30 with each wrapping about an opposite side of the assembly. In the depicted preferred embodiment, first conductive layer 44 is at the first conductive layer level of flex 30 while second conductive layer 48 is at the second conductive layer level of flex 30. Typically, both conductive layers are interior to first and second outer surfaces 40 and 42. Intermediate layer 46 lies between first conductive layer 44 and second conductive layer 48. There may be more than one intermediate layer, but an intermediate layer of polyimide is preferred. Similar dielectric materials may be used.
[0047] As depicted in FIG. 8 and seen in more detail in later figures, base flex contact 54 is preferably comprised from metal at the level of second conductive layer 48 interior to second outer surface 42. Base flex contact 54 is solid metal in a preferred embodiment and is preferably comprised of copper and suitable barrier metals or coatings as required. This results in a solid metal pathway from element 12 to an application board thereby providing a significant thermal pathway for dissipation of heat generated in module 10. This depiction of base flex contact 54 illustrates the solid metal path from element 12 to module contact 28 and, therefore, to an application PWB to which module 10 is connectable. As those of skill in the art will understand, heat transference from module 10 is thereby encouraged.
[0048] With continuing reference to FIG. 8 , CSP contact 26 and module contact 28 together offset module 10 from an application platform such as a PWB. The combined heights of CSP contact 26 and module contact 28 provide a moment arm longer than the height of a single CSP contact 26 alone. This provides a longer moment arm through which temperature-gradient-over-time stresses (such as typified by temp cycle), can be distributed and can be helpful particularly where element 12 contacts such as CSP contacts 26 become diminutive as a result of high density contact arrays resulting in small diameter CSP contacts.
[0049] FIG. 9 is an enlarged detail of an exemplar connection between example CSP contact 26 and example module contact 28 through base flex contact 54 to illustrate the solid metal path from element 12 to module contact 28 and, therefore, to an application PWB to which module 10 is connectable. As shown in FIG. 9 , base flex contact 54 is at the level of second conductive layer 48 and is interior to first and second outer surface layers 40 and 42 respectively, of flex circuit 30. Base flex contacts 54 need not be at the level of second conductive layer 48 and may be configured from first conductive layer 44 depending upon the routing demands of the interconnections specified between elements 12 and 14 or 12 and 14 and 16.
[0050] FIG. 10 is an alternative preferred embodiment of the present invention. Depicted in FIG. 10 are base element 12 and support elements 14 and 16 with all of the depicted ICs being packaged in CSP with support elements 14 and 16 extending beyond the physical boundaries of base element 12. Also shown is extensive and preferred use of conformal underfill 32. FIG. 11 is an enlarged section of the preferred embodiment depicted in FIG. 10 and identifies an area “B” that will be further described in FIG. 12.
[0051] FIG. 12 illustrates in enlarged perspective, detail of the area marked “B” in FIG. 11 and illustrates an exemplar connection between example CSP contacts 26 of a support element and support flex contacts 56 of flex 30. In this depiction, support flex contacts 56 are shown as being at the level of first conductive layer 44 of flex 30. FIG. 12 illustrates a via 58 between the support flex contact 56 in contact with the right-most depicted CSP contact 26 and second conductive layer 48. The use of vias between conductive layer levels allows flexibility in strategies employed to connect base element 12 with support elements and allows, for example, the connection of a contact from support elements 14 or 16 to a selected module contact 28. Often, support elements 14 and/or 16 will have signals that are not directly connected to base element 12, but which have functionality relevant to the operation of entire module 10. In such cases, a module contact 28 provides that signal connection to support element 14 or 16 without a corresponding direct connection to base element 12. Such a connection strategy is shown in FIG. 13.
[0052] FIG. 14 is an enlarged depiction of an exemplar area around a base flex contact 54 in a preferred embodiment. The depicted base contact 54 is shown being delineated at the level of second conductive layer 48, but the many base element contacts 54 employed to provide connection to base element 12 may be located at the level of second conductive layer 48 or first conductive layer 44. Although it is not preferable, different base element contacts 54 for the same base element 12 may be located at different conductive layers. That is, some connection strategies may specify that some of the CSP contacts 26 of base element 12 should be connected to flex 30 through base element contacts 54 located at the level of second conductive layer 48, while at the same time, other CSP contacts 26 of base element 12 should be connected to flex 30 through base element contacts 54 located at the level of first conductive layer 44. It is preferable, however, to have all the contacts of base element 12 contact flex 30 at the same conductive layer level of the flex. In the FIG. 14 depiction of an example base contact 54, however, windows 60 and 62 are opened in first and second outer surface layers 40 and 42 respectively, to provide access to a particular exemplar base flex contact 54 residing at the level of second conductive layer 48 in the flex. Base flex contact 54 as is shown in FIG. 14 may be connected to or isolated from the conductive plane of second conductive layer 48. Demarking a lower flex contact 54 from second conductive layer 48 is represented in FIG. 14 by demarcation gap 63 shown at second conductive layer 48. Where a base flex contact 54 or support flex contact 56 is not completely isolated from its conductive layer, demarcation gaps do not extend completely around the flex contact.
[0053] As shown by example in FIG. 14 , CSP contacts 26 of base element 12 pass through a window 60 opened through first outer surface layer 40, first conductive layer 44, and intermediate layer 46, to contact depicted base flex contact 54. Window 62 is opened through second outer surface layer 42 through which module contacts 28 pass to contact base flex contact 54. Where the base flex contact 54 to be contacted is at the level of first conductive layer 44, window 62 passes through second outer surface layer 42 as well as second conductive layer 48 and intermediate layer 46 to reach the level of first conductive layer 44 where the appropriate base flex contact is located while window 60 would pass only through first outer surface layer 40. As earlier shown in FIG. 13 , there need not be a window 60 for every window 62 where a module contact 28 provides connection only to a support element. Similarly, there need not be a window 62 for every window 60 when there is no module contact 28 in physical proximity to a particular base element 12 CSP contact. Where base element 12 is a leaded package, pads connected by vias to appropriate conductive layers are employed with flex 30.
[0054] With continuing reference to FIGS. 13 and 14 , module contacts 28 pass through windows 62 opened in second outer layer 42 to contact base flex contacts 54. In those embodiments such as that shown in FIG. 13 that show module 10 exhibiting an array of module contacts 28 having a greater number of module contacts 28 than the base element 12 exhibits in CSP or other contacts 26, module 10 can express a wider interface for address, data, and control signals than that expressed by the constituent elements 12, 14 and 16. Further, a module contact 28 may also be employed to convey separate enable signals through conductive layer levels to support elements 14 or 16 and thereby provide locations through which support elements 14 or 16 may be selectably enabled.
[0055] Depending upon the frequencies employed by the elements of module 10, the dedication of one of the conductive layers of flex 30 to a particular functionality such as ground or power is typically not required for lower frequency applications. In other applications where higher speeds are encountered or where longer trace lengths beyond the critical length are employed, impedance controlling planes can be used or return paths (power or ground) can be routed next to such traces as a coplanar waveguide.
[0056] FIG. 15 depicts an abstraction of a typical routing employed in first conductive plane 44 by the assignee of the present invention in implementing a preferred embodiment of the present invention. FIG. 15 illustrates an abstraction of the plot employed for the conductive areas of at the level of first conductive plane 44 for the preferred embodiment depicted in FIG. 10. As those of skill will notice, in the plot shown in FIG. 15 , the connective fields identified with references 64 provide connections for support element 14 while connective fields identified with references 66 provide connections for support element 16. Connective field 68 provides connections for base element 12. The connective fields 64 and 66 provide support flex contacts 56 as well as traces that, combined with vias 58, provide part of the connective facility for interconnecting support elements 14 and 16 to base element 12. The view is abstracted with many of the actual routing lines removed to assist in the clarity of the view.
[0057] FIG. 16 depicts an abstraction of a typical routing employed for conductive areas at the level of second conductive plane 48 by the assignee of the present invention in implementing a preferred embodiment of the present invention. FIG. 16 illustrates an abstraction of the plot employed for the preferred embodiment depicted in FIG. 10.
[0058] In the area of FIGS. 15 and 16 employed to connect base element 12, there is illustrated an example of using vias 58 to more fully employ the two conductive layers of the preferred embodiments. Connective fields 65 and 67 indicate vias 58 as well as traces (that are not shown in the depiction for clarity of view) that provide part of the connective facility for interconnecting support elements 14 and 16 to base element 12.
[0059] On the depiction of FIG. 16 , there is found the identification of a base flex contact 54. With reference to earlier FIGS. 13 and 14 , base element 12 has a CSP contact 26 that passes through window 60 and therefore, first conductive layer 44 shown in FIG. 15 , to contact the base flex contact 54 at the level of the second conductive layer as shown in FIG. 16. It should be understood that this is a heuristic explanation and meant to be merely an example illustrating a feature found in some preferred embodiments of the invention.
[0060] Base flex contact 54 at the level of second conductive layer 48 is connected to a via 58 by a trace 70. Via 58 passes in a relatively upward direction toward the body of base element 12. As via 58 passes upwardly through flex 30, it contacts a conductive area at the level of first conductive layer 44 as shown in FIG. 15 by the identification of via 58. Via 58 is then connected to trace 72 that provides a connection network to a variety of other contacts in the depicted embodiment. For example, trace 72 branches to connect to another via 58 identified in the lower part of FIG. 15. Thus, the use of two conductive layers is given an added flexibility by the illustrated use of vias through an intermediate layer.
[0061] Vias that route through intermediate layer 46 to interconnect traces or flex contacts or conductive areas at different conductive layers may be “on-pad” or coincident with the support or base flex contact to which they are connected. Such vias may also be “off-pad” and located near windows associated with the flex contacts from which signals are to be conveyed to another conductive layer. This provides added flexibility to connection schemes and layout routing. Another explication of the use of on-pad and off-pad vias that is suitable for use in the present invention is provided in incorporated and pending U.S. application Ser. No. 10/005,581, filed Oct. 26, 2001. Therein there is also found strategies for interconnection of elements using a multi-layer flex circuit that dedicates conductive layers to particular functions. Such a strategy may be used with the present invention where the simplicity of the interconnection allows.
[0062] As those of skill will recognize, the connection between conductive layers provided by vias (on or off pad) may be provided by any of several well-known techniques such as plated holes or solid lines or wires and need not literally be vias.
[0063] Although the present invention has been described in detail, it will be apparent to those skilled in the art that the invention may be embodied in a variety of specific forms and that various changes, substitutions and alterations can be made without departing from the spirit and scope of the invention. The described embodiments are only illustrative and not restrictive and the scope of the invention is, therefore, indicated by the following claims.
Claims
1. A circuit module comprising:
a base element CSP integrated circuit having first and second oppositely facing major surfaces, the first major surface having a plurality of base element contacts;
a support element CSP integrated circuit having first and second oppositely facing major surfaces, the first major surface having a plurality of support element contacts, the base element CSP integrated circuit and the support element CSP integrated circuit being in a stacked disposition to orient their respective second major surfaces toward each other, whereby the plurality of base element contacts face away from the plurality of support element contacts;
a flex circuit comprising one or more conductive layers, base element flex contacts connected to at least one of the one or more conductive layers, and support element flex contacts connected to at least one of the one or more conductive layers, the base element flex contacts being in contact with the plurality of base element contacts and the support element flex contacts being in contact with the plurality of support element contacts.
2. A circuit module comprising:
a base element CSP integrated circuit having two major surfaces and comprising a first set of contacts;
a support element CSP integrated circuit having two major surfaces and comprising a first set of contacts, the base element CSP integrated circuit and the support element CSP integrated circuit being in a stacked disposition relative to each other;
a flex circuit comprising a first conductive layer disposed at a first conductive layer level of the flex circuit and a second conductive layer disposed at a second conductive layer level of the flex circuit, between which conductive layer levels is an intermediate layer, conductive areas at the first conductive layer level of the flex circuit being in contact with the first sets of contacts of the base element and the support element integrated circuits;
wherein the first set of contacts of each of the base element and support element CSP integrated circuits are disposed along a first one of the two major surfaces of the base element and support element CSP integrated circuits, respectively, and the base element CSP integrated circuit and the support element CSP integrated circuit are in stacked disposition that disposes a second one of the two major surfaces of the base element CSP integrated circuit nearer a second one of the two major surfaces of the support element CSP integrated circuit than the first one of the two major surfaces of the support element CSP integrated circuit.
3. The circuit module of claim 2 in which a heat transference element is disposed between the second major surface of the two major surfaces of the base element CSP integrated circuit and the second major surface of the two major surfaces of the support element CSP integrated circuit.
Patent Citations (142)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3436604(A) | 1969-04-01 | Hyltin | Applicant |
| US3654394(A) | 1972-04-01 | Gordon | Applicant |
| US3727064(A) | 1973-04-01 | Bottini | Applicant |
| US3746934(A) | 1973-07-01 | Stein | Applicant |
| US3772776(A) | 1973-11-01 | Weisenburger | Applicant |
| US4103318(A) | 1978-07-01 | Schwede | Applicant |
| US4288841(A) | 1981-09-01 | Gogal | Applicant |
| US4398235(A) | 1983-08-01 | Lutz et al. | Applicant |
| US4406508(A) | 1983-09-01 | Sadigh-Behzadi | Applicant |
| US4437235(A) | 1984-03-01 | McIver | Applicant |
| US4513368(A) | 1985-04-01 | Houseman | Applicant |
| US4645944(A) | 1987-02-01 | Uya | Applicant |
| US4696525(A) | 1987-09-01 | Coller et al. | Applicant |
| US4733461(A) | 1988-03-01 | Nakano | Applicant |
| US4763188(A) | 1988-08-01 | Johnson | Applicant |
| US4821007(A) | 1989-04-01 | Fields et al. | Applicant |
| US4823234(A) | 1989-04-01 | Konishi et al. | Applicant |
| US4833568(A) | 1989-05-01 | Berhold | Applicant |
| US4862249(A) | 1989-08-01 | Carlson | Applicant |
| US4884237(A) | 1989-11-01 | Mueller et al. | Applicant |
| US4891789(A) | 1990-01-01 | Quattrini et al. | Applicant |
| US4911643(A) | 1990-03-01 | Perry et al. | Applicant |
| US4953060(A) | 1990-08-01 | Lauffer et al. | Applicant |
| US4956694(A) | 1990-09-01 | Eide | Applicant |
| US4983533(A) | 1991-01-01 | Go | Applicant |
| US4985703(A) | 1991-01-01 | Kaneyama | Applicant |
| US5012323(A) | 1991-04-01 | Farnworth | Applicant |
| US5016138(A) | 1991-05-01 | Woodman | Applicant |
| US5034350(A) | 1991-07-01 | Marchisi | Applicant |
| US5041015(A) | 1991-08-01 | Travis | Applicant |
| US5099393(A) | 1992-03-01 | Bentlage et al. | Applicant |
| US5104820(A) | 1992-04-01 | Go et al. | Applicant |
| US5138430(A) | 1992-08-01 | Gow, 3rd et al. | Applicant |
| US5159434(A) | 1992-10-01 | Kohno et al. | Applicant |
| US5198888(A) | 1993-03-01 | Sugano et al. | Applicant |
| US5222014(A) | 1993-06-01 | Lin | Applicant |
| US5224023(A) | 1993-06-01 | Smith et al. | Applicant |
| US5239198(A) | 1993-08-01 | Lin et al. | Applicant |
| US5241454(A) | 1993-08-01 | Ameen et al. | Applicant |
| US5247423(A) | 1993-09-01 | Lin et al. | Applicant |
| US5259770(A) | 1993-11-01 | Bates et al. | Applicant |
| US5261068(A) | 1993-11-01 | Gaskins et al. | Applicant |
| US5262927(A) | 1993-11-01 | Chia et al. | Applicant |
| US5279029(A) | 1994-01-01 | Burns | Applicant |
| US5281852(A) | 1994-01-01 | Normington | Applicant |
| US5289062(A) | 1994-02-01 | Wyland | Applicant |
| US5311401(A) | 1994-05-01 | Gates, Jr. et al. | Applicant |
| US5313097(A) | 1994-05-01 | Haj-Ali-Ahmadi et al. | Applicant |
| US5343075(A) | 1994-08-01 | Nishino | Applicant |
| US5347428(A) | 1994-09-01 | Carson et al. | Applicant |
| US5375041(A) | 1994-12-01 | McMahon | Applicant |
| US5377077(A) | 1994-12-01 | Burns | Applicant |
| US5394010(A) | 1995-02-01 | Tazawa et al. | Applicant |
| US5402006(A) | 1995-03-01 | O'Donley | Applicant |
| US5420751(A) | 1995-05-01 | Burns | Applicant |
| US5428190(A) | 1995-06-01 | Stopperan | Examiner |
| US5446620(A) | 1995-08-01 | Burns et al. | Applicant |
| US5455740(A) | 1995-10-01 | Burns | Applicant |
| US5475920(A) | 1995-12-01 | Burns et al. | Applicant |
| US5479318(A) | 1995-12-01 | Burns | Applicant |
| US5484959(A) | 1996-01-01 | Burns | Applicant |
| US5493476(A) | 1996-02-01 | Burns | Applicant |
| US5499160(A) | 1996-03-01 | Burns | Applicant |
| US5514907(A) | 1996-05-01 | Moshayedi | Applicant |
| US5523619(A) | 1996-06-01 | McAllister et al. | Applicant |
| US5541812(A) | 1996-07-01 | Burns | Applicant |
| US5543664(A) | 1996-08-01 | Burns | Applicant |
| US5561591(A) | 1996-10-01 | Burns | Applicant |
| US5566051(A) | 1996-10-01 | Burns | Applicant |
| US5572065(A) | 1996-11-01 | Burns | Applicant |
| US5592364(A) | 1997-01-01 | Roane | Applicant |
| US5612570(A) | 1997-03-01 | Eide et al. | Applicant |
| US5631193(A) | 1997-05-01 | Burns | Applicant |
| US5644161(A) | 1997-07-01 | Burns | Applicant |
| US5654877(A) | 1997-08-01 | Burns | Applicant |
| US5776797(A) | 1998-07-01 | Nicewarner, Jr. et al. | Applicant |
| US5778522(A) | 1998-07-01 | Burns | Applicant |
| US5801437(A) | 1998-09-01 | Burns | Applicant |
| US5805422(A) | 1998-09-01 | Otake et al. | Applicant |
| US5828125(A) | 1998-10-01 | Burns | Applicant |
| US5835988(A) | 1998-11-01 | Ishii | Applicant |
| US5869353(A) | 1999-02-01 | Levy et al. | Applicant |
| US5926369(A) | 1999-07-01 | Ingraham et al. | Applicant |
| US5949657(A) | 1999-09-01 | Karabatsos | Applicant |
| US5953215(A) | 1999-09-01 | Karabatsos | Applicant |
| US6014316(A) | 2000-01-01 | Eide | Applicant |
| US6025642(A) | 2000-02-01 | Burns | Applicant |
| US6028352(A) | 2000-02-01 | Eide | Applicant |
| US6028365(A) | 2000-02-01 | Akram et al. | Applicant |
| US6072233(A) | 2000-06-01 | Corisis et al. | Applicant |
| US6097087(A) | 2000-08-01 | Farnworth et al. | Applicant |
| USRE36916(E) | 2000-10-01 | Moshayedi | Applicant |
| US6172874(B1) | 2001-01-01 | Bartilson | Applicant |
| US6205654(B1) | 2001-03-01 | Burns | Applicant |
| US6208521(B1) | 2001-03-01 | Nakatsuka | Applicant |
| US6225688(B1) | 2001-05-01 | Kim et al. | Applicant |
| US6233650(B1) | 2001-05-01 | Johnson et al. | Applicant |
| US6262476(B1) | 2001-07-01 | Vidal | Applicant |
| US6262895(B1) | 2001-07-01 | Forthun | Applicant |
| US6265660(B1) | 2001-07-01 | Tandy | Applicant |
| US6266252(B1) | 2001-07-01 | Karabatsos | Applicant |
| US6281577(B1) | 2001-08-01 | Oppermann et al. | Applicant |
| US6300679(B1) | 2001-10-01 | Mukerji et al. | Applicant |
| US6323060(B1) | 2001-11-01 | Isaak | Applicant |
| US6351029(B1) | 2002-02-01 | Isaak | Applicant |
| US6368896(B2) | 2002-04-01 | Farnworth et al. | Applicant |
| US6392162(B1) | 2002-05-01 | Karabatsos | Applicant |
| US6410857(B1) | 2002-06-01 | Gonya | Examiner |
| US6426240(B2) | 2002-07-01 | Isaak | Applicant |
| US6426549(B1) | 2002-07-01 | Isaak | Applicant |
| US6433418(B1) | 2002-08-01 | Fujisawa et al. | Applicant |
| US6444921(B1) | 2002-09-01 | Wang et al. | Examiner |
| US6446158(B1) | 2002-09-01 | Karabatsos | Applicant |
| US6462412(B2) | 2002-10-01 | Kamei et al. | Applicant |
| US6465877(B1) | 2002-10-01 | Farnworth et al. | Applicant |
| US6465893(B1) | 2002-10-01 | Khandros et al. | Applicant |
| US6473308(B2) | 2002-10-01 | Forthun | Applicant |
| US6486544(B1) | 2002-11-01 | Hashimoto | Applicant |
| US6514793(B2) | 2003-02-01 | Isaak | Applicant |
| US6560117(B2) | 2003-05-01 | Moon | Applicant |
| US6572387(B2) | 2003-06-01 | Burns et al. | Applicant |
| US6590282(B1) | 2003-07-01 | Wang et al. | Applicant |
| US6600222(B1) | 2003-07-01 | Levardo | Applicant |
| US6620651(B2) | 2003-09-01 | He et al. | Applicant |
| US6657134(B2) | 2003-12-01 | Spielberger et al. | Examiner |
| US2002/0006032(A1) | 2002-01-01 | Karabatsos | Applicant |
| US2002/0101261(A1) | 2002-08-01 | Karabatsos | Applicant |
| US2002/0139577(A1) | 2002-10-01 | Miller | Applicant |
| US2002/0164838(A1) | 2002-11-01 | Moon et al. | Applicant |
| US2002/0180022(A1) | 2002-12-01 | Emoto | Applicant |
| EP122-687(A) | 1984-10-01 | Applicant | |
| EP298211(A) | 1989-01-01 | Applicant | |
| EP461-639(A) | 1991-12-01 | Applicant | |
| JP57-31166(A) | 1982-02-01 | Applicant | |
| JP58-96756(A) | 1983-06-01 | Applicant | |
| JP58-112348(A) | 1983-07-01 | Applicant | |
| JP60-254762 | 1985-12-01 | Applicant | |
| JP62-230027(A) | 1987-10-01 | Applicant | |
| JP65-153849(A) | 1988-06-01 | Applicant | |
| JP4209562 | 1992-07-01 | Applicant | |
| JP5-21697(A) | 1993-01-01 | Applicant | |
| RU834-957 | 1981-05-01 | Applicant |
Non-Patent Literature (19)
- Dense-Pac Microsystems, 16 Megabit High Speed CMOS SRAM DPSIMX16MKn3.Applicant
- Dense-Pac Microsystems, 256 Megabyte CMOS DRAM DP3ED32MS72RW5.Applicant
- Dense-Pac Microsystems, Breaking Space Barriers, 3-D Technology 1993.Applicant
- Dense-Pac Microsystems, DPS512X16A3, Ceramic 512K X 16 CMOS SRAM Module.Applicant
- “Deisgn Techniques for Ball Grid Arrays,” William R. Newberry, Xynetix Design Systems, Inc.Applicant
- “Chip Scale Packaging and Redistribution,” Paul A. Magill, Glenn A. Rinne, J. Daniel Mis, Wayne C. Machon, Joseph W. Baggs, Unitive Electronics Inc.Applicant
- “Alterable Interposer Block for Personalizing Stacked Module Interconnections,” IBM Technical Disclosure Bulletin, vol. 30, No. 8, Jan. 8, 1988, pp. 373-374.Applicant
- IBM Preliminary 168 Pin SDRAM Registered DIMM Functional Description & Timing Daigrams.Applicant
- “3D Interconnection for Ultra-Dense Multichip Modules,” Christian VAL, Thomson-CSF DCS Computer Division, Thierry Lemoine, Thomson-CSF RCM Radar Countermeasures Divison.Applicant
- “High Density Memory Packaging Technology High Speed Imaging Applications,” Dean Frew, Texas Instruments Incorporated.Applicant
- Teresa Technologies, Inc.—Semiconductor Intellectual Property, Chip Scale Packaging—Website pages (3).Applicant
- “Vertically-Integrated Package,” Alvin Weinberg, Pacesetter, Inc. and W. Kinzy Jones, Florida International University.Applicant
- Ron Bauer, Intel. “Stacked-CSP Delivers Flexibility, Reliability, and Space-Saving Capabilities”, Spring 2002.Applicant
- Tessera uZ Ball Stack Package. 4 figures that purport to be directed to the uZ—Ball Stacked Memory Page.Applicant
- Tessera Introduces uZ ä—Ball Stacked Memory Package for Computing and Portable Electronic Products Joyce Smaragdis, Tessera Public Relations (www.tessera.com/news_events/press_coverage.cfm); 2 figures that purport to be directed to the uZ ä—Ball Stacked Memory Package.Applicant
- Chip Scale Review Online—An Independent Journal Dedicated to the Advancement of Chip-Scale Electronics. (Website 9 pages) Fjelstad, Joseph, Pacific Consultants L.L.C.Applicant
- Flexible Thinking: Examining the Flexible Circuit Tapes. (Website 2 pages) Fjelstad, Joseph.Applicant
- Die Products: Ideal IC Packaging for Demanding Applications—Advanced packaging that's no bigger than the die itself brings together high performance and high reliability with small size and low cost. (Website 3 pages with 2 figures) Larry Gilg and Chris Windsor. Dec. 23, 2002.Applicant
- Flexible Printed Circuit Technology—A Versatile Interconnection Option. (Website 2 pages) Fjelstad, Joseph, Dec. 3, 2002.Applicant