Contactless electrical energy transmission system having a primary side current feedback control and soft-switched secondary side rectifier

[0001] Generally, the present invention relates to the field of contactless electrical energy transmission (CEET) systems, more particularly, to CEET systems that provide highly regulated power to a load.

[0002] Contactless electrical energy transmissions are known for the convenience by which they deliver power to a load. Generally, CEET systems transfer power via an air-gap inductive coupling without there being any direct electric connection between a primary side and a secondary side. As such, in some applications, CEET systems offer distinct advantages over energy transmission systems that use wires and connectors. For example, CEET systems are preferred in hazardous applications such as mining and underwater environments due to the elimination of the sparking and the risk of electrical shocks. Other exemplary applications that use CEET systems include charging devices that safely and reliably transfer power to consumer electronic devices and medical devices.

[0003] A typical CEET system consists of a transmitter in the primary side, a transformer, and a receiver in the secondary side. Such CEET system employs a primary inverter at the transmitter and a secondary rectifier at the receiver. The inverter and rectifier are coupled to each other via the primary and secondary windings of the transformer. Since the primary winding and the secondary winding are inductively coupled through the air-gap, electric power is transferred from the primary side to the secondary side as magnetic energy obviating the need for any physical electrical interconnections.

[0004] However, power transmission via the inductive coupling of the CEET transformer has certain drawbacks in terms of low efficiency and unregulated delivery of power to the load. This is because the leakage inductance of the CEET transformer with air-separated primary and secondary windings is much larger than the leakage inductance of a conventional transformer that uses well interleaved primary and secondary windings. The CEET primary and secondary windings can store high amounts of leakage inductance energy that can cause high parasitic ringing and losses. Moreover, in CEET systems, it is very difficult to regulate power transmission mainly because there is no physical connection between the primary side and the secondary side that would provide feedback information for regulating the power transmission.

[0005] FIG. 1 shows one CEET system that achieves high efficiency by recovering the energy stored in the leakage inductance of the transformer. This system, which is more fully described in U.S. Pat. No. 6,301,128 B1, issued to Delta Electronics, Inc., the assignee of the present invention, incorporates the leakage inductance of each one of the primary and secondary sides in its power stage. The primary side includes a variable-frequency resonant inverter and the secondary side includes a controlled rectifier. An input-voltage feed forward control block controls the output frequency of the variable-frequency resonant inverter in response to source voltage variations, while a pulse width modulated (PWM) output voltage feedback control block controls the controlled rectifier output in response to load variations. Under this arrangement, the PWM output voltage feedback control block and the input-voltage feed forward control block act as independent controls for regulating the output voltage without any feedback connection between the primary and secondary sides. FIG. 2 shows a more detailed schematic block diagram of the power stage and the controllers shown in FIG. 1.

[0006] In conventional CEET systems, lack of any feedback information from the secondary side to the primary side prevents adjusting energy transfer from the primary side in response to load variations that occur on the secondary side. Thus, the maximum transferable power through the inductive coupling of the primary and secondary sides can vary under a range of light-load to high-load conditions. Such variations can create extra circulating energy and conduction losses. Moreover, for pulse width modulated control of energy transfer on the secondary side, the ratio of the duty cycle variations can be very large at high-load and light-load conditions. As a result, guaranteeing reliable operation over the entire load range requires complex circuitry for implementing a suitable feedback control.

[0007] Finally, switch S_S of the controlled rectifier in FIG. 2 turns on with hand switching, i.e., when the MOSFET switch turns on when the voltage across the switch is equal to the output voltage. The hard switching is not desirable, because it increases conductive noise and energy loss in the CEET system.

[0008] Therefore, there exists a need for a simple CEET solution that provides a highly regulated power transfer between the primary and secondary sides and avoids harmful hard switching conditions.

[0009] Briefly, according to the present invention, a contactless electrical energy transmission system couples a power source to a load. The system includes a transformer having a primary winding that is coupled to the power source through a primary resonant circuit of an inverter and a secondary winding that is coupled to the load through a secondary resonant circuit of a rectifier. The primary and secondary resonant circuits are inductively coupled to each other. A primary control circuit is responsive to a current change through the primary resonant circuit to control the switching frequency of a controllable switching device for maintaining a substantially constant energy transfer between the primary winding and secondary winding in response to either one or both of a power source voltage change and a load change.

[0010] According to another aspect, a secondary control circuit generates one or more pulse width modulated control signals for controlling the amount of energy delivered to the load under varying load conditions. The pulse width modulated signals are generated in response to a voltage variation across the load and a zero current crossing through the secondary resonant circuit.

[0011] According to yet another aspect of the present invention, a secondary controllable switching circuit is responsive to one or more pulse width modulated control signals. The secondary controllable switching circuit has one or more switches that are activated at substantially zero voltage to avoid hard switching conditions.

[0012] According to some of the more detailed features of the present invention, the secondary control circuit detects a zero current crossing through the secondary resonant circuit to generate synchronized ramp signals for controlling the pulse width modulated control signals. In an exemplary embodiment, the synchronized ramp signals are 180° out of phase from each other.

[0021] FIG. 3 shows an exemplary block diagram of the CEET system in accordance with the present invention. The system of FIG. 3 includes a variable frequency resonant inverter at a primary side and a controlled rectifier at a secondary side that includes a load. The primary side and secondary side are inductively coupled through the primary and secondary windings of a transformer. As shown, the inverter couples a power source having a power voltage V_S to the primary winding through a primary resonant circuit comprising inductive and capacitive elements in the primary side. As described later in detail, a primary-current feed back frequency control block controls a primary switching frequency for regulating the power transfer between the primary and secondary sides. On the secondary side, the rectifier, which is a controlled zero-voltage switching (ZVS) rectifier, couples the secondary winding to a load through a secondary resonant circuit comprising inductive and capacitive elements in the secondary side. The primary resonant circuit and the secondary resonant circuit are inductively coupled each other through the primary and secondary windings of the transformer.

[0022] In accordance with one aspect of the present invention, current through the primary winding is controlled in response to a sensed current change that is caused by a power voltage V_S or a load change. As such either one of a power voltage change or load change or both regulate the power transfer between the primary and secondary sides. More specifically, a primary controllable switching device has a switching frequency that controls the current flow through the primary winding. This aspect of the present invention senses primary resonant current changes for controlling the switching frequency of the primary controllable switching device so that the transferred power through the transformer is automatically maintained constant relative to power voltage V_S and load changes. Also, as described later in detail, in accordance with another aspect of the present invention, a secondary current zero-cross detection block is used with a synchronized ramp signal generator to control a pulse width modulated (PWM) feedback control block that provides tightly regulated control over a wide range of load conditions.

[0023] FIG. 4 shows a more detailed block diagram of the CEET system of FIG. 3 with a series resonant inverter in the primary side. The primary side is comprised of a pair of primary switches S_H and S_L, which are shown with their antiparallel diodes. These switches form a primary controlled switching circuit. The inverter also includes a resonant capacitor C_P, which is part of the primary resonant circuit. The secondary side is comprised of resonant capacitor C_S, diodes D_{1 and D2}, and filter capacitor C. Secondary switches S₁ and S₂, which are also shown with their antiparallel diodes, form a secondary controlled switching circuit.

[0024] FIG. 5 shows an equivalent circuit to the CEET system of the invention with leakage L_P, L_S, and magnetizing L_M inductances of the transformer. To simplify the analysis, it is assumed that the input- and output-ripple voltages are negligible so that the voltages across the input and output filter capacitors can be represented by constant-voltage sources V_S and V_O, respectively. As such, inductive and capacitive elements shown on the primary and secondary sides create respective primary and secondary resonant circuits that are inductively coupled to each other.

[0025] To further facilitate the explanation of the operation, FIGS. 6(a)-(l) show topological stages of the circuit in FIG. 5 during a switching cycle, whereas FIGS. 7(a)(-(q) show the power-stage key waveforms for operation. To further simplify the analysis, the following analysis of operation assumes that all semiconductor components in the circuit are ideal. i.e., that they exhibit zero resistance when in the on state and infinite resistance in the off state. Moreover, the magnetizing current i_M in FIG. 5 is in phase with resonant current i_LS. Nevertheless, these assumptions do not have any significant effect on the explanation of the principle of operation of the proposed circuit.

[0026] Before secondary switch S₁, is turned on at t=T₀, negative primary side resonant current i_LP=i_M+i_P=i_M+i_LS/n flows through leakage inductance L_P, resonant capacitor C_P, and low-side switch S_L, whereas, negative secondary-side resonant current i_LS flows through leakage inductance L_S, resonant capacitor C_S, output diode D₂, and the antiparallel diode of secondary switch S₁, as shown in FIG. 6(l). At the same time, output diode D₁ and secondary switch S₂ are off blocking output voltage V₀, whereas, high-side switch S_H is off blocking input voltage V_S. As a result, secondary switch S₁ turns on with ZVS at t=T₀, as shown in FIG. 6(a).

[0027] After secondary switch S₁ is turned on, the direction of the resonant current is not changed until low-side switch S_L is turned off at t=T₁. After low-side switch S_L is turned off at t=T₁, resonant current i_LP flowing through switch S_L is diverted from the switch to its output capacitance C_OSSL, as shown in FIG. 6(b). As a result, the voltage across switch S_L starts increasing, whereas the voltage across high-side switch S_H starts decreasing, as illustrated in FIGS. 7(c) and 7(d), since the sum of the voltage across switches S_L and S_H is equal to input voltage V_S. When the voltage across high-side switch S_H reaches zero at t=T₂, i.e., when output capacitance C_OSSH of high-side switch S_H fully discharged, the antiparallel diode of high-side switch S_H begins to conduct, as shown in FIG. 6(c). At the same time, low-side switch S_L is off blocking input voltage V_S. Because after t=T₂ input voltage V_S is connected to the resonant circuit, the resonant current starts increasing. This topological stage ends at t=T₄ when i_LP reaches zero and the antiparallel diode of high-side switch S_H stops conducting. As can be seen from FIG. 7(e), to achieve ZVS of S_H, it is necessary to turn on S_H while its antiparallel diode is conducting.

[0028] In FIG. 7(a), high-side switch S_H is turned on at t=T₃ with ZVS. As a result, after t=T₄ resonant current i_LP continues to flow through closed switch S_H, as shown in FIG. 6(e). Because of the assumption that currents i_M and i_LS are in phase with current i_LP, when the direction of current i_LP is reversed at t=T₄, the direction of i_M and i_LS is also reversed, as illustrated in FIGS. 7(e)-7(g). Consequently, at t=T₄ current i_LS which was flowing through output diode D₂ and the antiparallel diode of switch S₁, is diverted to the antiparallel diode of switch S₂ and switch S₁, as shown in FIG. 6(e). This topological stage ends at t=T₅, when secondary switch S₁ is turned off.

[0029] After secondary switch S₁ is turned off at t=T₅, primary side resonant current i_LP flows through leakage inductance L_P, resonant capacitor C_P, and high-side switch S_H, whereas, secondary-side resonant current i_LS flows through leakage inductance L_S, resonant capacitor C_S, output diode D₁, and the antiparallel diode of secondary switch S₂, as shown in FIG. 6(f). As a result, secondary switch S₂ can be turned on with ZVS at t=T₆, as shown in FIG. 6(g). This topological stage ends at t=T₇, when high-side switch S_H is turned off. After high-side switch S_H is turned off at t=T₇, resonant current i_LP flowing through switch S_H is diverted from the switch to its output capacitance C_OSSH, as shown in FIG. 6(h). As a result, output capacitance C_OSSH is being charged, whereas output capacitance C_OSSL is being discharged. When output capacitance C_OSSL is fully discharged at t=T₈, the antiparallel diode of low-side switch S_L begins to conduct, as shown in FIG. 6(i). At the same time, high-side switch S_H is off blocking input voltage V_S. This topological stage ends at t=T₁₀ when i_LP reaches zero and the antiparallel diode of low-side switch S_L stops conducting. To achieve ZVS of S_L, it is necessary to turn on S_L while its antiparallel diode is conducting. In FIG. 7, low-side switch S_L is turned on at t=T₉ with ZVS. As a result, after t=T₁₀ resonant current i_LP continues to flow through closed switch S_L, as shown in FIG. 6(j). As shown in FIGS. 6(k) and 7, after t=T₁₀, the direction of currents i_LP, i_M, and i_LS are reversed so that current i_LP flows through S_L, whereas, current i_LS flows through switch S₂ and the antiparallel diode of switch S₁, as shown in FIG. 6(k). The circuit stays in this topological stage until the next switching cycle is initiated at t=T₁₂.

[0030] As can be seen, the voltage stress of switches S_H and S_L is always limited to input voltage V_S while the voltage stress of S₁, S₂, D₁, and D₂ are always limited to the output voltage V_O.

[0031] FIG. 8 shows an exemplary implementation of the CEET system of the present invention. The primary side includes a primary control block that uses current feed back for frequency control. The primary control block comprises an error amplifier with compensator that receives a sensed primary current I_PR(SENSE) and a reference current signal I_REF. Because of the primary and secondary resonant circuits are inductively coupled to each other, the sensed primary current I_PR(SENSE) varies relative to the power voltage V_S changes as well as load changes. Based on the inputted sensed primary current I_PR(SENSE) and reference current signal I_REF, the error amplifier circuit generates an error signal V_C, which is applied to a voltage controlled oscillator (VCO). The VCO output sets the primary switching frequency f_s used to control the primary controlled switching circuit, which includes primary switches S_H and S_L. A driver controls the switching states of the primary switches S_H and S_L by turning them on and off in accordance with the primary switching frequency f_S.

[0032] Because the primary switching frequency f_S controls the current flow through the primary winding, the disclosed arrangement maintains a constant energy transfer between the primary and secondary sides over the entire range of power voltage V_S and load variations. Consequently, the CEET system of the invention provides a tight regulation of delivered power over the entire load and power source voltage ranges without a physical feedback connection between the primary side and secondary side. As sated above, the primary switching frequency f_S is controlled to keep the magnitude of the primary current constant, so that the maximum transferable power through the inductive coupling is automatically kept constant without an excessive circulating energy.

[0033] Preferably, the range of the primary switching frequency f_S is set to be higher than the primary resonant frequency to provide a Zero Voltage Switching (ZVS) arrangement for the primary switches S_H and S_L, thereby avoiding hard switching conditions. Alternatively, the primary switching frequency f_S can be set to be lower than the primary resonant frequency primary to operate the primary switches S_H and S_L with a zero current switching (ZCS) arrangement.

[0034] In accordance with another aspect of the present invention, the CEET system provides the output voltage feedback controller with a constant PWM gain over the entire load range using synchronized ramp signals. The diodes D_{1 and D2}, which form the secondary rectifier, are controlled by a secondary control block. The secondary control block uses a ZVS PWM control to maintain a tight regulation of the output voltage in the presence of a varying load. The secondary control block includes two PWM modulators that are responsive to the output voltage variations and the synchronized ramp signals for controlling the secondary switches S₁ and S₂ during various load conditions including light load and high load conditions. Under this Arrangement, a sensed output voltage V_O(SENSE) is compared with a reference voltage V_REF at the input of an error with compensation amplifier. A generated error signal V_EA at the output of the error amplifier is compared with ramp signals V_RAMP1 and V_RAMP2. Ramp signals V_RAMP1 and V_RAMP2 are synchronized to the zero crossing of the secondary resonant current and 180° out of phase each other as shown in FIGS. 7(h) and 7(i). By the comparisons between error signal V_EA and ramp signals V_RAMP1, and V_RAMP2, gate signals S₁ and S₂ are generated as shown in FIGS. 7(j) and 7(n).

[0035] According to another aspect of the present invention, the gate signals are generated such that the secondary switches S1 and S2 turn on when their antiparallel diodes are conducting. As a result, the CEET system of the present invention not only provides ZVS for the primary switches S_H and S_L but also for the secondary switches S₁ and S₂.

[0036] When S₁ and S₂ are shorted, i.e., turned on, the load is separated from the secondary resonant circuit, causing less damped resonance and thereby increasing the secondary resonant current. This is because the secondary resonant current does not go through the load and is bypassed through the S₁ and S₂ causing a short circuit with no damping that results in the secondary resonant current to increase. Because of the inductive coupling provided by the primary and secondary windings, the increased current is sensed at the primary side. Based on the increased sensed current, the primary control block Increases the switching frequency to maintain constant current through the primary winding.

[0037] In case of above resonant frequency operation, when the switching frequency is reduced, higher current and thus more energy is delivered to the load. Conversely, when the switching frequency is increased, lower current and thus less energy is delivered to the load. This can happen when S₁ and S₂ are opened, i.e., turned off. As a result, the load is connected in series to the secondary resonant circuit increasing resonance damping, which reduces secondary resonant current flow. As a result, sensed resonant current at the primary side is reduced, thereby reducing the primary switching frequency to maintain constant current through the primary winding. It should be noted that S₁ and S₂ operate at the same frequency as the primary side switches S_L and S_H.

[0038] In an exemplary implementation, the performance of the CEET system of the invention was evaluated on a 36-W (12 V/3 A), universal-line-range (90-265 V_AC) prototype circuit operating over a switching frequency range from 125 kHz to 328 kHz. The experimental circuit was implemented with the following components: switches S_H and S_L—IRF840; secondary switch S₁ and S₂—SI4810DY; and output diode D₁ and D₂=MBR2045CT. Inductive coupling transformer T was built using a pair of modified ferrite cores (EER28-3F3) with the primary winding (80 turns of AWG#44/75 strands Litz wire) and the secondary winding (18 turns of AWG#42/150 strands Litz wire). The control circuit was implemented with controllers UC3863, LM319, AD817, and LM393. A TL431 voltage-reference ICs is used for an output voltage reference for the locally controlled rectifier. An IR2110 driver is used to generate the required gate-drive signals for switches S_H and S_L. Two TC4420 drivers are used to generate the required gate-drive signals for switches S₁ and S₂. The output voltage of the experimental circuit is well regulated with a voltage ripple less than 2% over the entire input-voltage range. The measured efficiencies are approximately 84.4% at full load and minimum input voltage and approximately 78.5% at full load and maximum input voltage.