Shared memory architecture in GPS signal processing

[0001] This application is a continuation of U.S. utility application entitled, “Shared Memory Architecture in GPS Signal Processing,” having Ser. No. 09/465,985, filed Dec. 16, 1999 now U.S. Pat. No. 6,526,322, which is entirely incorporated herein by reference.

[0002] This invention relates to the field of GPS receivers.

[0003] FIG. 1 illustrates a typical GPS radio receiver 10, while FIG. 2 provides a general flow chart illustrating the general operations of GPS receiver 10 such as a satellite signal acquisition, tracking, or re-acquisition, and navigational processing. As illustrated in the simplified block diagram of a typical GPS receiver 10 shown in FIG. 1, a signal processing block 20 is provided to perform satellite signal acquisition and processing on a digitized IF signal 19 received via receiver antenna 12. Signal processing block 20 typically performs a two-dimensional search for a satellite signal, in time (code phase) and frequency. To decrease the amount of time needed for GPS signal acquisition in time and frequency domains, a massively parallel architecture is usually required for searching in parallel a large number of code positions and frequency uncertainties. In the code phase search, the required number of code positions is directly related to initial time uncertainty. A large number of corellators allows a quick, parallel search of many code positions. In the frequency search, a large number of frequency bins architecture speeds up searching multiple frequency uncertainties in parallel, thereby reducing the total time for search.

[0004] As illustrate in FIG. 1, signal processing 20 consists of three functional stages: a first stage consists of channel correlation signal processing 22 that compares (or correlates) digitized signal 19 with a locally generated code that attempts to replicate the P or C/A code generated by a satellite. The replica code searches a “space” that consists of the unique codes generated by the different satellites, the temporal position of the code being sent at any given time, and the Doppler frequency offset caused by the relative motion of the satellite and user. Generally, correlator signal processing unit 22 can perform parallel correlations with multiple code/position/Doppler combinations simultaneously in a multiple channel fashion, usually up to 12. The next functional stage of signal processing 20 comprises tracking processing unit 24, typically provided by a tracking processing CPU. The tracking processing CPU uses correlator information from correlator signal processing unit 22 to ascertain the probability of correctness of a code/position/Doppler combination and to “follow”, or track, that signal once it is found. Tracking processing unit 24 includes having the tracking CPU program the correlator signal processing unit 22 where to search for a GPS satellite signal. Once a signal is found and locked onto, the tracking CPU also extracts the 50 Hz modulated data that contains navigation information transmitted by the GPS satellite. Finally, a navigation processing unit 26, comprising a navigation processing CPU, uses data collected by the correlator signal processing unit 22 and tracking processing unit 24 to perform the calculations to determine the user's position, velocity, and time.

[0005] In the typical GPS signal processing 20, an associated and dedicated memory unit is coupled to each functional unit stage. Thus, correlator signal processing unit 22 is typically coupled to an associated dedicated correlation processing memory unit 28 shown in FIG. 1. Coherent and non-coherent I & Q samples are stored in correlation processing memory 28 received from correlator signal processing unit 22. Tracking processing unit 24 is coupled to a tracking unit memory 30 to store the code, data, and parameters utilized by the tracking processor CPU for acquisition and tracking processing such as, for example, carrier loops, code loops, code lock detect, costas lock detect, bit synchronization, data demodulation. Navigation processing unit 26 is coupled to a navigation processing memory 32 for storing the code and data for the navigation processing CPU, such as calculation of position and time.

[0006] Thus, in operation, typical GPS receiver 10 requires significant hardware and memory to search, utilizing a large number of correlators and multiple frequency bins to implement. For example, an 8 frequency bin search should reduce the search time by a factor of 8 but it will require 4 times the memory to store the coherent integration samples and 8 times the memory to store the non-coherent integration samples. In order to achieve low cost, commercial GPS receiver architectures are deterred from using massively parallel architectures to avoid the cost of massively parallel implementation. There is therefore a need for a GPS signal processing architecture that minimizes the costly memory requirement and still achieves extremely fast signal acquisition.

[0007] A shared memory architecture for a GPS receiver is provided, wherein a processing memory is shared among the different processing functions, such as the correlator signal processing, tracking processing, and other applications processing. The shared memory architecture within the GPS receiver provides the memory necessary for signal processing operations, such as the massively parallel processing, while conserving memory cost by re-using that same memory for other GPS and non-GPS applications. The shared memory architecture for a GPS receiver provided in accordance with the principles of this invention thereby minimize the costly memory requirement often required of extremely fast signal acquisition of a GPS receiver.

[0017] FIG. 3 shows a shared memory architecture for a GPS receiver 100, wherein a signal processing memory 144 is shared among different signal processing functional units, such as a correlator signal processing unit 122, tracking processing unit 124 and applications processing unit 126. FIG. 4 shows a more detailed functional block diagram of processing memory 144 comprising an IQRAM 53 and an IQSQRAM 59. FIG. 4 further illustrates shared memory architecture in operation, as an illustration, such as during operations of channel correlator signal processing unit 122.

[0018] In operation, an IQ separator and down converter 46 samples a satellite IF signal 19 and separates signal 19 into a pair of I and Q signals 47. I and Q signal pair 47 is down converted to a baseband frequency before being provided to a Doppler rotator 48, which provides Doppler rotation of I and Q signal pair 47. Both carrier phase and carrier frequency are programmed in the Doppler rotator 48 by a tracking processing CPU of tracking processing unit 124 of FIG. 3. As shown in FIG. 4, correlator 50 receives the Doppler rotated I and Q signal pair 49 and correlates signal pair 49 with a replica I and Q code produced by a code generator 52. An IQ accumulator 54 receives both I and Q samples 64 from correlator 50 and accumulates the samples over a coherent integration period. The accumulated results are stored separately in an IQRAM 53. The multiple frequency bin correlator 56 then receives I and Q data provided from IQ accumulator 54 and performs an accumulation at IQSQ accumulator 58 on the results of the square root of the sum of I-squared plus Q-squared for a period of time specified as non-coherent integration. The accumulation results are then stored in an IQSQRAM memory 59 of processing memory 144.

[0019] FIGS. 5A and 5B further illustrate a more detailed block diagram of an IQRAM arbitration (FIG. 5A) and an IQSQRAM arbitration (FIG. 5B) provided to arbitrate use of IQRAM 53 and IQSQRAM 59. FIGS. 5A-5B illustrate the IQRAM and IQSQRAM arbitrator 60 and 62 that control access to shared memory IQRAM 53 and IQSQRAM 59, i.e., such as arbitrating memory use between channel correlator signal processing unit 122 and the other functions seeking access to memory 144. For the IQRAM arbitrator 60, the multiple memory access sources comprise the coherent integration of I and Q data from the output of coherent integration function 64 of correlator signal processing unit 122, the multipath/early—late processing 66 (i.e., for sampling data used for multipath mitigation by the tracking processor), the cache tag and data from the cache controller 68 (i.e., used to speed up memory accesses for all the signal processing, including tracking processing and navigation processing), and any application processing 126. In this example, during tracking, the IQRAM arbitrator 60 arbitrates the multiple sources seeking access to IQRAM 53. The IQSQRAM arbitrator 62 shown in FIG. 5B includes controlling access from the non-coherent integration of I and Q signals 74, access to parameters stored for the tracking loops 76, multiple frequency bin correlation 56 (FIG. 4), the convolution decoder 80 (used for a special differential GPS function), and any application processing functions 126. The arbitrator, such as the IQSQRAM arbitrator 62, arbitrates the multiple sources seeking access to the IQSQRAM 59.

[0020] FIG. 6 shows an example of the memory map 653 of the IQRAM 53 during our tracking operation example. There are three different address ranges for three types of memory sources: the coherent integration of I and Q data from the correlator outputs (multiple samples in acquisition mode, single sample in track/re-acquisition mode), the multipath/early-late sample data, and the cache tag/data. For this example, in satellite acquisition mode the whole address space of 0x000 though 0x1f7 is used to store the multiple sample (in this case four) coherent integrations needed to search multiple frequency bins simultaneously. In track, or reacquisition modes, however, only a single sample needs to be collected instead of four. Thus, in track/reacquisition modes, the coherent integration I and Q data is stored only in the address range from 0x000 to 0x077. This frees up the remaining space to be used for other functions. The multipath/early-late sampling data is stored in the address range from 0x080 to 0x0ff. The cache tag/data for tracking or navigation processing is stored in the range from 0x100 to 0x1ff. FIG. 9 shows a structure for a 2 way set associative cache implementation of processing memory 144. The cache can be used as the instruction and data cache for the tracking and navigation processing functions to speed them up. The memory region used as cache can alternatively be used as fast local RAM for data storage by the tracking processor or applications processor. Thus, same areas of the address map are shared by multiple functions, including other non-GPS applications, such as navigation processing, GPS location processing, wireless networking protocol processing, and other application processing that would be desirable to incorporate into GPS receiver 100.

[0021] FIG. 7 and FIG. 8 show the memory map 759 and 859 for IQSQRAM 59 for other GPS functions, such as acquisition (or re-acquisition). The memory requirements once again are different for acquisition mode and track/reacquisition modes. In acquisition mode, 1920 words in address range of 0x000 to 0x77f are used to store noncoherent accumulations. In track/reacquisition modes, however only 240 words stored in address range 0x000 to 0x0ef are needed to store the noncoherent accumulations. This frees up the remaining space for other functions. In this example the other functions include convolutional decoder parameters and data, and expanded tracking processor parameters and data.

[0022] FIGS. 7-8 illustrates sample memory mapping for memory IQSQRAM 59 during different modes. The memory mapping of IQRAM 53 and IQSQRAM 59 of processing memory 144 as illustrated in FIGS. 6-8 is a sample implementation. It is understood that this shared memory mapping in GPS receiver 100 can be extended to process other applications performed by the GPS receiver, such as navigation processing, GPS location processing, processing wireless networking protocols, to just name a few. It should be understood that the shared memory architecture, such as illustrated with reference to FIGS. 3-9 can be applied to other GPS receiver applications contemplated as being within a GPS receiver. The shared memory architecture within the GPS receiver provides the memory necessary for signal processing operations, such as the massively parallel processing, while conserving memory cost by re-using that same memory for other GPS and non-GPS applications. The shared memory architecture for a GPS receiver provided in accordance with the principles of this invention thereby minimize the costly memory requirement often required of extremely fast signal acquisition of a GPS receiver.

[0023] Foregoing described embodiments of the invention are provided as illustrations and descriptions. They are not intended to limit the invention to precise form described. In particular, Applicant(s) contemplate that functional implementation of invention described herein may be implemented equivalently in hardware, software, firmware, and/or other available functional components or building blocks. Other variations and embodiments are possible in light of above teachings, and it is thus intended that the scope of invention not be limited by this Detailed Description, but rather by claims following.