Method for transmitting data over a data bus with minimized digital inter-symbol interference

[0001] This application is a continuation of U.S. application Ser. No. 09/220,089, filed Dec. 23, 1998 now U.S. Pat. No. 6,577,687.

[0002] The invention relates generally to transmitting binary data over a data transmission line and more precisely to transmitting binary data over a data transmission line with minimized digital inter-symbol interference.

[0003] As illustrated in FIG. 1, data is typically transmitted back and forth between a host computer system 10 and peripheral devices, such as disk drive 5, tape drive 6, or printer 7, over a data bus 15. The data bus 15 couples the host computer system 10 and the peripheral devices together and enables the exchange of data between the system and the devices. One type of data bus is a Small Computer System Interconnect (SCSI) data bus. A SCSI data bus can be configured in different ways and has several modes of operation. One configuration and mode of operation is known as SCSI wide bus which includes a sixteen bit data bus with associated control signals such as Busy (BSY), Select (SEL), Control/Data (C/D), Input/Output (I/O), Message (MSG), Request (REQ), Acknowledge (ACK), Attention (ATN), and Reset (RST) The SCSI data bus 15 is connected to the host computer system 10 via a host adapter 12 and is connected to disk drive 5, tape drive 6, and printer 7 via disk controller 8, tape controller 9, and printer controller 11, respectively. The device controller is matched to the specific type of device connected to the SCSI bus as shown in FIG. 1. The data bus 15 may be configured to include a plurality of peripheral devices daisy chained together, where both the host computer system 10 and the last device connected to the data bus 15 (furthest from the host) are terminated with a bus terminator 16. The bus terminator 16 includes circuitry for regulating the maximum and the minimum voltage levels on the data bus 15.

[0004] Referring to FIGS. 2A and 2B, the maximum and minimum voltage thresholds for data detection (V-one and V-zero) are sensed by data detection circuitry 13. Each threshold is a fixed d.c. voltage level connected to a signal line of the data bus 15, which is driven by driver circuitry 14. This fixed d.c. threshold level is typically defined between the terminator voltage boundaries (+V-term and −V-term). Both the host adapter and the device controllers contain driver circuitry 14 for driving, and data detection circuitry 13 for receiving, the data and logic circuits (not shown in FIG. 2A) for directing data flow and processing operations.

[0005] When information is transferred between the host computer system and any one of the plurality of peripheral devices, a handshaking protocol is used to initiate data requests and acknowledge that such requests have been completed. A REQ control signal may be asserted by an initiating device to request that the target either write or read data to/from the initiating device. An ACK control signal may be asserted by the target device to acknowledge that the target device successfully sent or received data.

[0006] A problem can occur when the SCSI data bus idles with no data transfers for a prolonged period of time. In this instance the voltage level on the data bus will rise to the maximum voltage value defined by the bus terminators, called herein the “quiescent negated voltage level.” When a REQ is asserted, the REQ control circuitry provides a predetermined fixed window of time for the REQ to be sensed by the data detection circuitry before subsequent REQs are asserted. Since the bus voltage is at the quiescent negated voltage level during prolonged idles, the REQ must make a larger signal level swing than during synchronous operation in order to reach a level capable of being sensed as a REQ by the data detection circuitry. In one failure mode, there is insufficient time for the REQ signal to be sensed by the data detection circuitry during a first assertion of REQ before a subsequent REQ is asserted. Consequently, REQ data transmitted on other lines of the data bus during the first REQ pulse may not be sensed correctly by the data detection circuitry and may be lost. A second failure mode occurs when the REQ signal is not sensed at all by the data detection circuit within predetermined time constraints. These failure modes are hereby defined as digital control inter-symbol interference, i.e., “control ISI.”

[0007] The above described problems which can occur during the first REQ assertion are not relevant to subsequent REQs because the data bus voltage level is no longer at the quiescent negated voltage level and thus subsequently transmitted REQs do not require as large a voltage swing before being sensed by the data detection circuitry.

[0008] Referring to FIG. 3, a similar problem occurs when the user data signal is unchanged (all zeros or ones) for a prolonged period of time. A prolonged unchanged user data signal allows the user data voltage level to approach the quiescent negated voltage level. Subsequent transitions in the user data signal from the quiescent negated voltage level require a large voltage swing in the data signal in order to be sensed by the data detection circuitry. Again, there is a fixed period of time for these data signal transitions to be sensed by the data detection circuitry before another signal transition is asserted. However, this period of time is often insufficient for the first data signal transition to be sensed by the data detection circuitry, thereby causing the data defined within this first large data signal transition to be lost. This loss of user data occurring within the first user data transition is hereby defined as digital data inter-symbol interference (“data ISI”).

[0009] In transmitting data over a data bus, the trend is to increase the frequency at which information can be transferred over the data bus. However, an increase in data frequency causes a proportional decrease in the time period allowable for control and data pulses to be sensed by the data detection circuitry. Therefore, as data transmission frequencies are increased, there is a corresponding increase in both control ISI as well as data ISI as defined above. Minimizing both control and data ISI is thus highly desirable.

[0010] An object of the present invention is to transmit data over a data bus with minimized digital control inter-symbol interference.

[0011] Another object of the present invention is to transmit data over a data bus with minimized digital data inter-symbol interference.

[0012] A first embodiment of the present invention comprises a method for transmitting data from a sending device (sender) to a receiving device (receiver) via a data bus in a manner to minimize control and data inter-symbol interference. The method comprises the steps of executing a start data transfer command, waiting for a FIFO register to contain data, the FIFO register being coupled to a peripheral device, determining when the FIFO register is holding the data, driving the data held in the FIFO register onto the data bus, inverting the data previously driven onto the data bus to reduce the quiescent negated voltage level of the data bus, driving the inverted data onto the data bus, pausing for a predetermined period of time (t3), driving true data onto the data bus, pausing for a predetermined period of time (t1), asserting a REQ control signal, and pausing a predetermined period of time, (t2), for the data to be sensed by the data detection circuitry. The step of pausing for the predetermined period of time, t2, provides the data detection circuitry additional time to sense the data being transmitted on the data bus, thereby minimizing digital control inter-symbol interference during data transmission from the sender to the receiver.

[0013] This method transmits data over the data bus with minimized digital control and data inter-symbol interference because the voltage level on the data bus is not permitted to reach the quiescent negated voltage level (the bus terminator voltage level) before a transition occurs. Even after a prolonged period of time where data signals transmitted over the data bus have remained constant, an abrupt transition is not subjected to the lengthy transition necessitated by the bus floating at the quiescent negated voltage level. Moreover, additional time is provided for the first REQ pulse to be detected before subsequent REQ pulses are asserted. Accordingly, the first level transition occurring after the prolonged unchanged data transmission level is detected by the data detection circuitry within predefined data detection circuitry time constraints.

[0014] These and other objects, advantages, aspects and features of the present invention will be more fully understood and appreciated upon consideration of the following detailed description of a preferred embodiment, presented in conjunction with the accompanying drawings.

[0024] Referring again to FIG. 1, generally, the present invention comprises a method for bi-directionally transmitting data from a sender to a receiver via a data bus 15. In one instance, the sender is defined as a host computer system 10 and the receiver is defined as a peripheral device such as the disk drive 5 for transmitting data from the host computer system 10 to the disk drive 5. Alternatively, the sender is defined as a peripheral device such as the disk drive 5 and the receiver is defined as the host computer system 10 for transmitting data from the disk drive 5 to the host computer system 10.

[0025] One preferred embodiment of the present invention as set forth herein is a method for transmitting data from the disk drive 5 to the host computer system 10 via the data bus 15, such as a SCSI data bus, with minimized digital inter-symbol interference. Referring to FIG. 4, the method comprises the steps of executing a start data transfer command at step 20 from the disk drive 5 to the requesting host computer system 10. The disk drive 5 waits for a FIFO register (not shown) to be holding data at step 30. The FIFO register is physically associated or positioned with the disk drive 5. Once data is detected as being held in the FIFO register at step 40, the data held in the FIFO register is driven onto the data bus 15 at step 50. At step 60 the operation pauses for a first predetermined period of time, t1, for the data to be set-up on the data bus 15, whereby a subsequent assertion of a REQ command at step 70 transfers data from the sender to the receiver. The first predetermined period of time typically ranges from approximately 12.5 nano-seconds to 25 nano-seconds.

[0026] Since the REQ command has been asserted after a period of no data transmissions, the next step is to pause for a second predetermined period of time, t2 at step 80, so that the REQ pulse transition can be sensed by the data detection circuitry 13 and data associated therewith reliably sampled. The second predetermined period of time typically ranges from approximately 25 nano-seconds to 50 nano-seconds. As illustrated in FIG. 5 this second period of time, t2, is substantially longer in duration than typical pauses that are interleaved between subsequent synchronous data transmissions, e.g. t1. The period of time, t2, is substantially longer in order to provide the data detection circuitry 13 additional time to sense the first REQ data signal transition and to accurately sample the REQ data transferred over the data bus 15. In this manner, data transmission over the data bus 15 is accomplished with minimized digital control inter-symbol interference. After the first REQ data signal transition has been sensed, the voltage level of the REQ data signal will be lower than the quiescent negated voltage level and thus additional time is not necessary for subsequent REQ data to be sensed.

[0027] Referring to FIGS. 6 and 7, another preferred embodiment of the present invention adds additional steps to the FIG. 4 flow chart and further comprises loading a data ISI counter at step 72 after asserting a REQ in step 70. The data ISI counter counts the number of data segments transmitted over the data bus 15. After a predetermined number of data ISI counter count cycles and if there is still data to be transferred, the process steps restart at step 30.

[0028] The method steps of this embodiment further include the steps of inverting and driving the data onto the data bus 15 at step 52, that had been previously driven onto the data bus 15 in step 50. Then the process is paused for a third predetermined period of time, t3 at step 54 to insure that the data bus 15 voltage level does not reach the quiescent negated voltage level during subsequent steps of driving true data onto the data bus 15 at step 56. The third predetermined period of time typically ranges from approximately 12.5 nano-seconds to 25 nano-seconds. Moreover, during subsequent steps of driving true data onto the data bus 15 at step 56, the data bus voltage does not reach the quiescent negated voltage level for a predetermined period of time as defined by the data ISI counter in step 72. This reduction in the quiescent negated voltage level of the data bus 15, achieved at steps 52-56, enables subsequent data segments transmitted over the data bus 15 to be sensed faster by the data detection circuitry 13. The subsequent data segments are detected faster because the voltage level on the data bus 15 is lower than the quiescent negated voltage level as shown in FIG. 7. Therefore, subsequent data segment transitions comprise smaller voltage swings before being detected by the data detection circuitry 13. These smaller voltage swings made by data transitions are more likely to be detected within time constraints of the data detection circuitry 13 than data transitions that make larger voltage swings.

[0029] The subsequent data segments transmitted over the data bus 15 follow the method steps of: deasserting the REQ drive command at step 100 and then determining if the FIFO register is holding data at step 110. If the FIFO register is still holding data, then driving the data held in the FIFO register onto the data bus 15 at step 105, and then pausing for a predetermined period of time, t1 at step 61, for data to be set up on the data bus 15, i.e., set up time.

[0030] Thereafter, the REQ pulse is asserted at step 130 by the disk drive 5 for transferring a data segment in response to a data request by the host computer system 10 for the next data segment. Accordingly, the data is transmitted from the disk drive 5 to the host computer system 10 over the data bus 15. Then the step of pausing for a period of time, t1 at step 62, is carried out so that data held on the data bus 15 can be sensed by the data detection circuitry 13, i.e., hold time. In one preferred implementation, the set up time equals the hold time, however equality is not required. Next, the REQ drive command is deasserted at step 140. Then, the data ISI counter is decremented at step 150 and the data ISI counter is checked at step 160 to determine if the counter has reached zero. The FIFO register is again checked at step 110 to determine whether the FIFO register is holding data.

[0031] Further, if the FIFO register is again determined to be holding data at step 110, then the method steps 105, 61, 130, 62, 140, 150, and 160 described above are repeated, if the data ISI counter is not zero at step 160 and the FIFO register is still holding data at step 110, then these steps 105, 61, 130, 62, 140, 150, and 160 described above are cyclically repeated until the FIFO register is determined not be holding data at step 110 or the data ISI counter is equal to zero as determined at step 160.

[0032] Conversely, if it is determined that the FIFO register is not holding data at step 110, then it is determined if the last data segment has been transferred at step 170. If the last data segment has been transferred, then the data transfer method ends at step 180. If, however, the last data segment has not been transferred, then the data transfer method again waits for the FIFO register to be holding data at step 30 and repeats the FIG. 6 steps for transferring data over the data bus 15.

[0033] Additionally, if the data ISI counter is equal to zero as determined at step 160, then it is again determined if the last data segment has been transferred at step 170. If the last data segment has been transferred, then the data transfer method ends at step 180. If, however, the last data segment has not been transferred, then the data transfer method again waits for the FIFO register to be holding data at step 30 and repeats the FIG. 6 steps for transferring data over the data bus 15, until all of the data has been transferred.

[0034] It is important to note that the pause for a period of time, t2 at step 80, is longer in duration than the pause for a period of time, t1 at step 60. The pause period, t2 at step 80, is asserted for the initial data segment transferred over the data bus 15 as illustrated in FIG. 5. Additionally, the pause period, t2 at step 80, is also asserted when data transfers over the data bus 15 are paused for any reason or if the data ISI counter equals zero at step 160. In summary, the pause period, t2 at step 80, is asserted during initial start data transfers at step 20; when the data transfers are paused for any reason; or when the data ISI counter equals zero at step 160. The pause period, t1 at step 60, is asserted during synchronous data segment transfers.

[0035] The data ISI counter (not shown) is a programmable register that may be programmed to count data segments over a range of approximately 1 to 31 counter count cycles. Each count cycle represents a data segment transmitted over the data bus 15. Thus, once the data ISI counter has decremented to zero, the above described method steps are again restarted at the steps of determining if the last data segment has been transferred at step 170 and if so then ending at step 180 and if not then waiting for the FIFO register to be holding data at step 30 and restarting the data transfer process.

[0036] This restart of the data transfer process causes the data lines of the data bus 15 to be cleared of digital control/data inter-symbol interference after a predetermined number of counter count cycles in accordance with the preprogrammed data ISI counter value. Likewise, a restart occurs if the FIFO register is determined to be no longer holding data in step 10 and if it is determined in step 170 that the last data segment has not been sent. Therefore, if either the data ISI counter has reached zero in step 160 or if the last data segment has not been sent in step 170, then the method for transferring data over the data bus 15 restarts at the step of waiting for the FIFO register to be holding data at step 30.

[0037] Referring again to FIG. 1, another aspect of the invention includes the step of individually monitoring each data line of the data bus 15 with a 16-bit data activity detector 17. The data activity detector 17 is connected to each of the data lines defined within the data bus 15. When a monitored line is inactive for a period of time, the FIG. 6 method steps are repeated for each individual data line of the data bus 15.

[0038] Referring to FIGS. 1-7, a method for transmitting data from the host computer system 10 to a peripheral device via the data bus 15 comprises the method steps of replacing the REQ command with an ACK command and repeating the method steps described above.

[0039] The above described method for transmitting data over a data bus has many advantages over the prior art, such as, starting data transfers on a data bus, after the data bus has been at idle for a prolonged period of time, with minimized inter-symbol interference.

[0040] Another advantage of the above described method for transmitting data over a multi-line data bus is directed to synchronously transmitting data over the data bus with minimized digital data inter-symbol interference even though any one of the data lines has remained in an unchanged state for a prolonged period of time.

[0041] The data transfer rate, according to principle of the present invention, can be increased because the data bus need not compensate for digital control inter-symbol interference realized after restarting the data bus after prolonged periods of time at idle. Moreover, the data transfer rate of the data bus can be increased because the data bus need not compensate for digital data inter-symbol interference realized after prolonged synchronous data transfers of unchanged data values.

[0042] Having thus described an embodiment of the invention, it will now be appreciated that the objects of the invention have been fully achieved, and it will be understood by those skilled in the art that many changes in construction and widely differing embodiments and applications of the invention will suggest themselves without departing from the spirit and scope of the invention. The disclosure and the description herein are purely illustrative and are not intended to be in any sense limiting.