Gain control circuitry for delay locked loop circuit

[0001] This application is a continuation in part of U.S. patent application Ser. No. 10/376,817 entitled “SYSTEM FOR PHASE LOCKED LOOP OPERATION AND METHOD THEREOF” by Abbasi et al. filed on Feb. 28, 2003, whose disclosure is incorporated herein by reference.

[0002] This application is related to U.S. Pat. No. 6,411,142 entitled “COMMON BIAS AND DIFFERENTIAL STRUCTURE BASED DLL WITH FAST LOCKUP CIRCUIT AND CURRENT RANGE CALIBATION FOR PROCESS VARIATION” issued Jun. 25, 2002.

[0003] This application is related to U.S. patent application Ser. No. 09/730,954 entitled “COMMON BIAS AND DIFFERENTIAL STRUCTURE BASED PLL WITH FAST LOCKUP CIRCUIT AND CURRENT RANGE CALIBRATION FOR PROCESS VARIATION” filed on Dec. 6, 2000 (now U.S. Pat. No. 6,646,512 issued Nov. 11, 2003).

[0004] The present disclosure relates generally to delay locked loop (DLL) circuits. More particularly, this disclosure relates to a DLL circuit which is based on a variable length plurality of differential delay elements, an advanced common biasing technique which tolerates process variations and calibrates current ranges for operational variances and lock detection for faster processing.

[0005] Delay-locked loops are often used in the I/O interfaces of digital integrated circuits in order to hide clock distribution delays and to improve overall system timing. In recent years, the demand has risen for devices capable of high-speed processing. As a result, the demand for DLL circuits that quickly compensate for electronic noise and capacitive delays has also risen.

[0006] One type of design used by those skilled in the art to minimize the noise present in the circuit at the required speed is a self-bias signal technique. Referring to FIG. 1, this prior art DLL circuit is a self-biasing configuration that is composed of a phase comparator, charge pump, loop filter, bias generator and a plurality of delay cells. In this configuration, devices dependent on a precisely delayed clock signal must delay processing for a standardized time period to insure that the received signal is exact. This processing delay is caused by the fact that most DLL circuits are designed to tolerate the worst-case conditions. The DLL circuit performance during this worst-case condition is the processing delay time set for most devices using the output of this circuit.

[0007] This prior art design uses a constant charge pump current which gives rise to a constant damping factor and a constant loop bandwidth. A constant bandwidth can constrain the achievement of a wide operating frequency range and low input tracking jitter. If the frequency is disturbed, the phase error that results from each cycle of the disturbance will accumulate for many cycles until the loop can compensate for the phase error. The error will be accumulated for a number of cycles, which is proportional to the operating frequency divided by the loop bandwidth. Thus the loop bandwidth would have to be positioned as close as possible to the reference frequency bandwidth to minimize the total phase error. The result is that the frequency bandwidth must be conservatively set for stability at the lowest operating frequency with worst case process variations rather than set for optimized jitter performance. The self-biased DLL also exhibits much faster locking times only when locking from similar or higher operating frequencies. However, if the self-biased DLL is started at a very low operating frequency, it will exhibit very slow locking times.

[0008] Accordingly, there is a need for a DLL circuit which provides a fast lock-up circuit, has better jitter performance, tolerates process variations, reduces power consumption, reduces processing delay time and extends the DLL operating frequency range.

[0021] The use of the same reference symbols in different drawings indicates similar or identical items.

[0022] The first embodiment of the present disclosure will be described with reference to the drawing figures wherein like numerals represent like elements throughout.

[0023] Referring to FIG. 2, a DLL circuit 10 made in accordance with an embodiment of the present disclosure is shown. The DLL circuit 10 includes a phase frequency detector (PFD) 11, a lock circuit 12, a charge pump 13, a charge pump control circuit 14, a loop filter 15 including a capacator C1 (not shown), a common bias generator 16, a current range control circuit 17, a delay cell switching circuit 21 and a plurality of delay cells 20_a . . . 20_n. The PFD 11 receives a reference signal F_ref from an outside source, a reset signal DLL_reset and the DLL output signal F₀. Coupled to the PFD 11 are the lock circuit 12 and the charge pump 13. As those skilled in the art should know, the PFD 11 determines the phase difference between the reference signal F_ref and the DLL 10 output signal F₀. If the PFD 11 detects a phase difference between the two input signals F_ref, F₀, the phase error signals U, D are sent to the lock circuit 12 and the charge pump 13. The duration (pulse width) of these output signals U, D depends on the amount of phase error that is detected by the PFD 11.

[0024] The lock circuit 12, shown in FIG. 3A, is controlled by the phase error signals U, D output from the PFD 11. Coupled to the PFD 11 and the current range control circuit 17, the lock circuit 12 monitors the crossing of the phase of the DLL output signal F₀ and the phase of the reference signal F_ref, as will be disclosed hereinafter. The lock circuit 12 comprises a plurality of invertors 3, a plurality of AND gates 5, two S-R flip flops 7 and a delay 9. When the lock circuit 12 detects the crossing of the phase of the two signals F₀, F_ref, the lock circuit 12 provides an output Q₃ to the current range control circuit 17 to remain at the present bias current level. The output Q₃ of the lock circuit 12, as the DLL circuit 10 attempts to match the phase of the output signal F₀ with the phase of the reference signal F_ref, is illustrated in the logic table of FIG. 3C.

[0025] Referring to FIGS. 3B and 3C, as the DLL circuit 10 comes out of reset, the error signals U, D are in the neutral state 0, 0. Since the output frequency F₀ is out of phase with the reference frequency F_ref, the error signals U, D go to a state 0, 1 indicating that the loop filter 15 capacitor C1 must be charged. On the subsequent rising edge of the reference frequency F_ref, the error signals U, D go to a state 1, 1. This state causes the PFD 11 to reset and return the error signals U, D to their neutral state 0, 0. This process continues until the phase of the output frequency F₀ passes the phase of the reference frequency F_ref which is indicated by the error signals U, D going to a state 1, 0. This condition will signal the lock circuit 12 to output a logical one (1) to the current range control circuit 17, indicating that the current range control circuit 17 should maintain the bias current at the present level which will be described in greater detail hereinafter.

[0026] The lock circuit 12 operates to quickly detect the matching of the phases of reference signal F_ref and output signal F₀. Once this condition is detected, the lock circuit 12 provides the output signal Q₃ to the current range control circuit 17 to remain at the present bias current level, the optimal bias current I_bias (shown in FIG. 4A) to be output to the plurality of delay cells 20_a . . . 20_n. This lock circuit 12 provides fast signal lock detection so that devices using the DLL 10 output signal F₀ do not have to delay processing for a longer period of time than necessary, resulting in faster device processing time.

[0027] Referring back to FIG. 2, the error signals U, D from the PFD 11 are also forwarded to the charge pump 13. The charge pump 13 outputs a charge current that charges or discharges the capacitor C1 of the loop filter 15 to a voltage level V_lpf. The charge pump 13 receives the error signals U, D, a bias voltage input V_bp from the common bias generator 16, and the logic signals S1, S2, S3 from the charge pump control circuit 14, as will be described in greater detail hereinafter. V_bp is a reference bias voltage which controls the charge pump 13 output current. It is well known to those skilled in the art that the charging and discharging of the loop filter 15 capacitor C1 creates a voltage change V_lpf across the loop filter 15. As the voltage V_lpf increases, the charge pump 13 output current decreases. This voltage change V_lpf is a reference for the common bias generator 16 and the current range control circuit 17 to generate the reference signals which control the amount of delay generated by each delay element 20_a . . . 20_n.

[0028] The logic signals S1, S2, S3 received by the charge pump 13 from the charge pump control circuit 14 are equivalent to 1, 1, 1, respectively. This output allows the charge pump 13 to output a maximum charge current, causing the DLL 10 to have a high frequency response to the error signals U, D. However, when the DLL circuit 10 receives a high frequency reference signal, such as greater than 300 MHz, the charge pump control circuit 14 receives a logic one (1) signal from H-F_ref, which detects the existence of this high frequency reference signal. The charge pump control circuit 14 converts a charge control signal CC_signal and adjusts the outputs of the three logic signals S1, S2, S3, which in turn adjusts the amount of charge current output by the charge pump 13. When H-F_ref equals logic one (1), the signals S1, S2, S3 output from the charge pump control circuit 14 may be equivalent to 1, 1, 0 or 1, 0, 1, respectively, for example. The charge control signal CC_signal is an outside input signal whose value depends on the device or process for which the DLL 10 output F₀ is to be used. The charge pump control circuit 14 converts the charge control signal CC_signal to the logic signals S1, S2, S3. This instructs the charge pump 13 to switch out an internal current source (not shown) when the logic signal S1, S2, or S3 associated with the current source is zero (0), thereby dividing the current of the charge pump 13 by a number m (e.g., 3, 6, or 9). The use of the charge pump control circuit 14 when a high frequency input signal is detected provides a reduced frequency response to the error signals U, D as the phase of the output signal F₀ is adjusted to match the phase of the input signal F_ref, providing better jitter performance.

[0029] The loop filter 15, which comprises a capacitor C1, is coupled to the current range control circuit 17, the common bias generator 16, and the charge pump 13. This loop filter 15 receives a charge current generated by the charge pump 13 and an outside input voltage V_dd. As a result of the charging or discharging of the capacitor C1, a voltage V_lpf is created and output to the current range control circuit 17 and the common bias generator 16.

[0030] The current range control circuit 17, coupled to the output of the loop filter 15 and the lock circuit 12, the delay cell switching circuit 21 and the common bias generator 16, comprises two voltage comparators (not shown) and two (2) single bit outputs R0, R1. The current range control circuit 17 receives the loop filter 15 output voltage V_lpf and adjusts the level of the bias current I_bias generated in the common bias generator 16, through the output leads R0, R1. The voltage comparators in the current range control circuit 17 monitor the voltage V_lpf against an internal reference voltage V_ref which is indicative of the point where a small change in the voltage V_lpf causes a large change in the bias current I_bias. The reference voltage V_ref, which can be fixed or variable, is illustrated in the I_bias I-V curves 60-66 of FIG. 5. As those skilled in the art should know, each of these curves 60-66 include a nonlinear region where a small increase in the voltage creates a large decrease in the current. This nonlinear region creates a large change in the delay elements 20_a . . . 20_n, causing increased jitter within the DLL circuit 10. If the DLL circuit 10 is operated past a certain voltage point V_ref on the curves and into the nonlinear region, the amount of jitter will increase and the overall performance of the DLL circuit 10 will decrease. Therefore, when the voltage V_lpf is greater than the reference voltage V_ref, the PFD 11, bias generator 16 and lock circuit 12 receive a local reset signal Cal_reset from the current range control circuit 17 which resets the voltage V_lpf to zero (0). The current range control circuit 17 outputs R0, R1 switch states, adjusting the bias current I_bias to a lower level.

[0031] Initially, when the DLL circuit 10 is reset, the current range control circuit 17 receives a logic zero (0) signal from the lock circuit 12 and signals the bias generator 16 to switch on all four current sources I₁, I₂, I₃, I₄, which is indicated by the output 0, 0 for the two output leads R0, R1, respectively. The current range control circuit 17 also resets a delay cell signal DC at the input of a delay cell switching circuit 21, which sets the number of delay cells to the lowest delay level. When the lock circuit 12 detects the crossing of the phase of the reference and output signals F_ref, F₀, the current control circuit 17 is signaled to lock the common bias generator 16 at the present bias current level, which is the optimal bias current curve for the DLL circuit 10 performance. As disclosed above, when the voltage comparators in the current range control circuit 17 detect that the V_lpf is too high, the current range control circuit 17 output leads R0, R1 switch by one (1). For example, after the resetting of the DLL circuit 10, the output leads R0, R1 are equivalent to 0, 0. When the comparator detects the high voltage V_lpf, the output leads R0, R1 switch to 0, 1, respectively, which indicates that the common bias generator 16 should switch off current source I₄. The current range control circuit 17 also outputs an internal reset signal Cal_reset to the PFD 11, the lock circuit 12, and the bias generator 16 which resets the voltage V_lpf to zero (0). Each time the voltage comparators of the current range control circuit 17 detect this condition, the output leads R0, R1 increase by one (1) and another current source (for example 13) is switched off. This process continues until the output leads R0, R1 are equivalent to 1, 1, where the only remaining current source is I₁. At this point, the current range control circuit 17 outputs a logic one (1) delay cell signal DC to the delay cell switching circuit 21, indicating that the maximum number of delay cells 20_a . . . 20_n should be used. The reset signal Cal_reset is also output, thereby resetting the aforementioned components and the output leads R₀, R₁. The current range control circuit 17 again steps through the process described above. Once the current range control circuit 17 reaches the lowest bias current level for the second time, the common bias generator 16 is signaled to lock at the lowest bias current level I₁.

[0032] If the reference voltage V_ref is greater than the loop filter 15 voltage V_lpf and the lock circuit output is a logic one (1), the current range control circuit 17 remains at the present bias current level, which is considered the optimal operating point for the process utilizing the DLL 10 output signal Fo. As those skilled in the art should know, even though the current range control circuit 17 is illustrated utilizing two (2) single bit outputs R0, R1, a single two bit output may also be utilized. It should also be obvious to those skilled in the art that even though the current disclosure only utilizes four (4) bias current levels, the current range control circuit 17 can be designed to provide for more or less levels of current control.

[0033] Referring to FIG. 4B, the delay cell 20_a . . . 20_n, with a single differential amplifier representing a single differential delay element is shown. The number of delay cells 20_a . . . 20_n utilized by the DLL 10 is determined by the delay cell switching circuit 21. When the DLL 10 is reset, the current range control circuit 17 sends a logic zero (0) delay cell signal DC to the delay cell switching circuit 21, resetting it to the lowest delay cell count. For purposes of the preferred embodiment of the present disclosure, the lowest delay cell count is six (6). When the control circuit 17 sends a logic one (1) delay cell signal DC, the delay cell switching circuit 21 increases the number of delay cells used by the DLL 10 to its maximum count; which for purposes of the present disclosure is twenty 20 delay cells. The minimum and maximum delay cell counts may be changed depending on the device and process. Additionally, even though the present disclosure has only two levels of delay cell counts, minimum and maximum, the switching circuit 21 may provide for more levels.

[0034] Since each of the delay elements 20_a . . . 20_n draw transient power, the reduced delay cell count allows the DLL 10 to consume less power because fewer delay cells are used. The delay cell switching circuit 21 coupled to the current range control circuit 17 provides the DLL circuit 10 with more flexibility and faster locking times.

[0035] Referring to FIG. 4A, the present disclosure utilizes a single common bias generator 16, comprising a bias current generator 56, a bias voltage generator 58 and a differential amplifier 54. The differential amplifier 54 reduces the noise from the power supply. The differential amplifier provides improved power supply rejection ratio performance. The bias current generator 56 includes four symmetric loads 70, 72, 74, 76 and a switching circuit 57. Each of the symmetric loads 70, 72, 74, 76, which may or may not have the same device width, has as its voltage source V_dd and the low pass filter output signal V_lpf as its control voltage. The four symmetric loads 70, 72, 74, 76 act as current sources I₁, I₂, I₃, I₄. These current sources I₁, I₂, I₃, I₄ are switched on and off by the switching circuit 57. The outputs R0, R1 from the current range control circuit 17 dictate to the switching circuit 57 which of the current sources should be on and which should be off. As should be known to those skilled in the art, there are numerous switching circuits that are responsive to a digital input and can be used as described herein. In this manner, the current range control circuit 17 provides four discrete levels of bias current I_bias. This allows for better control of the DLL circuit 10 by providing the flexibility of varying the current slope without having to vary the delay cell itself. The bias current I_bias is output from the bias current generator 56 to the bias voltage generator 58.

[0036] The bias voltage generator 58 comprises two n channel transistors 51, 52 and one p channel transistor 53. The gate voltage of the n channel transistors 51, 52 is connected to the output of the differential amplifier 54. This differential amplifier 54 works to eliminate the noise generated by power supply voltage V_dd. The n channel transistors 51, 52 are configured such that the bias current I_bias through transistor 51 is mirrored onto transistor 52 and reflected up to transistor 53. When the bias current I_bias is mirrored in this way, two reference voltages are created. The two reference voltages are the bias voltages V_bn and V_bp, which determine the amount of delay for each delay element 20_a . . . 20_n. This configuration also provides the bias current I_bias from the common bias generator 16 to each delay element 20_a . . . 20_n. Using this common bias generator 16 and a selectable number of delay cells 20_a . . . 20_n will provide better linearity in the overall delay of the DLL circuit 10.

[0037] Referring still to FIG. 4A, each delay cell 20_a . . . 20_n contains two p channel transistors 21 and 22 and three n channel transistors 23, 24, 25. Transistors 23, 24 act as switches in the delay cell 20_a and determine the actual delay for each element based on the bias current I_bias via the voltages V_bn and V_bp. The p channel transistors 21, 22 act as current sources for the transistors 23, 24. Transistor 25 acts as a current source as well. The p channel transistors 21 and 22 are biased by the voltage V_bp. Since the amount of bias current I_bias determines the voltage V_bp, the delay time changes with V_bp. Transistors 23 and 24 receive a voltage input V⁺, and V⁻. The delay elements 20_a . . . 20_n are configured in such a way that the voltage inputs V⁺, V⁻ of the delay elements come from the voltage outputs V₀⁺, V₀⁻ of the preceding delay elements. The voltage outputs V₀⁺, V₀⁻ from the last delay element 20_n are coupled to a differential amplifier 22.

[0038] The current supplied by transistor 22 does not pass through transistor 24 when transistor 24 is “off” (or not conducting). Likewise, when transistor 23 is not conducting, the current provided by transistor 21 does not pass through transistor 23. There are parasitic capacitances at the inputs of transistors 23 and 24 that charge and discharge to affect the voltages V⁺ and V⁻, which rise and fall. When transistors 23 and 24 are on and off, respectively, the charge on the parasitic capacitors at the input of transistors 23 and 24 on the subsequent delay cell will be affected. When transistor 23 is turned on, it discharges the parasitic capacitances of the next delay cell and V₀⁻ changes from (V_dd−V_ds21) to (0V+V_ds23+V_ds25). Likewise, when transistor 24 is off, transistor 22 charges the capacitance of the following delay cell and V₀⁺ changes from (0V+V_ds24+V_ds25) to (V_dd−V_ds22), the drain to source voltage of transistor 22 at saturation. As is well known to those skilled in the art, the delay provided by the delay cell is equivalent to the duration between turning on transistor 23 and turning off transistor 24, and when the voltages V⁺ and V⁻ are equal. When this point is reached, the transistors in the next delay cell are activated. V₀+ and V₀⁻ are the output voltages of each delay cell that provide the input voltages V⁺, V⁻ to the next delay cell.

[0039] The flow diagram in accordance with present disclosure is illustrated in FIG. 6. The DLL circuit 10 receives a reset signal DLL_reset from an external source and resets all DLL 10 circuit components (step 700). If the reference signal is a high frequency reference signal, the H-F_ref signal goes high, activating the charge pump control circuit 14. The charge pump control circuit 14 then outputs logic signals S1, S2, S3 to the charge pump 13 to adjust the current in the charge pump 13, in accordance with the charge control signal CC_signal (step 700a). The PFD 11 resets the error signals U, D (step 701). The current range control circuit 17 receives the reset signal DLL_reset from the outside source and sets the bias current level of the common bias generator 16 to the maximum (I₁+I₂+I₃+I₄) and sets the delay cell count to its minimum (step 701a). The charge pump 13 outputs the appropriate charge current (step 703), generating a DLL circuit 10 delayed output signal F₀. The delayed output signal F₀ is then output to the PFD 11 to be compared to the reference signal F_ref (step 704). If F₀ is in phase with F_ref the lock circuit 12 signals the current range control circuit 17 to lock at the present current level (step 705). Once the bias current level I_bias is locked, the DLL circuit 10 is in lock range position (step 706) and the procedure terminates.

[0040] If the two signals F_ref, F₀ are out of phase, the PFD 11 outputs the error signals U, D, whose duration depend on the amount of phase error that is detected between the two signals F_ref, F₀ (step 707). The charge pump 13 receives the error signals U, D from the PFD 11 and the logic signals S1, S2, S3 from the charge pump control circuit 14 and outputs a current, commensurate with those signals, which sources or sinks the loop filter 15 capacitor C1 (step 708). As a result of the charging or discharging of the loop filter 15 capacitor C1, the control voltage V_lpf is generated (step 709). If the loop filter 15 voltage V_lpf is greater than V_ref and the current range control circuit 17 is not in the minimum range with the delay cell signal DC equal to one (1), the current range control circuit 17 outputs a local reset signal Cal_reset, which resets the voltage V_lpf to zero (0) (step 709a). The current range control circuit 17 outputs R0, R1 then switch to the next lowest level (step 709b).

[0041] If the current range control circuit 17 is at the minimum current level (i.e., R0, R1 is equal to 1,1) and the delay cell signal DC is equal to one (1), the common bias generator 16 outputs the bias current I_bias and bias voltages V_bp, V_bn to the plurality of delay cells 20_a . . . 20_n (step 711), which generates the DLL circuit 10 output signal F₀ (step 704).

[0042] If the delay cell signal is equal to zero (0) when the current range control circuit 17 is at the minimum current level (i.e., R0, R1 is equal to 1,1), the current range control circuit 17 signals the switching circuit 21 to use the maximum number of delay cells (step 712) (DC=1) and outputs the internal reset signal Cal_reset (712a). When the delay cell signal DC switches from zero (0) to one (1), the process is started again (step 702).

[0043] This design of the DLL circuit 10, in accordance with the preferred embodiment, will achieve a wide operating frequency range with a short lock in time and good jitter performance over a wide power supply voltage range. The differential DLL, operating in the biasing current mode, provides a much wider operating frequency range with high common-mode noise immunity. The common biasing technique provides the necessary bias with less sensitivity to temperature and process variations. It also provides better power supply rejection ratio and current range calibration regulation when the power supply droops or when process variations change.

[0044] Referring now to FIG. 7, a block diagram of a bias generator is shown and referenced generally as bias generator 100, in accordance with one embodiment of the present disclosure. Bias generator 100 includes loads 91-96, switches 81-86, transistors 88, 97, and 98, differential amplifier 87, and gain control circuit 99.

[0045] Bias generator 100 operates similar to the bias generator 16 of FIG. 4A. However, wherein the bias currents of the various current levels of the bias generator 16 were set to go to zero, the bias currents of most of the current levels of bias generator 100 are designed to remain within set current limits. Each of the current levels of bias generator 100 allows a smaller range of currents than current levels of bias generator 16. Accordingly, each of the current levels of bias generator 100 have smaller values of gain factors (K_VCDL) than current levels of bias generator 16, when using low source voltages, such as V_DD near one volt. The gain factor K_VCDL represents the resulting conversion factor of the delay element control circuit, such as delay cell switching circuit 21 and delay cells 20_a . . . 20_n. Lower K_VCDL values leads to lower jitter and better control over feedback stability, resulting in an increase in the range of operational frequencies. In combination with the current range control circuit 17, the gain control circuit 99 allows a DLL to operate over a much larger range of frequencies than a similar DLL without circuits 17 and 99.

[0046] It should be appreciated that the value of K_VCDL in a particular current level can be calculated and calculations of K_VCDL are known in the art. For example, the representation of K_VCDL as described in one embodiment of the present disclosure is based on the following equation, referenced as Equation 1. $\begin{array}{cc}\mathrm{Kvcdl}=\frac{d}{d{V}_{\mathrm{LPF}}}\left(N\frac{\left(V_H-V_L\right)-V_d}{2}·\frac{C_L}{g_{\mathrm{FIXED}}+g_{\mathrm{DYNAMIC}}}\right)& \left(\mathrm{Equation}1\right)\end{array}$

[0047] In Equation 1, g_FIXED and g_DYNAMIC refer to the CMOS channel conductance of the fixed current sources (connected to V_REF) and of the dynamic current sources connected to V_LPF), respectively. V_LPF is the voltage value across the low pass filter 15. V_H and V_L are the maximum and minimum values, respectively, of the output (V₀⁺ and V₀⁻) of delay cell 20. Vd is the voltage difference (V₀⁺−V₀⁻) and can be greater than or equal to zero. N represents the number of delay cells 20 that make up the VCDL 18, and C_L represents the capacitive load seen by each output of delay cells 20.

[0048] Gain control circuit 99 operates similar to switching circuit 57 (FIG. 4A). However, instead of switching on and off current sources from the loads, such as symmetric loads 70, 72, 74 and 76, gain control circuit 99 switches voltage input sources for each of the loads 91-96. While loads of bias generator 16, symmetric loads 70, 72, 74, and 76, were symmetric, loads 91-96 of bias generator 100 are not necessarily symmetric in that different amounts of current can be provided from different loads of loads 91-96. Thus, varying amounts of fixed currents for the different currents can be provided, maintaining a similar level of varying current for each current range keeping K_VCDL similar in all current ranges. Based on values of R0 and R1, which may be provided by current range control circuit 17, the gain control circuit 99 selects voltages for individual loads of loads 91-96. For each load of loads 91-96, the current range control circuit can provide either a fixed voltage reference V_REF, V_LPF (from low pass filter 15), or V_DD, as in the following table, Table 1.

[0049]

TABLE 1
R0	R1	CH1	CH2	CH3	CH4	CH5	CH6
0	0	VLPF	VLPF	VREF	VREF	VREF	VDD
0	1	VDD	VLPF	VLPF	VREF	VREF	VREF
1	0	VDD	VDD	VLPF	VREF	VREF	VDD
1	1	VDD	VDD	VDD	VLPF	VDD	VDD

[0050] As shown in Table 1, for each current range specified by the current range control circuit, either V_REF, V_LPF, or V_DD, can be assigned to each of the specified loads, the loads 91-96 corresponding to channels CH1-CH6 in the table, through the use of switches 81-86, respectively. Setting a voltage input source of V_LPF to a particular load allows current generated from the particular load to vary with the V_LPF signal. Setting a voltage input source of V_REF to a particular load allows the current generated by the particular load to be fixed. Alternatively, the gain control circuit 99 can also disable voltage inputs V_LPF and V_REF and provide V_DD to a particular load, effectively shutting off current generated from that particular load. Fixed current provided by some of the loads of loads 91-96 set a minimum current value for a particular current level, as illustrated in the graph in FIG. 8. It should be noted that the device widths for loads 91-96 may be the same or different for each load. For example, in one embodiment, the device widths for loads 95 and 96 are smaller than the device widths for loads 91-94. Furthermore, it should be appreciated that other methods of providing varying current levels can be used without departing from the scope of the present disclosure.

[0051] In the graph of FIG. 8, each of the current levels are shown as I-V curves 101-104. Curve 101 is indicative of a curve from the current level with R₀ and R₁ having values of 0,0, respectively. Curve 102 is indicative of a curve from the current level with R₀ and R₁ having values of 0,1, respectively. Curve 103 is indicative of a curve from the current level with R₀ and R₁ having values of 1,0, respectively. Curve 104 is indicative of a curve from the current level with R₀ and R₁ having values of 1,1, respectively. Each current level has a fixed range of current. For example, curve 101 only operates a current I_B between I₀ and I₂. Curve 102 operates with a current I_B between I₁ and I₄. Curve 103 operates with a current I_B between I₃ and I₆. The value of I_B is allowed to go to zero in curve 104, wherein the range of I_B is within I₅ and zero.

[0052] It should be noted that the current levels for each of the curves 101-104 overlap with adjacent curves. For each I-V curve 101-104, the full range of voltage associated with the V_LPF is not desirable for use. While V_LPF is capable of ranging from the full level of the supplied power level, noise and device limitations result in unreliable values of K_VCDL near the limits of the power supply (near 0 V and the maximum voltage of the power supply V_DD). For example, it may be desired for transistors associated with the delay cells 20_a . . . 20_n to be in a saturated mode of operation for reliable use. The values of K_VCDL are unreliable and unstable below a first threshold, V_TH0, and above a second threshold V_TH1. Therefore, for each curve 101-103, the usable range of V_LPF, during which a DLL such as DLL 10 is in a locked mode of operation, is between limits such as V_TH0 and V_TH1. The locked mode of operation indicates when the DLL is tracking a reference signal, such as F_REF. Despite device limitations, the final curve 104 can be allowed to reach zero, regardless of an increase in V_LPF greater than the V_TH1. As previously discussed in reference to the I-V curves of FIG. 5, current range control circuit 17 can monitor the value of V_LPF and switch to a next curve when the value of V_LPF approaches the value of V_TH1. Once the current range control circuit 17 switches to a next current range, a reset signal, Cal_reset, is provided to reset V_LPF to zero. V_LPF then ramps up in voltage as the delay cells 20_a . . . 20_n are operated in the next current range. It should be noted that while the same limits are shown for each of the curves 101-104, different limits can be used for each of the curves, without departing from the scope of the present disclosure.

[0053] Based on the current ranges of I_B, the delay cells 20_a . . . 20_n can generate a particular range of phases. As portions of the full range of voltage for V_LPF are not usable with a single current range, the current ranges associated with adjacent curves 101-104 overlap. For example, the highest current limit for curve 102 is I₁, which is within the current range of curve 101. Similarly, the highest current for curve 103 is I₃, which is within the current range of curve 102. Accordingly, ranges of phases generated by the delay cells 20_a . . . 20_n also overlap for each of the current levels.

[0054] Referring back to FIG. 7, differential amplifier 87 operates similar to differential amplifier 54 and removes noise from bias current i_B. Bias current i_B is converted to bias voltages V_BP and V_BN, through the use of n-channel transistors 88 and 98 and p-channel transistor 97. The bias voltages, provided to delay cells 20_a . . . 20_n, control the gain factor, K_VCDL, of the delay cells 20_a . . . 20_n. As V_BP and V_BN are limited in voltage, dependent on the current limits of I_B in a particular current level, a resultant K_VCDL does not have to operate for a full range of the supply voltage V_DD. While prior-art devices forced the K_VCDL to be used for a full range of current, such as current I₀ to zero amps, the bias generator 100 allows a K_VCDL generated to work in a smaller range while not reducing the operational range of a DLL, such as DLL circuit 10. For example, a K_VCDL for a first current level, such as the current level associated with curve 101 only has to operate within a current range of I₀ and I₂. Within each range of current, the delay cells 20_a . . . 20_n operates in a fixed range of phases. However, as each of the different current levels can be used, the delay cells 20_a . . . 20_n can still be operated over a full range of phases. Conventional low power devices had large K_VCDLs which caused high jitter and poor feedback stability. The present embodiment of FIG. 7 allows for smaller subsets of frequencies for small current ranges to be used to allow each K_VCDL associated with a particular current level to be small while still providing a full range of operation, by switching to other current levels.

[0055] While a specific embodiment of the present disclosure has been shown and described, many modifications and variations can be made by one skilled in the art without departing from the spirit and scope of the disclosure. The above description serves to illustrate and not limit the particular form in any way.