TLB parity error recovery

[0001] 1. Field of the Present Invention

[0002] The present invention relates to the field of data processing systems, and more particularly, to address translation mechanisms such as translation lookaside buffer (TLBs) and facilities for responding to an error detected during the address translation process.

[0003] 2. History of Related Art

[0004] Data processing systems employing virtual addressing schemes are well known in the field of microprocessor based data processing systems. In a virtual address machine, each program can access the complete effective address (EA) of the system. To accommodate multiple programs running simultaneously, a virtual address (VA) is utilized. The virtual address space is larger than the effective address space so that operating system can allocate separate regions of the virtual address space to each program. Typically, the operating system associates some portions of the effective address space with private virtual address space regions for exclusive use by a program when the program is started. These private regions are not accessible to a second program. Other regions of the effective address space are associated with shared virtual address space regions that are accessible to some or all other programs. These shared regions may contain, for example, operating and subroutine libraries.

[0005] When an instruction that references an address in memory such as a load or store instruction is executed, the effective address of the instruction must be translated before the memory can be accessed. The address translation process may include translating the effective address to an intermediate address known as the virtual address and then converting the virtual address to a real address or physical address. The translation from an effective address to a virtual address is typically performed using a segment-lookaside-buffer (SLB) or a segment register, the content of which replaces some of the high order bits of the effective address. The resulting virtual address is subsequently translated to a real address using a translation-lookaside-buffer (TLB) or a page table. The TLB is a cache of the content of page table entries that have been used recently to translate virtual address.

[0006] The two step address translation described can reduce the performance of the processor. To address the performance penalties associated with a two step address translation, the processor may implement one or more effective-to-real address tables (ERATs) to translate effective addresses directly to real addresses. These ERATs are cache tables that contain the results of recent address translations. When an address generated by a program misses in the ERAT, the address translation must be performed using the SLB. If the program address also misses in the TLB, the TLB must be reloaded from system memory. The program latency associated with a memory access resulting from a TLB miss is significant enough to warrant the use of relatively large TLBs to reduce the TLB miss rate to an acceptable level.

[0007] For systems using 64 bits or more of addressing, the increasingly large number of entries desirable for an adequate TLB results in a TLB unit that occupies a significant area of the processor. As the size of the TLB grows, the likelihood that the TLB contains an error increases. It would therefore be desirable to implement a mechanism by which errors in the TLB would be quickly identified. It would be further desirable if the implemented solution were able to respond to a TLB with a precise exception routine.

[0008] The identified problems are in large part addressed by a microprocessor, data processing system, and method for handling parity errors in an address translation facility such as a TLB. The microprocessor includes a load/store unit configured to generate an effective address associated with a load/store instruction. An address translation unit adapted to translate the effective address to a real address using a translation lookaside buffer (TLB). The address translation unit includes a parity checker configured to verify the parity of entries in the TLB and to signal the load store unit when a TLB entry contains a parity error. The load store unit is configured to initiate a TLB parity error interrupt routine in response to the signal from the translation unit. In one embodiment, the TLB interrupt routine selectively invalidates the TLB entry that contained the parity error. The load/store unit preferably includes an effective to real address table (ERAT) containing a set of address translations. In this embodiment, the load/store unit invokes the address translation unit to translate the effective address only if the effective address misses in the ERAT. The LSU may suitably include an ERAT miss queue (EMQ) adapted to retain an effective address that misses in the ERAT until the address translation unit completes the translation process. In this embodiment, the EMQ is configured to issue a TLB parity error interrupt signal to initiate the TLB parity error interrupt routine. In one embodiment, the TLB interrupt routine loads a data address register (DAR) of the microprocessor with the effective address of the instruction that resulted in the parity error. The TLB interrupt routine may further set a data storage interrupt routine status register (DSISR) to indicate the TLB parity error.

[0013] While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description presented herein are not intended to limit the invention to the particular embodiment disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.

[0014] Turning now to FIG. 1, a simplified block diagram of a data processing system 113 in accordance with the invention is depicted. Data processing system 113 includes a processor (CPU) 110 connected to a system bus 112. Although the embodiment depicted in FIG. 1 indicates a single CPU 110, it will be appreciated that multiple CPUs may be connected to system bus 112 in a multiprocessor embodiment. As shown in FIG. 1, data processing system 113 further includes a system memory (RAM) 114. In addition, a user interface adapter 122 is connected to system bus 112 to provide facilities for input devices such as a keyboard 124 and a pointing device or mouse 126. Data processing system 113 further includes a display device such as a monitor indicated by reference numeral 138 connected to system bus 112 via a display adapter 136. An I/O adapter 118 is connected to system bus 112 and provides facilities for connecting mass storage devices such as a hard disk 120 or a tape drive unit 140. The communications adapter 134 connected to system bus 112 provides facilities for connecting data processing 113 to other data processing systems via a computer network. A non-volatile memory device (ROM) 116 may include computer instructions such as a basic input-output system (BIOS) or other fundamental soft routines that control the interaction of CPU 110 with other hardware.

[0015] Turning now to FIG. 2, a load/store unit (LSU) 201 configured in accordance with the present invention is depicted. LSU 201 is a functional unit within CPU 110. In the depicted embodiment, LSU 201 includes a dual pipeline structure in which two load or store instructions can be issued per machine cycle. Registers 202 through 205 receive operands from fixed points units (not shown). A 64 bit adder 206 adds operands received from registers 202 and 203 to produce an effective address that is output to an effective address register 208. 64 bit adder 207 adds the operands from registers 204 and 205 to produce an effective address at register 209. The effective addresses are decoded to access tag arrays 210 and 211 to determine whether there is a hit or miss within L1 data cache 236. If there is a cache miss, then the addresses are passed through registers 212 and 213 and sent to an L2 cache (not shown) effective addresses are further sent from adders 206 and 207 to respective effective to real address translator (ERAT) arrays 214 and 215 respectively. The ERATs 214 and 215 output translated addresses through registers 216 and 217 if there is a hit to the ERAT table. Effective addresses from adders 206 and 207 also access L1 cache 236 for load operations after being decoded by decoders within L1 cache 236 if there is hit in the L1 cache 236, then the data is read out of the L1 cache 236 into registers 237, 238 and formatted by formatters 240 and 241 and returned on the result bus to be sent to a register file (not shown). The cache line read from L1 cache 236 is also returned into registers 202 through 205 for operations that are dependant on the result as an operand. If the effective address misses in the L1 cache, the request is forwarded to the L2 cache (not shown). The load miss queue (LMQ) 218 waits for the load data to come back from the L2 cache. The data associated with the cache line retreat from the L2 cache is then loaded L1 cache 236.

[0016] In the preferred embodiment, load operations can be performed speculatively and out of order. Store instructions may also be executed out of order. Store instructions are passed through the address translator operation in ERATs 214 and 215. They are then inserted into the store data queue (SDQ) 221 for storage into L1 cache 236 after the instructions have completed. Store instructions may execute out of order but are written but are written into L1 cache 236 in order.

[0017] Store reorder queue (SRQ) 222 keeps track of store instructions that have been executed. SRQ 222 maintains the store instructions in the queue and determines when the data is available in the store data queue (SDQ) 221 and when the store instruction will be the next instruction to complete. Registers 223, 225 through 229 and 237 through 238 are utilized for timing. Cache lines in L1 cache 236 are accessed based on the effective address of the cache line. The real address (RA) tag array 233 keeps track of where in the L1 cache 236 a cache line was written. Format block 231 takes the data from SDQ 221 and rotates it properly to write into the correct byte positions in L1 cache 236 upon execution of a store instruction. Rotate blocks 224 and 230 are utilized for store forwarding. If there is a store instruction that is waiting in the store queue and has not been written into the queue because it is not next to complete, and a younger load instruction is received that needs that data, the data will be forwarded to the load instruction being executed. Rotate block 239 is utilized to rotate data received from the L2 cache in response to an L1 cache miss, for forwarding the data from the L2 cache onto the result bus for forwarding to the proper register file. Register 235 is implemented for timing purposes to stage from the L2 cache (not shown). Format blocks 240 and 241 format or shift cache data into the proper byte positions for the load result to the register file.

[0018] Load/store unit 201 further includes an ERAT miss queue (EMQ) 250. EMQ 250 contains the effective addresses and other information for instructions that miss in ERATs 214 and 215 while the address translation process is in progress. EMQ 250 is configured to receive various control signals from an address translation unit portion of load/store unit 201 described in greater detail with respect to FIG. 3 below. In the present embodiment, EMQ 250 is configured to receive a TLB machine check signal 252 generated by the address translation. The TLB machine check signal 252 informs EMQ 250 that a parity error was discovered in the table look-aside-buffer during translation of an effective address that missed in ERATs 214 and 215.

[0019] Turning now to FIG. 3, a load/store translation unit 300 is depicted. LSU translation unit 300 is configured to receive effective addresses from load/store unit 201 and from an instruction fetch unit 350 that miss in their corresponding ERAT tables. In the depicted embodiment, load/store unit 201 includes two data ERAT tables 214 and 215 as discussed previously. In addition, an instruction fetch unit 350 includes an instruction ERAT table 301 that functions in a manner similar to data ERATs 214 and 215 for addresses that correspond to instructions rather than data. Each ERAT includes an effective address register and a miss signal register at its output. Instruction ERAT 301 includes an effective address register 303 and a miss register 304. The first data ERAT (D-ERAT0) 214 includes an EA0 register 305 and a miss register 306. A second data ERAT (D-ERAT1) 215 includes an effective address register (EA1) 307 and a miss register 308.

[0020] When an address misses in its corresponding ERAT, the ERAT generates a miss signal that is forwarded to its corresponding miss register. In addition, the effective address that missed in the ERAT is forwarded to the corresponding effective address register. The effective address registers 303, 305, and 307 are forwarded to respective registers 310, 311, and 312 in LSU translation unit 300. The miss signal information from miss registers 304, 306, and 308 are forwarded to an arbitration block 313 in LSU translation unit 300. Recall that the ERATs comprise a relatively small memory array for rapidly generating translation information. When an address generated by a program is not found in the relatively small ERAT, the address is forwarded to translation unit 300 to perform the address translation process.

[0021] In the depicted embodiment, CPU 110 includes only a single translation unit 300. Therefore, access to the translation unit facilities must be arbitrated in the event that multiple ERAT misses occur simultaneously. Arbitration block 313 may utilize any of a variety of arbitration schemes to select among registers 310, 311, and 312 for forwarding to the translation unit facilities in LSU translation unit 300. In the depicted embodiment, arbitration block 313 selects an effective address from registers 310, 311, or 312 and forwards the effective address to a segment lookaside buffer (SLB 314). SLB 314 is utilized to generate a virtual address from the effective address. SLB 314 generates, in response to receiving an effective address, a virtual address that includes a virtual segment identifier (VSID). The VSID is forwarded to translation lookaside buffer (TLB) 315 for comparison with a set of VSIDs stored therein.

[0022] TLB 315 includes a set of entries where each entry includes a VSID, which serves as a tag, and a real address component. TLB 315 compares a received address, such as the VSID, with its set of tags and determines if the VSID matched to one of the VSIDs in the TLB. If the VSID generated by SLB 314 matches or hits in TLB 315, the real address component of the matching TLB entry is output and a hit signal 320 is generated. The real address is then routed back to load/store unit 201 or instruction fetch unit 350 for the purposes of reloading the ERATs 214, 215, or 301. In addition, LSU translation unit 300 includes a parity checker 322 configured to check the parity of an entry in TLB 315 when a VSID comparison results in a cache hit. In the preferred embodiment, TLB 315 is configured to generate and store one or more parity bits corresponding to each entry when the TLB is loaded. When a TLB match occurs, parity checker 322 verifies the parity of the matched TLB entry. If parity checker 322 detects an error, it is asserts an error signal 324. If hit signal 320 and error signal 324 are simultaneously asserted, TLB machine check signal 252 is asserted and routed back to EMQ 250 (as shown in FIG. 2).

[0023] Returning now to FIG. 2, in response to receiving an asserted TLB machine check signal 252, EMQ 250 is adapted to assert a TLB parity error signal 254. TLB parity error signal 254 is preferably asserted by EMQ 250 while the effective address that was responsible for the TLB parity error is present in the pipeline. In the depicted embodiment, TLB parity error signal 254 is routed to an interrupt logic block 256. In response to receiving an asserted TLB parity error signal 254, interrupt logic block 256 initiates a TLB parity error recovery routine. In one embodiment, the TLB parity error recovery is configured to store the effective address that generated the parity error into a data address register (DAR) (not depicted) of microprocessor 110 and to write one or more bits in a data storage interrupt status register (DSISR) to indicate the TLB parity error as the source of the data storage interrupt. The DAR and DSISR are special purposes registers used for handling data storage interrupts. Additional information concerning data storage interrupts as implemented in prior are microprocessors is available in PowerPC™ Microprocessor Family: The Programming Environments (January, 1997) (IBM Order No.: G522-0290-00), which is incorporated by reference herein. In the preferred embodiment, the TLB parity error recovery routine is configured to read the DARs/DSISR to determine which address generated the TLB parity error signal. In response to determining the effective address that resulted in the TLB parity, one embodiment of the recovery routine is configured to selectively invalidate the specific entry within TLB 315 by accessing TLB 315 with the VSID corresponding to the effective address in the DAR while a TLB invalidate entry signal is asserted. After invalidating the appropriate TLB entry, the TLB parity error recovery routine completes and returns control to LSU 201, which allows the instruction corresponding to the parity error to finish execution with a machine check error signal. By routing the TLB machine check signal 252 to EMQ 250, the present invention facilitates the timely detection of a parity error in TLB 315 so that a precise interrupt routine, in which the effective address that resulted in the parity error, is recorded. In this manner, the error recovery routine is tailored to invalidate only the entry within TLB 315 that contained the parity error.

[0024] With the parity checking detection circuitry described herein, the address translation process may result in one of three conditions during a TLB comparison. In response to an ERAT miss, the effective address is translated to a virtual address by SLB 314. The VSID generated in SLB 314 is then routed to TLB 315 for comparison with the VSIDs stored therein. If the TLB comparison results in a TLB hit and parity checker 322 detects no parity error, the real address generated by TLB 315 is returned to the appropriate ERAT and the instruction is completed. If the TLB comparison of the VSID generated by SLB 314 results in a TLB miss, a page fault is returned to the ERAT in the appropriate TLB entry is retrieved from a page table entry in system memory. If the TLB comparison results in a TLB hit, but parity checker 322 indicates a parity error, the TLB machine check signal is returned to the ERAT. In one embodiment, the DAR is loaded with the effective address that resulted in the parity error and a TLB parity error recover routine initiated. Preferably, the recovery routine retrieves the information in DAR/DSISR to perform a precise interrupt routine in which only the entry in TLB 315 containing the parity error is invalidated. In one embodiment, the recovery routine may include the step of retrieving the appropriate page table entry from system memory in anticipation that the instruction that resulted in the parity error initially will be subsequently re-executed and will require translation in LSU translation unit 300. After the TLB parity error recovery routine is completed, the instruction that generated the error is allowed to execute. Upon completion, the machine check status of the instruction is evaluated and handled appropriately.

[0025] It will therefore be appreciated that the present invention contemplates a method of responding to a parity error in a table look-aside-buffer with a precise routine. It is understood that the form of the invention shown and described in the detailed description and the drawings are to be taken merely as presently preferred examples. It is intended that the following claims be interpreted broadly to embrace all the variations of the preferred embodiments disclosed.