US 6,897,673 B2Grant
Method and integrated circuit for capacitor measurement with digital readout
Issue Date:2005-05-24
•10 Claims
•9 Drawing Sheets
Abstract
On-chip absolute value measurement circuit and an on-chip capacitor mismatch value measurement circuits are provided. The absolute value measurement circuit begins charging a capacitor. When the voltage across the capacitor reaches a first threshold, the absolute value measurement circuit starts a counter. When the voltage across the capacitor reaches a second threshold, the counter stops. The counter value is provided as digital output. A computer device reads the digital output and calculates the absolute value of the capacitor based on the counter value. The mismatch measurement circuit repeatedly charges an evaluation capacitor and transfers the charge from the evaluation capacitor to an integrating capacitor. For each transfer of charge, a counter is incremented until the voltage across the integrating capacitor reaches a threshold voltage. The counter value is provided as digital output. This process is repeated for each evaluation capacitor on the chip. A computer device reads each counter value and calculates mismatch values based on the counter values.
Metadata
Assignee
- LSI Logic Corporation
Inventors
- Scott Christopher Savage
- John Lynn McNitt
- Sean Anthony Golliher
Application Information
Application Number:US 10/392,206
Filing Date:2003-03-19
Priority Date:2003-03-19
Art Unit:2829
Patent Drawings (9 sheets)
Description
Background of the Invention
[0001] 1. Technical Field
[0002] The present invention relates to capacitor mismatch and absolute value measurements and, in particular, to analog built-in self test circuits. Still more particularly, the present invention provides a method and integrated circuit for on-chip capacitor measurement with digital readout.
[0003] 2. Description of the Related Art
[0004] It is advantageous to know accurate capacitor absolute values and capacitor mismatch values of on-chip capacitors. Many analog circuits rely on precise values or ratios of capacitors for proper operation. For example, an analog-to-digital converter (ADC) relies upon capacitor mismatch for correct operation.
[0005] Generally, capacitor absolute values and capacitor mismatch values are measured with capacitor/voltage (CV) test equipment. This manual approach is lacking, because a specialized and expensive test setup is needed to place probes on a chip to extract the density of on-chip capacitor structures. This procedure requires that the test structures be accessible by a probe station. Furthermore, capacitor value measurements are so specific and specialized that, in general, no other tests can be performed with this same setup, since the setup is specialized for capacitor value measurements only.
[0006] As the size of the unit capacitor gets smaller, the accuracy of the absolute measurement is degraded. When the size of the capacitor decreases, the margin for error also decreases. This, in turn, degrades the accuracy of mismatch calculation.
[0007] Therefore, it would be advantageous to provide improved methods and integrated circuits for capacitor absolute value and mismatch measurement.
Summary of the Invention
[0008] The present invention provides on-chip absolute value measurement circuit and an on-chip capacitor mismatch value measurement circuit. The absolute value measurement circuit begins charging a capacitor. When the voltage across the capacitor reaches a first threshold, the absolute value measurement circuit starts a counter. When the voltage across the capacitor reaches a second threshold, the counter stops. The counter value is provided as digital output. A computer device reads the digital output and calculates the absolute value of the capacitor based on the counter value.
[0009] The mismatch measurement circuit repeatedly charges an evaluation capacitor and transfers the charge from the evaluation capacitor to an integrating capacitor. For each transfer of charge, a counter is incremented until the voltage across the integrating capacitor reaches a threshold voltage. The counter value is provided as digital output. This process is repeated for each evaluation capacitor on the chip. A computer device reads each counter value and calculates mismatch values based on the counter values.
Brief Description of the Drawings
[0010] The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
[0011] FIG. 1 is a block diagram illustrating a capacitor absolute value test setup in accordance with a preferred embodiment of the present invention;
[0012] FIG. 2 is a diagram depicting a capacitor absolute value measurement circuit in accordance with a preferred embodiment of the present invention;
[0013] FIG. 3 shows an example timing diagram for capacitor absolute value measurement in accordance with a preferred embodiment of the present invention;
[0014] FIG. 4 is a flowchart illustrating the operation of a capacitor absolute value measurement process in accordance with a preferred embodiment of the present invention;
[0015] FIG. 5 is a block diagram illustrating a capacitor mismatch test setup in accordance with a preferred embodiment of the present invention;
[0016] FIG. 6 is a diagram depicting a capacitor mismatch value measurement circuit in accordance with a preferred embodiment of the present invention;
[0017] FIG. 7 depicts timing diagram for the operation of determining a relative value for one evaluation capacitor in accordance with a preferred embodiment of the present invention; and
[0018] FIG. 8 is a flowchart illustrating the operation of a capacitor mismatch value measurement process in accordance with a preferred embodiment of the present invention.
Detailed Description
[0019] The description of the preferred embodiment of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiment was chosen and described in order to best explain the principles of the invention the practical application to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
[0020] With reference now to the figures and in particular wiht referece to FIG. 1 , a block diagram illustrating a capacitor absolute value test setup is shown in accordance with a preferred embodiment of the present invention. Capacitor circuit chip 100 is connected to workstation 102. The workstation may be a computer device, such as a desktop computer, a notebook computer, or a handheld computer. The workstation may also be specialized measurement computer device.
[0021] The workstation provides a start signal, START, to begin the test. The workstation then reads a digital value, DATA, provided by the capacitor measurement circuit within capacitor circuit 100. The DATA value may be used to determine the absolute value of a capacitor within the capacitor circuit. The workstation may also provide a clock signal, CK, to be used by the measurement circuit.
[0022] With reference to FIG. 2 , a diagram depicting a capacitor absolute value measurement circuit is shown in accordance with a preferred embodiment of the present invention. The capacitor absolute value measurement circuit includes a capacitor to be measured, C1. All switches in the measurement circuit are assumed to be positively triggered, meaning that a high control signal closes the switch and a low signal opens the switch. However, other conventions may be used within the scope of the present invention.
[0023] Before measurement begins, START is low and the circuit is initialized by closing switch SW0 and SW1 while SW2 is open. Current Ibias, generated by current source 204, flows through switch SW1 to ground, all the charge is cleared from capacitor C1, and the voltage at node VA goes to zero. Techniques and circuits for generating a substantially constant current are known in the art.
[0024] To begin the measurement, START is asserted (high). Control circuit 202 assures that Q goes high before Qb goes low. This ensures that Ibias always has a place to flow and the current source is never turned off. This technique is commonly referred to as make-before-break switching. Now, in the charging phase of operation, SW0 and SW1 are now open, while SW2 is closed. Current Ibias now flows directly into capacitor C1, causing the voltage at node VA to rise linearly with time according to the following equation:
As VA becomes larger than VREFM, V1 goes from low to high. VREFM is a predetermined, known, threshold voltage. The digital counter begins counting when comparator 208 is triggered by V1 going high. The N-bit digital counter counts up from zero in binary when there is a clock, CK, present and when V1 is high and V2 is low. The clock, CK, may be generated on-chip or supplied by a workstation or computer device.
As VA becomes larger than VREFM, V1 goes from low to high. VREFM is a predetermined, known, threshold voltage. The digital counter begins counting when comparator 208 is triggered by V1 going high. The N-bit digital counter counts up from zero in binary when there is a clock, CK, present and when V1 is high and V2 is low. The clock, CK, may be generated on-chip or supplied by a workstation or computer device.
[0025] Once the voltage VA becomes greater than that of VREFP, then comparator 206 is triggered and V2 becomes high. VREFP is a predetermined, known, threshold voltage. The counter stops counting when V2 is high and the value of the counter is stored and ready for observation at the bus DATA, which is observable at external chip pins. At this point, the binary number stored in the counter represents the number of clock cycles that it took for capacitor C1 to charge from VREFM to VREFP using a constant current Ibias.
[0026] Given the values of VREFM, VREFP, Ibias, and the input clock frequency, the absolute value of the capacitor may be determined using the equation:
where L is the number of clock cycles as recorded by the binary counter, T is the period of the clock input to node CK, and CT is the total capacitance at node VA.
where L is the number of clock cycles as recorded by the binary counter, T is the period of the clock input to node CK, and CT is the total capacitance at node VA.
[0027] CT, as measured above, includes C1 and all parasitic capacitances, CP, at node VA (CT=C1+CP). To subtract CP from CT, one must simply remove C1 from the circuit and repeat the above procedures to determine CP. Now, given a value for CP, one may determine the value of C1 as CT−CP.
[0028] With regard to current source 204, one method for obtaining a known bias current, Ibias, on chip is applying a voltage, perhaps VBG, a band-gap voltage, across an external resistor, REXT using a feedback loop. The current through this external resistor can be current mirrored to create Ibias. Since VBG and REXT are external to the chip, both the resistor value and the voltage at VBG can be measured very accurately. Ibias will then simply be as follows:
where M is any integer or real number representing the ratio of multiplication factors or widths in the current mirror devices. As to the voltages VREFM and VREFP, there is also a need to know these voltage values to a reasonable degree of accuracy. A non-inverting op-amp configuration can create both of these voltages by multiplying or dividing the known VBG voltage.
where M is any integer or real number representing the ratio of multiplication factors or widths in the current mirror devices. As to the voltages VREFM and VREFP, there is also a need to know these voltage values to a reasonable degree of accuracy. A non-inverting op-amp configuration can create both of these voltages by multiplying or dividing the known VBG voltage.
[0029] FIG. 3 shows an example timing diagram for capacitor absolute value measurement in accordance with a preferred embodiment of the present invention. The number of clock cycles in a real conversion would be substantially larger than in this example to increase measurement resolution. VREFP and VREFM are chosen by the designer and are generally constrained to be within the power supply voltage available. For example VREFM is shown in FIG. 3 to be zero; however, VREFM could be any value between VREFP and ground.
[0030] With reference now to FIG. 4 , a flowchart illustrating the operation of a capacitor absolute value measurement process is shown in accordance with a preferred embodiment of the present invention. The process begins by asserting the START signal (step 402) and starting a clock, CK (step 404). A control circuit causes Q to go high, closing switch SW2 (step 406). Subsequently, the control circuit causes Qb to go low, closing switches SW0 and SW1 (step 408). Next, a determination is made as to whether a first threshold voltage across the capacitor is reached (step 410). A first comparator causes V1 to go high when the first threshold is reached.
[0031] The capacitor continues to charge until the first threshold is reached and V1 goes high, at which time the counter starts (step 412). Next, a determination is made as to whether a second threshold voltage across the capacitor is reached (step 414). A second comparator causes V2 to go high when the second threshold is reached. The capacitor continues to charge until the second threshold is reached and V2 goes high, at which time the counter stops (step 416). The capacitor value is read at the DATA bus (step 418) and the process calculates the absolute capacitor value using the value at DATA (step 420). Thereafter, the process ends.
[0032] With reference now to FIG. 5 , a block diagram illustrating a capacitor mismatch test setup is shown in accordance with a preferred embodiment of the present invention. Capacitor circuit chip 500 is connected to workstation 502. The workstation may be a computer device, such as a desktop computer, a notebook computer, or a handheld computer. The workstation may also be specialized measurement computer device.
[0033] The workstation provides a reset signal, RST, to begin each portion of the mismatch test. In the example shown in FIG. 5 , the capacitor circuit includes four evaluation capacitors. The workstation may isolate each capacitor by asserting the appropriate combinations of P1A, P2A, P1B, P2B, P1C, P2C, P1D, P2D, P2, and P1R, as will be discussed below. The workstation then reads a digital value, DATA, provided by the capacitor measurement circuit within capacitor circuit 500 for each evaluation capacitor. The DATA values may be used to determine the capacitor mismatch values for the capacitors within the capacitor circuit.
[0034] With reference to FIG. 6 , a diagram depicting a capacitor mismatch value measurement circuit is shown in accordance with a preferred embodiment of the present invention. Mismatch is generally defined as the difference in absolute capacitance for capacitors that are drawn equally on a chip, but differ in absolute value due to processing variations. This processing variation is generally caused by differences in dielectric thickness, in etchings of the capacitor plates, and in proximity effects. The present invention allows an accurate measurement to be obtained of on-chip capacitor matching in a packaged part with a digital tester.
[0035] The capacitor mismatch value measurement circuit includes evaluation capacitors to be measure, CA, CB, CC, and CD. While the example shown in FIG. 6 includes four evaluation capacitors, more or fewer capacitors may be measured within the scope of the present invention. Ideally these capacitors have the same value; however, non-ideal aspects during fabrication prevent these capacitors from having exactly the same absolute value. Feedback capacitor, CFB, is a large integrating capacitor. As an example, CFB may be approximately 10,000 times larger than CA for this illustration. Amplifier 602 is used to create a switched capacitor integrator that transfers charge from the evaluation capacitors to the integrating capacitor. Comparator 604 compares the voltage at the output of the integrator, VO, with an on-chip reference voltage, VREF. Generally, VREF may be midway between the power supplies of the chip (VDD+VSS)/2. The absolute value of VREF is not critical; however, VREF must remain consistent throughout the entire measurement.
[0036] The function of digital counter 606 is to count the number of clock cycles between reset, RST, and when the output of the comparator, VC, toggles from a low to a high for each of the evaluation capacitors. In other words, the measurement circuit is reset and charge is repeatedly built up on evaluation capacitor CA and then transferred to CFB until the voltage across CFB equals VREF. The DATA value is recorded for CA and the process repeats for CB, and so on. The DATA value for CA may then be compared to the DATA value for CB to determine a mismatch between CA and CB for example.
[0037] Switches SW1, SW2, SW3, . . . , SW13 have two states, open and closed. All switches in the measurement circuit are assumed to be positively triggered, meaning that a high control signal closes the switch and a low signal opens the switch. However, other conventions may be used within the scope of the present invention.
[0038] The basic reset operation of FIG. 6 is as follows with RST asserted high. All P2* signals (P2* including P2, P2A, P2B, P2C, and P2D) are low, all P1* signals (P1* including P1, P1R, P1A, P1B, P1C, and P1D) are high, both RST switches (SW11 and SW12) are closed, and the digital counter is reset to zero. Each evaluation capacitor has VREF volts across them, since one side is permanently tied to VREF and the other side is grounded through a corresponding P1* switch. The integrating capacitor also has VREF volts across its terminals, since VM is shorted to VREF via SW11 and VO is tied to ground via SW12. In addition, VC is low since SW13 has the positive input of the comparator tied to ground with the negative input tied to VREF.
[0039] Next, FIG. 7 depicts timing diagram illustrating the operation of determining a relative value for one evaluation capacitor in accordance with a preferred embodiment of the present invention. The circuit is reset as described above. Then, both the P1* and the RST signals go low followed by the signals P2A and P2 both going high. Hence, SW1 closes and the digital counter is incremented by one from the starting value of zero. With SW1 closed, the amplifier responds to the charge stored in CA by raising its output from ground to VREF·(CA/CFB)+0, which is approximately VREF·{fraction (1/10,000)}.
[0040] Next, both P2 and P2A go low followed by P1A and P1R going high. With both P1A and P1R high, CA is recharged to VREF and the positive input of the comparator is raised to VREF·(CA/CFB) from ground. Since the positive input of the comparator is still lower than the negative input of the comparator (VREF), VC remains low.
[0041] Thereafter, both P1A and P1R go low followed by P2A and P2 again both going high. Again, SW1 closes and the digital counter is incremented by one to a value of two. With SW1 closed, the amplifier again responds to the charge stored in CA by raising its output from VREF·(CA/CFB) to VREF·(2CA/CFB). Again, both P2 and P2A go low followed by P1A and P1R going high. With both P1A and P1R high, CA is again recharged to VREF and the positive input of the comparator rises to its new value of VREF·(2CA/CFB). However, the positive comparator input is still lower than VREF and VC remains low.
[0042] This cycle of charging CA to VREF, transferring the charge from CA to CFB, and incrementing the counter continues until the voltage at VO is greater than VREF. When VO is greater than VREF, the comparator triggers and VC goes high, at which time the relative value of CA is inferred from the value of the digital counter. Since CA is assumed to be {fraction (1/10,000)} of CFB, the counter should have a value of 10,001 stored, with the extra value resulting from the comparator triggering when VO is greater than VREF rather than exactly equal.
[0043] Next, the relative value of CB is determined exactly as CA was determined. The circuit starts with a basic reset as previously described and the controls of P1A and P2A for SW2 and SW1 are substituted with controls for P1B and P2B for SW4 and SW3. For illustration purposes, assume that CB and CA are not perfectly matched such that CB=1.1·CA. Since CFB is unchanged, it will take fewer charge transfer cycles for CB to make the comparator trigger than it did for CA. More specifically, the counter will trigger at a value of {fraction (10,000/1.1)}=9,091. Hence, the mismatch for CA and CB can be calculated as {fraction (10,000/9,091)}=1.1, which clearly infers a 10% mismatch between CA and CB.
[0044] The evaluation capacitors CC and CD may be evaluated and their relative values determined to infer mismatch between CA, CB, CC, and CD. The four capacitors are used as an illustrative example. In practice, the number of capacitors would be much larger to get a more representative distribution of capacitor mismatch. Additionally, the relative value of the feedback capacitor can be made much larger to increase the measurement resolution or smaller for faster measurements and to consume less silicon area in fabrication.
[0045] Turning now to FIG. 8 , a flowchart illustrating the operation of a capacitor mismatch value measurement process is shown in accordance with a preferred embodiment of the present invention. The process begins and initializes the circuit (step 802). Then, the process charges the evaluation capacitor (step 804), transfers the charge from the evaluation capacitor to the integrating capacitor (step 806), and increments a counter (step 808). Next, a determination is made as to whether a threshold voltage is reached (step 810). If the threshold voltage is not reached, the process returns to step 804 to repeat the charge and transfer steps.
[0046] If the threshold voltage is reached in step 810, the process reads the relative data value (step 812) and a determination is made as to whether this is the last evaluation capacitor (step 814). If the current capacitor is not the last evaluation capacitor, the process considers the next evaluation capacitor (step 816) and returns to step 802 to initialize the measurement circuit. If, however, the current capacitor is the last evaluation capacitor in step 814, the process calculates mismatch values (step 818) and ends.
[0047] Thus, the present invention provides a digital tester for retrieving digital capacitor values and relative mismatch values. The test structures may be in either packaged or wafer form. The measurements of the present invention do not require an expensive and specialized capacitor/voltage measurement test box. Each capacitor measurement takes milliseconds, where each measurement using a capacitor/voltage measurement test box takes seconds, since probes must be lifted and placed on each capacitor site. Circuits sensitive to capacitor mismatch or accurate absolute value may use this circuit in a production test to quickly verify capacitor values and receive results in a digital form. The absolute value and mismatch value test circuits may also be employed separately or together in the same integrated circuit.
Claims
1. A method for on-chip measurement of capacitor values, the method comprising:
receiving, from an off-chip device, a set of digital inputs, wherein the set of digital inputs includes a reset signal and a plurality of switch signals;
measuring a value for an evaluation capacitor on the chip, wherein the step of measuring a value includes:
(a) charging the evaluation capacitor;
(b) transferring charge from the evaluation capacitor to an integrating capacitor;
(c) incrementing a counter; and
(d) repeating steps (a)-(c) until a threshold voltage is reached at the integrating capacitor; and
providing the counter value to the off-chip device in response to the threshold voltage being reached at the integrating capacitor.
2. The method of claim 1, further comprising:
determining, by the off-chip device, a capacitor mismatch value for the evaluation capacitor based on the counter value.
3. The method of claim 2, wherein the evaluation capacitor is a first evaluation capacitor and the capacitor mismatch value is a first capacitor mismatch value, the method further comprising:
determining, by the off-chip device, a second capacitor mismatch value for the second evaluation capacitor based on the second counter value; and
determining a mismatch between the first evaluation capacitor and the second evaluation capacitor based on the first capacitor mismatch value and the second capacitor mismatch value.
4. The method of claim 2, wherein the evaluation capacitor is a first evaluation capacitor and the capacitor mismatch value is a first capacitor mismatch value, the method farther comprising:
receiving a reset signal and a set of switch signals for switching to a second evaluation capacitor;
draining the integrating capacitor;
resetting the counter;
(c) charging the second evaluation capacitor,
(f) transferring charge from the second evaluation capacitor to an integrating capacitor;
(g) incrementing the counter;
(h) repeating steps (e)-(g) until the threshold voltage is reached at the integrating capacitor; and
providing a second counter value to the off-chip device.
5. The method of claim 4, further comprising:
determining, by the off-chip device, a second capacitor mismatch value for the second evaluation capacitor based on the second counter value; and
determining a mismatch between the first evaluation capacitor and the second evaluation capacitor based on the first capacitor mismatch value and the second capacitor mismatch value.
6. An apparatus for on-chip measurement of capacitor values, the apparatus comprising:
a set of digital inputs, wherein the set of digital inputs receive signals from an off-chip device and wherein the set of digital inputs includes a reset signal and a plurality of switch signals;
an evaluation capacitor on the chip;
a test circuit, wherein the test circuit measures a value for the evaluation capacitor based on the set of digital inputs, wherein the test circuit includes:
an integrating capacitor;
a first set of switches, wherein the evaluation capacitor is charged in response to the first set of switches being closed;
a second set of switches, wherein charge from the evaluation capacitor is transferred to an integrating capacitor in response to the second set of switches being closed; and
a counter,
wherein the test circuit repeatedly closes the first set of switches to charge the evaluation capacitor, closes the second set of switches to transfer charge from the evaluation capacitor to the integrating capacitor, and increments the counter until a threshold voltage is reached at the integrating capacitor and wherein the test circuit provides the counter value to the off-chip device in response to the threshold voltage being reached at the integrating capacitor; and a digital output, wherein the digital output presents the counter value.
7. The apparatus of claim 6, wherein the off-chip device determines a capacitor mismatch value for the evaluation capacitor based on the counter value.
8. The apparatus of claim 7, wherein the evaluation capacitor is a first evaluation capacitor and the capacitor mismatch value is a first capacitor mismatch value, and
wherein the off-chip device determines a second capacitor mismatch value for the second evaluation capacitor based on the second counter value and determines a mismatch between the first evaluation capacitor and the second evaluation capacitor based on the first capacitor mismatch value and the second capacitor mismatch value.
9. The apparatus of claim 7, wherein the evaluation capacitor is a first evaluation capacitor and the capacitor mismatch value is a first capacitor mismatch value, the apparatus further comprising:
a second evaluation capacitor;
a third set of switches, wherein the second evaluation capacitor is charged in response to the third set of switches being closed; and
a fourth set of switches, wherein charge from the second evaluation capacitor is transferred to an integrating capacitor in response to the fourth set of switches being closed,
wherein the test circuit receives a reset signal and a set of switch signals for switching to a second evaluation capacitor, drains the integrating capacitor, resets the counter,
wherein the test circuit repeatedly closes the third set of switches to charge the second evaluation capacitor, closes the fourth set of switches to transfer charge from the second evaluation capacitor to the integrating capacitor, and increments the counter until a threshold voltage is reached at the integrating capacitor, and
wherein the test circuit provides the counter value to the off-chip device in response to the threshold voltage being reached at the integrating capacitor.
10. The apparatus of claim 9, wherein the off-chip device determines a second capacitor mismatch value for the second evaluation capacitor based on the second counter value, and
wherein the off-chip device determines a mismatch between the first evaluation capacitor and the second evaluation capacitor based on the first capacitor mismatch value and the second capacitor mismatch value.
Patent Citations (1)
| Patent | Date | Inventor | Cited By |
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| US6268813(B1) | 2001-07-01 | de Wit | Examiner |