US 6,895,457 B2Grant
Bus interface with a first-in-first-out memory
Issue Date:2005-05-17
•20 Claims
•8 Drawing Sheets
Abstract
A system includes a multithreaded processor. The multithreaded processor includes a plurality of microengines, a memory controller, a first bus interface and a second bus interface. The second bus interface includes a first-in-first-out memory with a plurality of elements to store packet data and packet status. The system also includes a system bus coupled to the first bus interface and a network bus coupled to the second bus interface.
Metadata
Assignee
- Intel Corporation
Inventors
- Gilbert Wolrich
- Debra Bernstein
- Matthew J. Adiletta
Application Information
Application Number:US 10/664,202
Filing Date:2003-09-16
Priority Date:2003-09-16
Art Unit:2111
Patent Drawings (8 sheets)
Description
[0001] U.S. patents cited herein are each hereby incorporated by reference in their entirety.
Background of the Invention
[0002] A network device receives packets of information from a communication media access control device, e.g., an Ethernet controller. Each packet may contain data and the destination address of that data. Each receiving port of the device has a “ready signal” which indicates that a predetermined number of bytes or the last byte of the packet has been received. The predetermined number of bytes is usually 64 because that is the size of a minimum Ethernet packet. A high percentage of Ethernet packets (approximately 80%) are minimum length packets, e.g., 64 bytes. Optimizing for 64 byte packets by requesting 64 bytes increases the bandwidth of the processor.
Summary of the Invention
[0003] According to one aspect of the invention, a method is described of receiving bytes of data from a media device includes issuing N consecutive requests, each for M bytes, to the media device and receiving N-1 responses of M bytes of data from the media device.
[0004] Other advantages will become apparent from the following description and from the claims.
Brief Description of the Drawings
[0005] FIG. 1 is a block diagram of a communication system employing a hardware-based multithreaded processor.
[0006] FIG. 2 is a detailed block diagram of the hardware-based multithreaded processor of FIG. 1.
[0007] FIG. 3 is a block diagram of a communication bus interface in the processor of FIG. 1.
[0008] FIGS. 4A and 4B are flowcharts illustrating the operation of a bus interface.
Description of the Preferred Embodiments
[0009] Referring to FIG. 1 , a communication system 10 includes a parallel, hardware-based multithreaded processor 12. The hardware-based multithreaded processor 12 is coupled to a bus such as a PCI bus 14, a memory system 16, and a second bus 18. The processor 12 includes a bus interface 28 that couples the processor 12 to the second bus 18. Bus interface 28 in one embodiment couples the processor 12 to the so-called FBUS 18 (FIFO (first-in, first-out) bus). The FBUS interface (FBI) 28 is responsible for controlling and interfacing the processor 12 to the FBUS 18. The FBUS 18 is a 64-bit wide FIFO bus, used to interface to MAC devices 13. The system 10 is especially useful for tasks that can be broken into parallel subtasks or functions. Specifically, a hardware-based multithreaded processor 12 is useful for tasks that are bandwidth oriented rather than latency oriented. The hardware-based multithreaded processor 12 has multiple microengines 22 each with multiple hardware controlled threads that can be simultaneously active and independently work on a task.
[0010] The hardware-based multithreaded processor 12 also includes a central controller (also called processor or microprocessor) 20 that assists in loading microcode control for other resources of the hardware-based multithreaded processor 12 and performs other general purpose computer type functions such as handling protocols, exceptions, and extra support for packet processing where the microengines 22 pass the packets off for more detailed processing such as in boundary conditions. In one embodiment, the processor 20 is a Strong Arm® (Arm is a trademark of ARM Limited, United Kingdom) based architecture. The general purpose microprocessor 20 has an operating system. Through the operating system, the processor 20 can call functions to operate on microengines 22a-22f. The processor 20 can use any supported operating system, preferably a real time operating system. For the core processor 20 implemented as a Strong Arm architecture, operating systems such as, MicrosoftNT real-time, VXWorks and μCUS, a freeware operating system available over the Internet, can be used.
[0011] The hardware-based multithreaded processor 12 also includes a plurality of function microengines 22a-22f. Functional microengines (microengines) 22a-22f each maintain a plurality of program counters in hardware and states associated with the program counters. Effectively, a corresponding plurality of sets of threads can be simultaneously active on each of the microengines 22a-22f while only one is actually operating at any one time.
[0012] In one embodiment, there are six microengines 22a-22f as shown. Each microengines 22a-22f has capabilities for processing four hardware threads. The six microengines 22a-22f operate with shared resources including memory system 16 and bus interfaces 24 and 28. The memory system 16 includes a Synchronous Dynamic Random Access Memory (SDRAM) controller 26a and a Static Random Access Memory (SRAM) controller 26b. SDRAM 16a and SDRAM controller 26a are typically used for processing large volumes of data, e.g., processing of network payloads from network packets. SRAM 16b and SRAM controller 26b are used in a networking implementation for low latency, fast access tasks, e.g., accessing look-up tables, memory for the core processor 20, and so forth.
[0013] The six microengines 22a-22f access either the SDRAM 16a or SRAM 16b based on characteristics of the data. Thus, low latency, low bandwidth data is stored in and fetched from SRAM 16b, whereas higher bandwidth data for which latency is not as important, is stored in and fetched from SDRAM 16a. The microengines 22a-22f can execute memory reference instructions to either the SDRAM controller 26a or the SRAM controller 26b.
[0014] Advantages of hardware multithreading can be explained by SRAM or SDRAM memory accesses. As an example, an SRAM access requested by a Thread—0, from a microengine 22a-22f will cause the SRAM controller 26b to initiate an access to the SRAM 16b. The SRAM controller 26b controls arbitration for the SRAM bus 27, accesses the SRAM 16b, fetches the data from the SRAM 16b, and returns data to the requesting microengine 22a-22f. During an SRAM 16b access, if the microengine, e.g., 22a, had only a single thread that could operate, that microengine would be dormant until data was returned from the SRAM 16b. The hardware context swapping within each of the microengines 22a-22f enables other contexts with unique program counters to execute in that same microengine. Thus, another thread, e.g., Thread—1, can function while the first thread, e.g., Thread—0, is awaiting the read data to return. During execution, Thread—1 may access the SDRAM memory 16a. While Thread—1 operates on the SDRAM unit 26a, and Thread—0 is operating on the SRAM unit 26b, a new thread, e.g., Thread—2, can now operate in the microengine 22a. Thread—2 can operate for a certain amount of time until it needs to access memory or perform some other long latency operation, such as making an access to a bus interface. Therefore, simultaneously, the processor 12 can have a bus operation, SRAM operation, and SDRAM operation all being completed or operated upon by one microengine 22a and have one more thread available to process more work in the data path.
[0015] The hardware context swapping also synchronizes completion of tasks. For example, two threads could hit the same shared resource, e.g., SRAM 16b. Each one of these separate functional units, e.g., the FBI 28, the SRAM controller 26b, and the SDRAM controller 26a, when they complete a requested task from one of the microengine thread contexts reports back a flag signaling completion of an operation. When the flag is received by the microengine 22a-22f, the microengine 22a-22f can determine which thread to turn on.
[0016] Each of the functional units, e.g., the FBI 28, the SRAM controller 26b, and the SDRAM controller 26a, are coupled to one or more internal buses. The internal buses are dual, 32-bit buses (i.e., one bus for read and one for write). The hardware-based multithreaded processor 12 also is constructed such that the sum of the bandwidths of the internal buses in the processor 12 exceeds the bandwidth of external buses coupled to the processor 12. The processor 12 includes an internal core processor bus 32, e.g., an ASB bus (Advanced System Bus), that couples the processor core 20 to the memory controller 26a, 26b and to an ASB translator 30. The ASB bus 32 is a subset of the so-called AMBA bus that is used with the Strong Arm processor core. The processor 12 also includes a private bus 34 that couples the microengine units 22 to SRAM controller 26b, ASB translator 30, and FBI 28. A memory bus 38 couples the memory controllers 26a, 26b to the bus interfaces 24 and 28 and memory system 16 including a flashrom 16c used for boot operations and so forth.
[0017] One example of an application for the hardware-based multithreaded processor 12 is as a network processor. As a network processor, the hardware-based multithreaded processor 12 interfaces to network devices such as a media access controller (MAC) device, e.g., a 10/100 BaseT Octal MAC 13a or a Gigabit Ethernet device 13b. In general, as a network processor, the hardware-based multithreaded processor 12 can interface to any type of communication device or interface that receives/sends large amounts of data. If communication system 10 functions in a networking application, it could receive a plurality of network packets from the devices 13a, 13b and process those packets in a parallel manner. With the hardware-based multithreaded processor 12, each network packet can be independently processed.
[0018] Referring to FIG. 2 , the FBI 28 supports Transmit and Receive flags for each port that a MAC device supports, along with an Interrupt flag indicating when service is warranted. The FBI 28 also includes a controller 28a that performs header processing of incoming packets from the FBUS 18. The controller 28a extracts the packet headers and performs a microprogrammable source/destination/protocol hashed lookup (used for address smoothing) in an SRAM unit 26b. If the hash does not successfully resolve, the packet header is sent to the processor core 20 for additional processing. The FBI 28 supports the following internal data transactions:
[0019]
| FBUS unit | (Shared bus SRAM) | to/from microengine |
| FBUS unit | (via private bus) | writes from SDRAM Unit |
| FBUS unit | (via Mbus) | Reads to DRAM |
[0020] The FBUS 18 is a standard industry bus and includes a data bus, e.g., 64 bits wide, and sideband control for address and read/write control. The FBI 28 provides the ability to input large amounts of data using a series of input and output FIFOs 29a-29b. From the FIFOs 29a-29b, the microengines 22a-22f fetch data from or command a SDRAM controller 26a to move data from a receive FIFO in which data has come from a device on bus 18 into the FBI 28. The data can be sent through SDRAM controller 26a to SDRAM memory 16a, via a direct memory access. Similarly, the microengines 22a-22f can move data from the SDRAM 26a to the FBI 28 and out to the FBUS 18 via the FBI 28.
[0021] Referring to FIG. 3 , communication between the microengines 22a-22f and the FBI 28 is shown. The FBI 28 in a network application can perform header processing of incoming packets from the FBUS 18. A key function that the FBI 28 performs is extraction of packet headers, and a microprogrammable source/destination/protocol hashed lookup in SRAM 26b. If the hash does not successfully resolve, the packet header is promoted to the core processor 20 for more sophisticated processing.
[0022] The FBI 28 contains a transmit FIFO 29b, a receive FIFO 29a, a hash unit 29c, and FBI control and status registers (CSR) 189. These four units communicate with the microengines 22a-22f via a time-multiplexed access to the SRAM bus 38 that is connected to transfer registers in the microengines 22a-22f. All data transfers to and from the microengines 22a-22f are via the transfer registers. The FBI 28 includes a push state machine 200 for pushing data into the transfer registers during the time cycles which the SRAM 26b is not using the SRAM data bus (part of bus 38) and a pull state machine 202 for fetching data from the transfer registers in the respective microengine 22a-22f.
[0023] The hash unit 29c includes a pair of FIFOs 188a and 188b. The hash unit 29c determines that the FBI 28 received an FBI_hash request from a microengine 22a-22f. The hash unit 29c fetches hash keys from the requesting microengine 22a-22f. After the keys are fetched and hashed, the indices are delivered back to the requesting microengine 22a-22f. Up to three hashes are performed under a single FBI_hash request. The buses 34 and 38 are each unidirectional: SDRAM_push/pull_data, and Sbus_push/pull_data. Each of these buses requires control signals which will provide read/write controls to the appropriate microengine 22a-22f transfer registers.
[0024] Referring to FIGS. 4A and 4B , the FBI 28 may operate 40 in Fetch_N mode, e.g., Fetch—8 mode, as shown in FIG. 4A , where the value of N may be programmable. In Fetch—8 mode, the FBI 28 requests 42 packet data and status from a MAC device 13, e.g., the 10/100 BaseT Octal MAC 13a or the Gigabit Ethernet device 13b over a 64-bit bus, e.g., FBUS 18. In Fetch_N mode, the FBI 28 issues 42 N requests, each for M bytes, e.g., eight bytes (64 bits, one quadword), over N clock cycles (one request per cycle). The MAC device 13 responds to each request, and the FBI 28 receives 44 the M requested bytes in the receive FIFO 29a four cycles after requesting 42 the data and waits to detect 46 an end of packet indicator. In Fetch—8 mode, after receiving 44 all the requested bytes, e.g., 64 and getting the end of packet indicator, the FBI 28 requests 50 and receives another M bytes to obtain the status for minimum length packets, which uses additional clock cycles. The FBI 28 can process 54 a next operation.
[0025] Referring to FIG. 4B , the FBI 28 may operate 60 in Fetch—9 mode. In Fetch—9 mode, the FBI 28 requests 62 and receives 64 bytes generally as described above. After eleven cycles, the FBI 28 has received 64 all requested bytes. The receive FIFO 29a contains sixteen elements, each capable of storing 64 bytes of packet data plus sixteen additional bytes (two quadwords) for associated packet status. The first 64 bytes of received packet data are stored in one element of the receive FIFO 29a and the last eight bytes are stored in the first status quadword part of the receive FIFO 29a for that element. In this way, for a minimum sized packet (64 bytes), the FBI 28 already has the status associated with the packet from the initial packet data requests 62 and does not have to wait four additional cycles to request 62 and receive 64 the status.
[0026] The FBI 28 checks 66 the requested bytes by looking for an end-of-packet indicator at the end of the first 64 bytes. If the packet is a minimum length packet 68, the FBI 28 begins 70 its next operation, having received 64 a complete packet of data and its status. If the packet is between 64 and 72 bytes, the FBI 28 requests 72 another eight bytes so as to receive 72 the packet status four cycles later. These eight additional bytes are stored in the second status quadword for that element in the receive FIFO 29a. The FBI 28 begins 70 its next operation having now received a complete packet of data and its status.
[0027] Still referring to FIG. 4B , the FBI 28 may operate in Fetch—10 mode. Fetch—10 mode optimizes bandwidth for a high frequency of packets having between 64 and 80 bytes, e.g., packets with VLAN (virtual local area network) tags from the Gigabit Ethernet device 13b. In Fetch—10 mode, the FBI 28 requests 62 and receives 64 bytes as described above in FIG. 4B , except the FBI 28 issues 62 ten requests, each for M bytes, over ten clock cycles (one request per cycle). The first 64 bytes are stored in one element of the receive FIFO 29a, bytes 65-72 in the first status quadword of that element, and bytes 73-80 in the second status quadword of that element. As above, the FBI 28 checks 66, 68 to see if the receive FIFO 29a contains the packet data and its status. If so, the FBI 28 begins 48 its next operation 70. If not, it requests 72 another M bytes. Once received, this quadword may be stored in a third status quadword of that element or in another receive FIFO 29a element. The FBI 28 then begins 70 its next operation having now received a complete packet of data and its status.
Claims
1. A system comprising:
a multithreaded processor comprising a plurality of microengines, a memory controller, a first bus interface and a second bus interface, the second bus interface comprising a first-in-first-out memory with a plurality of elements to store packet data and packet status;
a system bus coupled to the first bus interface;
a network bus coupled to the second bus interface;
a media access control device coupled to the network bus; and
a memory system coupled to the memory controller.
2. The system of claim 1, wherein the second bus interface comprises a controller and a first-in-first-out memory operable to store data from the memory system to be sent to the second bus.
3. The system of claim 1, wherein each microengine has a plurality of hardware-controlled threads operable to be active simultaneously.
4. The system of claim 1, wherein the second bus interface is operable to issue N requests for packet data and packet status to the media access control device coupled to the network bus, each request for M bytes; receive packet data and packet status and store received packet data and packet status in an element of the first-in-first-out memory; detect an end-of-packet indicator; determine if the last M received bytes contain data or packet status; and if the last M received bytes contain packet data, issue other request of M bytes to retrieve packet status.
5. A processor comprising:
a bus interface coupled to a bus, the bus interface comprising first-in-first-out memories;
a plurality of microengines coupled to the bus interface, each microengine having a plurality of hardware-controlled threads operable to be active simultaneously, the microengines being operable to transfer data to the first-in-first-out memories;
a first memory controller; and
a second memory controller.
6. The processor of claim 5, wherein bus interface is coupled to a bus, the bus being coupled to a media access control device.
7. The processor of claim 5, wherein each microengine maintains a plurality of program counters and states associated with the program counters.
8. The processor of claim 5, wherein a first thread of a microengine is operable to request access to a memory coupled to the first memory controller, and a second thread of the microengine is operable while the first thread waits for data from the memory.
9. The processor of claim 8, wherein the first memory controller sends a signal to the microengine when the first memory controller completes the requested access.
10. The processor of claim 8, wherein the second thread of the microengine is operable to request access to a second memory coupled to the second memory controller, and a third thread of the microengine operates while the first and second threads wait for data from the first and second memories.
11. The processor of claim 10, wherein the third thread accesses the first bus interface while the first and second threads wait for data from the first and second memories.
12. The processor of claim 10, wherein a fourth thread of the microengine processes data in a data path of the network processor.
13. The processor of claim 5, wherein the microengines access either the first or second memory controllers based on characteristics of data.
14. The processor of claim 5, wherein the bus interface is coupled to first and second network devices, the bus interface being operable to receive a plurality of packets from the first and second network devices, the microengines being operable to process the packets in parallel.
15. The processor of claim 14, being operable to process each packet independently.
16. The processor of claim 14, wherein the bus interface stores transmit, receive and interrupt flags for each network device.
17. The processor of claim 5, wherein the bus interface comprises a first-in-first-out memory operable to store packet data and packet status from the bus.
18. The processor of claim 17, wherein the bus interface is operable to issue N requests for packet data and packet status to a network device coupled to the bus, each request for M bytes; receive packet data and packet status and store received packet data and packet status in an element of the first-in-first-out memory; detect an end-of-packet indicator; determine if the last M received bytes contain data or packet status; and if the last M received bytes contain packet data, issue another request of M bytes to retrieve packet status.
19. The processor of claim 5, wherein the bus interface comprises a hash unit operable to process hash requests from the microengines.
20. The processor of claim 5, wherein the bus interface comprises a plurality of state machines operable to transfer data to and from registers in the microengines.
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