Global planarization method

[0001] (1) Field of the Invention

[0002] This invention concerns methods for manufacturing substrates with large or difficult to planarize features such as large step height features, large width features or features of varying pattern densities. Such difficult to polish features are found in substrates such as photonic light circuits (PLC's) and micro-electro-mechanical systems (MEM's) which are also known as microelectromechanisms. The methods of this invention employ reverse mask etching and chemical mechanical polishing (CMP) techniques to planarize the difficult to polish feature with little dishing and with little edge loss.

[0003] (2) Description of the Art

[0004] Manufacturing processes for integrated circuits are well known in the art. Integrated circuits are typically formed on a substrate by the sequential deposition of conductive, semiconductive or insulating layers onto a silicon wafer. After deposition, each layer can be etched to create circuitry features. Integrated circuit fabrication processes generally require a subsequent layer to be deposited upon a planar surface of a previous layer. Chemical mechanical planarization (CMP) is used to planarize an integrated circuit layer in order to prepare it for the deposition of a subsequent layer.

[0005] The procedures used to manufacture integrated circuits are only starting to be applied to the manufacture of other electronic devices such as photonic light circuits (PLC's) and microelectronic mechanism (MEM's). However, the size (width and depth) and densities of features applied to such substrates are very different that features applied to IC's. This makes it impossible to use chemical mechanical polishing to planarize certain substrate layers without introducing undesirable effects and features such as dishing. During CMP of MEM's and PLC's, localized differences in polish pressure cause small features to polish faster than wider gaps, and oxide layers applied to narrow features polish slower than oxide applied to larger features in the same deposition step. Due to the high feature precision requirements of substrates such as PLC's and MEM's, undesirable features caused by CMP are a major and unsolved problem.

[0006] FIGS. 1A-1D are cross-section views of embodiments of electronic devices that include features that are currently difficult to planarized by CMP. FIG. 1A is an electronic substrate cross-section that includes a large width feature 100 that is associated with a plurality of features 102 having very small widths. The substrate is covered by a deposited material 104 that fills large width feature 100 and small width features 102 and is to be planarized by CMP. The typical result of CMP of the substrate of FIG. 1A is shown in FIG. 1B. FIG. 1B depicts a substrate 100 including material 104 located above-large width feature 100 is dished to a greater extent thereby leaving the substrate with an unacceptable deviation from planarity. Dishing of the large density of small width features also occurs and usually results in dissimilar trench depths. The dishing occurs primarily because material 104 applied over large width feature 100 typically has a thickness H1 that is less than the thickness H2 of material 104 above the plurality of narrow features 102. Furthermore, polishing material 104 until it is planar with the surface of substrate 101 often causes the corners 105 associated of large width feature 100 to become rounded. Such rounded corners are undesirable for most electronic substrates including photonic light circuits which require features with sharp edges to minimize undesirable features in subsequently applied layers and to improve the efficiency of subsequent lithography steps.

[0007] Problems also occur when applying CMP techniques to add a large step height features to electronic substrates. FIG. 1C shows an electronic substrate including a large step height feature 110. Large step height feature 110 will typically have a height of from 2 to about 50 microns. In order to deposit a layer of material 111 into large step height feature 110, the step height H3 (the peak to valley height) of the top surface of material applied to the surface of the substrate and into large step height feature 110 can be quite large. Using CMP material 111 to planarize it with the surface 112 of substrate 109 is very difficult because using CMP to polish a thick layer of material causes dishing 113 and undesirably rounded corners 114 at the junction of the large step height feature 110 and substrate surface 112.

[0008] As integrated circuit manufacturing techniques are applied to larger and more diverse electronic substrates such as PLC's and MEM's, there remains a need for processes and techniques for planarizing the surfaces of such substrates without substantial deviation from planarity.

[0009] In one aspect, this invention includes methods for adding at least one feature to a substrate. The method begins with a substrate having a base material layer and a first material layer applied on top of the base material layer wherein the first material layer has a thickness of at least 2 microns and wherein the first material layer has an exposed surface. A first photosensitive etch resistant material layer is deposited onto the exposed surface of the first material layer. A first mask is placed on first photosensitive etch resistant material layer surface wherein the first mask covers portions of the first photosensitive etch resistant material layer to form covered portions of the photosensitive etch resistant material layer and wherein the first mask leaves portions of the first photosensitive etch resistant material layer exposed to form exposed portions of the first photosensitive etch resistant material layer. The exposed portions of the photosensitive etch resistant material layer is activated to give activated portions and non-activated portions of the first photosensitive etch resistant material layer. A portion of the first photosensitive etch resistant material layer is removed to expose the underlying first material layer. Next, the exposed first material layer is etched to a predetermined thickness to form a feature. The remaining first photosensitive etch resistant material layer is removed from the substrate to expose the entire first material layer surface. Then a second material layer is deposited onto the surface of the first material layer in an amount that is sufficient to fill the first material layer feature. A second photosensitive etch resistant material layer is deposited onto the exposed surface of the second material layer. A second mask is placed over the second photosensitive etch resistant material layer to form exposed portions of second photosensitive etch resistant material layer and unexposed portions of second photosensitive etch resistant material layer. The exposed portions of the second photosensitive etch resistant material layer are activated to form activated and non-activated portions of the second photosensitive etch resistant material layer. The portion of the second photosensitive etch resistant material layer that does not lie above the feature to expose portions of the second material layer is removed, a portion of the exposed second material layer is stripped from the substrate to the optimized height, and the exposed surface of the substrate is planarized by chemical mechanical polishing.

[0014] The present invention concerns methods for manufacturing substrates having features that create planarization difficulties. Such features include large step-height features, large width features, a low density of features in proximity to a high density of features, planarization of photonic light circuits that require good wall sharpness and combinations thereof. Substrates that can be manufactured by the processes of this invention include, but are not limited to, photonic light circuits (PLC's) and microelectromechanisms (MEM's).

[0015] FIGS. 2A-2H are steps in one embodiment of processes of this invention for manufacturing substrates with large step-height features. In FIG. 2A, a substrate 10 is provided that includes a base material layer 12 and a first material layer 14 applied to the top of base material layer 12. First material layer 14 further includes an exposed surface 16. Typically, a feature, such as a large step height feature, a large width feature, a photonic light circuit feature or a MEM feature will be applied to first material layer 14.

[0016] A first photosensitive etch resistant material 18 is applied to exposed surface 16 of first material layer 14 in FIG. 2B. The first photosensitive etch resistant material 18 may be any positive or negative photosensitive material or any other material that is used in integrated circuit manufacturing to apply a resist pattern to a substrate surface. The photosensitive etch resistant material should be resistant to the materials that are used to etch first material layer 14 which lies below etch resistant material layer 18. The thickness of first photosensitive etch resistant material layer 18 will depend upon a number of factors including, but not limited to, the etch material used and the expected etch time. The deeper the feature that is being etched into first material layer 14, the thicker the photoresist layer 18 must be to protect the covered areas from being etched. If photoresist layer 18 is too thick problems arise in applying an etch resistant material layer of uniform thickness. It becomes difficult to form sharp edges in the underlying material that is being etched.

[0017] FIG. 2C shows substrate 10 after the lithography step, i.e., after a mask has been applied to first photosensitive etch resistant material layer 18 to form patterned openings 19 in etch resistant material layer 18. Openings 19 exposes or protects areas of first material layer surface 20 which are to be subsequently removed or protected from removal. This lithography step can be performed using a reversed mask of the underlying structure or by using the identical mask of the underlying structure and changing from a positive to a negative photoresist material and vice versa. In the lithography step, the masked surface is activated by exposure to light, heat or any other form of energy that is necessary to interact with the photosensitive etch resistant material layer 18 in a positive or negative matter. After activation, the activated or non-activated portions of first photosensitive etch resistant material layer 18 are removed from first material layer 14 to form openings 19 that expose a portion of first material layer 20.

[0018] In FIG. 2D, exposed first material layer portions 20 of FIG. 2C are etched down a predetermined thickness to form a trench 22. After trench 22 is formed, the remaining first photosensitive etch resistant material layer 18 can be removed from substrate 10. If first material layer 14 is selected from a matter that has photosensitive characteristics, then the etch resistant material layer is not required and the mask described above will be applied directly to the surface of first material layer 14. In this embodiment a mask is applied to the surface of first material layer 14, the mask substrate is processed by the lithography step described above to form activated and non-activated portions of first material layer 14 after which the activated or non-activated portions are removed to form trench 22. One example of a first material 14 that exhibits photosensitive characteristics are polyimides. Photosensitive materials such as polyimides can be applied to first material layer 14 by conformal layer application processes such as by a spin coating.

[0019] Trench 22 may be formed by any method known in the art for controllably and uniformly removing a portion of a material layer from an integrated circuit or other substrate. Useful methods for selectively and controllably removing a material layer from a substrate include, for example, reactive ion etching, wet etching and plasma etching electrochemical etching and deep reactive ion etching. A preferred method to remove a portion of first material layer 14 to form trench 22 is reactive ion etching.

[0020] A second material layer 24 is deposited onto the surface of first material layer 14 in FIG. 2E. Second material layer 24 is a conformal layer meaning here that the exposed surface of second material layer 24 is non planar because it follows the general shape the surface that it is covering. Second material layer 24 is applied to exposed surface 16 of first material layer 14 in an amount sufficient to fill trench 22 to a depth that exceeds the height of surface 16 of first material layer 14. A second material layer 24 may be applied to the surface of substrate 10 by any means known in the art for applying a conformal layer to a substrate. Non limiting examples of such methods include spin coating, jet coating, chemical vapor deposition, physical vapor deposition, electroplating and so forth. If second material layer 24 is a malleable material, then the substrate can undergo a reflow process to reduce magnitude of the peaks and valleys after application of second material layer 24 to substrate 10.

[0021] A second photosensitive etch resistant material layer 26 is applied to exposed surface 25 of second material layer 24 and processed by the lithographic techniques described above in a manner that protects the second material layer 24 located above trench 22 from being removed by etching. FIG. 2F shows substrate 10 following lithography and includes a second photosensitive etch resistant material portion 26 located above trench 22. In this lithography step, a second mask is used to image second photosensitive etch resistant material layer 26. The second mask may have essentially the same geometry as the first mask used to image first photosensitive etch resistant material layer 18 or it may be a negative of the first mask depending upon the type of etch resistant material used.

[0022] In order to reduce the complexity of the substrate manufacturing process the first and second photosensitive etch resistant materials will be the same material. In this preferred embodiment, the second mask used to image a second photosensitive etch resistant material layer will be essentially the reversed version of the first mask except that some overlay or underlay may be present to accommodate local effects due to pattern density and immediate effects due to feature sizes, and also to accommodate photobias of photosensitive materials.

[0023] In FIG. 2G, unprotected portions 27 of second material layer 24, i.e., those portions of second material layer 24 that are not covered by the second photosensitive etch resistant material layer are removed from substrate 10 until second material layer surface 24 is removed to a predetermined level that is essentially level with the center of trench 20. As a result, a small amount of second material layer 24 can remain associated with surface 16 of first material layer 14 that do not define a trench or some other feature.

[0024] Unprotected portions 27 of second material layer 24 are typically removed by etching techniques. They may be alternatively removed by CMPs techniques if the selected photosenstive etch resistant material portion 26 is extremely hard and resistant to CMP. Otherwise, etching is the preferred method of removing unprotected portion 27 of second material layer 24 from substrate 10.

[0025] Finally, the exposed surface of substrate 10 shown in FIG. 2G is polished using chemical mechanical planarization techniques until second material layer 24 becomes coplanar with first material layer 14 to create feature 28. The portion of second photosensitive etch resistant material layer 26 remaining on the surface of second material layer 24 shown in FIG. 2G can be stripped from second material layer 24 prior to chemical mechanical planarization or it may be removed as part of the chemical mechanical planarization procedure.

[0026] FIGS. 3A-3K are an alternative embodiment for the process steps shown in FIGS. 2A-2H. The process begins in FIG. 3A with the same substrate used in FIG. 2A. In the step shown in FIG. 3B, an etch and/or polishing stop material layer 40 is applied to the surface of substrate 10. In FIG. 3C, a photosensitive etch resistant material layer 42 applied to the surface of stop material layer 40. In FIG. 3D, the photosensitive etch resistant material layer 42, is exposed and developed to form an opening 44 that exposes the underlying stop layer material 40. In FIG. 3E, the exposed portion of stop layer 40 and the underlying first material layer 14 are etched to a predetermined level to create feature 46. At this point, the remaining photosensitive etch resistant material layer 42 can be removed from substrate 10 to form the substrate shown in FIG. 3F, or the processing of substrate 10 can continue.

[0027] Examples of useful stop materials include, but are not limited to polyimides, nitrides such as silicon nitride, polysilicon, silicon oxynitride (SiOn), silicon carbide (SiC), Al₂O₃, W, Ti, TiN, Ta, TaN, TiW, Mo or any other material that exhibits the desired stop material properties of etch and/or polishing resistance. The depth of stop layer 30 will depend upon the thickness and/or width of the feature being polished. Stop layer 30 may range from about 100 Å to about 1 micron in thickness. Preferably, stop layer 30 will have a thickness of from about 500 Å to about 5000 Å.

[0028] The remaining processing steps shown in FIGS. 3G-3K are essentially identical to those shown in FIGS. 2E-2H. The only difference is that second material layer 24 is planarized by CMP until it is planar with stop layer material 34. In an alternative embodiment, the photoresist layer portion 26 shown in FIG. 31 can be selected from a hard stop material layer that is imaged and etched to protect the underlying feature 22.

[0029] FIGS. 4A-4M are steps in alternative process of this invention for adding a feature to a substrate. The process depicted in FIGS. 4A-4M differs from the process depicted in FIGS. 2A-2H primarily in steps 4E through 4G in which a stop layer 30 is selectively applied to portions 32 of first material layer 14 in order to protect the exposed portions of first material layer 14 from being removed during the selective etching or CMP of second material layer 24 from substrate 10 in step 4K. Stop layer 30 may be any material that inhibits etching, that inhibits polishing, or both. For example, stop layer 30 may be chosen from a material that prevents first material layer 14 from being removed during selective etching of first or second material layer. Stop layer 30 may also be a polishing stop layer which protects first material layer from being overpolished during the CMP steps of the process of this invention.

[0030] According to FIG. 4E, stop material 30 is applied as a layer to exposed surface 16 of first material layer 14. In FIG. 4F, a third photosensitive etch resistant material layer 33 is applied to the surface of etch stop material layer 30. A mask is placed over third photosensitive etch resistant layer 33 as shown in FIG. 4G and the photosensitive material is activated as in the lithographic techniques described above in a manner that causes stop layer 30 associated with exposed surface 16 of first material layer to remain while allowing for the removal of stop layer material 30 located in trench 22. The resulting substrate 10 includes a stop material layer portion 34 associated with first material layer 14 is shown in FIG. 4H.

[0031] In a further optional embodiment of this invention, the process steps, shown in FIGS. 4G and 4H, of removing the portions of third photosensitive etch resistant layer 32 that remain after the lithography step is complete can be omitted. In this optional process embodiment, the remaining third photosensitive etch resistant material layer portions 34 will remain in place until they are removed by etching CMP techniques and/or following deposition of second material layer 24.

[0032] The processes of this invention are useful for manufacturing substrates including features with large step heights. The term “large step-height feature” refers to substrate features having a thickness of from about 2 to about 50 microns and more preferably from about 5 to about 15 microns. The processes of this invention are also useful for manufacturing substrates including large width features. The term “large width feature” refers to substrate features having width of from about 2 microns to about 30,000 microns and more preferably from about 10 to about 15,000 microns. In yet another embodiment, the process of this invention are useful for manufacturing substrates that include an area of low feature density adjacent to an area of high feature density.

[0033] Many useful electronic devices can be manufactured using the processes of this invention. The choice of device will largely determine the choice of materials used to manufacture the substrates. The processes of this invention are especially useful for manufacturing photonic light circuits (PLC's) and microelctromechanisms (MEM's). PLC's are typically manufactured using materials that are light transparent or semi-transparent. When the processes of this invention are used to manufacture PLC's, the first and second materials will generally be a transparent organic or inorganic material such as silicon, silicon oxynitride, polysilicon, polyimides, polymethylmethacrylate, perfluorinated polymers and polyacrylics, or silicon dioxide (SiO₂), doped oxide such as Ge, Er, ZnO, ZrO₂, InP, GaN, GaAIN, and mixtures thereof. The second material will have a different refractive index than the first material.

[0034] With MEM's, the first material may be selected from a sacrificial materials such as, GaAs, polysilicon, SiN, polyimide, photoresists, SiO₂, Cu, Al, AlGa, As and mixtures thereof while the second structural material will be selected from a metal or an alloy such as copper, aluminum, tungsten, polysilicon, SiH, GaAs, diamond, nickel and nickel compounds and so forth and alloys thereof.

[0035] The processes of this invention all use chemical mechanical polishing techniques to planarize the second material layer. In a typical chemical mechanical planarization (CMP) process, the substrate surface that is being polished is placed into contact with a rotating polishing pad. A carrier applies pressure against the backside of the substrate. During the polishing process, the pad and table are rotated while a downward force is maintained against the substrate back. A polishing composition is applied to the interface between the polishing pad and the substrate surface being polished. The polishing composition can be applied to the interface by applying the polishing composition to the polishing pad surface, to the substrate surface being polished or both. The polishing composition can be applied to the interface either intermittently or continuously and the application of the polishing composition can begin prior to or after the polishing pad is brought into contact with the substrate surface being polished. Finally, the term “applying a polishing composition” as it used in the specification and claims is not time limited and refers to the application of a polishing composition either before or after a polishing substrate is moved into contact with the surface being polished.

[0036] The polishing process further requires an abrasive material to assist in removing a portion of the substrate surface that has been softened by a reaction between the polishing composition and the substrate surface material. The abrasive may be incorporated into the polishing pad such as polishing pads disclosed in U.S. Pat. No. 6,121,143 which is incorporated herein by reference, it may be incorporated into the polishing composition, or both. Ingredients in the polishing composition or slurry initiate the polishing process by chemically reacting with the material on the surface of the substrate that is being polished. The polishing process is facilitated by the movement of the pad relative to the substrate as the chemically reactive polishing composition or slurry is provided to the substrate/pad interface. Polishing is continued in this manner until the desired film or amount of film on the substrate surface is removed.

[0037] The movement of the polishing pad in relationship to the substrate can vary depending upon the desired polishing end results. Often, the polishing pad substrate is rotated while the substrate being polished remains stationary. Alternatively, the polishing pad and the substrate being polished can both move with respect to one another. The polishing substrates and in particular the polishing pads of this invention can be moved in a linear manner, they can move in a orbital or a rotational manner or they can move in a combination of the directions.

[0038] The polishing composition is formulated to include chemicals that react with and soften the surface of the material being polished. The choice of polishing composition or slurry is an important factor in the CMP step. Depending on the choice of ingredients such as oxidizing agents, film forming agents, acids, bases, surfactants, complexing agents, abrasives, and other useful additives, the polishing slurry can be tailored to provide effective polishing of the substrate layer(s) at desired polishing rates while minimizing surface imperfections, defects and corrosion and erosion. Furthermore, the polishing composition may be selected to provide controlled polishing selectivities to other thin-film materials used in substrate manufacturing.

[0039] Examples of CMP polishing compositions and slurries are disclosed, in U.S. Pat. Nos. 6,068,787, 6,063,306, 6,033,596, 6,039,891, 6,015,506, 5,954,997, 5,993,686, 5,783,489, 5,244,523, 5,209,816, 5,340,370, 4,789,648, 5,391,258, 5,476,606, 5,527,423, 5,354,490, 5,157,876, 5,137,544, 4,956,313, the specifications of each of which are incorporated herein by reference.

[0040] The present invention has been described by means of specific embodiments, that would be understood that modifications may be made without departing from the spirit of the invention. The scope of the invention is not to be considered as limited by the description of the invention as set forth in the specification and examples, but rather as defined by the following claims.