Projection TV

[00002] This application is a divisional of U.S. application Ser. No. 09,255,778 filed Feb. 23, 1999, now U.S. Pat No. 6,617,648.

[00003] 1. Field of the Invention

[00004] The present invention relates to a projection TV receiver (hereinafter referred to as a projection TV) having semiconductor circuits that are constituted of thin-film transistors using a thin-film semiconductor.

[00005] 2. Description of the Related Art

[00006] In recent years, the technology of constructing semiconductor circuits by forming TFTs on a substrate having an insulating surface has made a rapid progress. A typical example of such semiconductor circuits is an electro-optical device such as an active matrix liquid crystal display device.

[00007] The active matrix liquid crystal display device is a monolithic display device in which a pixel matrix circuit and driver circuits are formed on the same substrate. Further, the system-on-panel which incorporates not only a pixel matrix circuit and driver circuits but also a memory circuit and logic circuits such as a clock generation circuit is now being developed.

[00008] With increased demand for electronic devices that utilize such display devices, keen competition for development of such electronic devices is now being made. A typical example of those electronic devices is a projector.

[00009] The projector is a device for applying strong light emitted from a backlight to a liquid crystal display device and projecting an image formed by the pixel matrix circuit of the liquid crystal display device onto a large-size screen.

[00010] The projector is generally classified into two types. The type in which an image is projected onto a rectangular screen whose sides measure several meters from the front side is called a front projector s (or a front projection TV). The type in which an image is projected onto a screen having a diagonal size of tens of inches from the back side is called a rear projector (or a rear projection TV).

[00011] Particularly in recent years, with the scheduled full digitization of ground-wave broadcasts, the rear projection TV has becomes the most promising candidate for future TVs for home use. This is based on a view that the rear projection TV will be advantageous over the CRT-type TV in terms of resolution, compactness, weight (lighter weight is preferable), set productivity, and power consumption (lower power consumption is preferable).

[00012] In view of the above-mentioned demand, an object of the present invention is to provide a projection TV that is highly reliable and easy to maintain.

[00013] According to a first aspect of the invention, there is provided a projection TV having at least an optical system and a liquid crystal module, wherein thin-film transistors constituting the liquid crystal module have a channel forming region that is a crystal structural body in which a plurality of rod-like or flat-rod-like crystals are arranged approximately parallel with each other in a particular direction; and wherein the thin-film transistors have an operation temperature of 80° C.-250° C.

[00014] According to a second aspect of the invention, there is provided a projection TV having at least an optical system and a liquid crystal module, wherein thin-film transistors constituting the liquid crystal module have a channel forming region that is a crystal structural body in which a plurality of rod-like or flat-rod-like crystals are arranged approximately parallel with each other in a particular direction and crystal lattices are continuous at most of grain boundaries; and wherein the thin-film transistors have an operation temperature of 80°C.-250° C.

[00015] The most important features of the invention are that the kink effect (the phenomenon that the operation is rendered out of control owing to hot carrier injection or the like) in a thin-film transistor is prevented or inhibited in a state that it is operating, and that a liquid crystal module that is constructed by using such thin-film transistors is applied to a projection TV.

[00016] The thin-film transistor utilized in the invention has a feature that the kink effect is prevented in a state that the thin-film transistor is operating in such a manner that charge that is captured in a gate insulating film by hot carrier injection or the like during operation is released by self-heating that is caused by the operation.

[00017] Because of the unique feature that the resistance to deterioration is increased by heating, this type of thin-film transistor is considered a switching element that is most suitable for use in a projection TV which is prone to accumulate inside heat that is generated by strong light coming from a backlight or by self-heating.

[00034] The present invention will be hereinafter described in detail by using embodiments.

[heading-00035] Embodiment 1

[00036] In this embodiment, a case where a pixel matrix circuit and peripheral circuits are constructed monolithically by forming TFTs according to the invention on a substrate having an insulating surface will be described mainly with reference to FIGS. 3A-3D, 4A-4D, and 5A-5C. In this embodiment, a CMOS circuit which is a basic circuit is used as an example of peripheral circuits such as driver circuits and logic circuits.

[00037] First, a quartz substrate 301 is prepared as a substrate having an insulating surface. A ceramic substrate formed with an insulating film of 0.5-5 μm in thickness, a silicon substrate, or the like can be used instead of a quartz substrate. Since low-grade silicon substrates as used in solar cells are inexpensive, they are effective for uses in which a transparent substrate is not needed, such as a reflection-type display device.

[00038] Reference numeral 302 denotes an amorphous silicon film. An adjustment is so made that the final thickness (after reduction by thermal oxidation) of the amorphous silicon 302 becomes 10-75 nm (preferably 15-45 nm). TFTs to be formed in this embodiment have a very thin active layer, and hence are FD (full depletion) TFTs in which the channel forming region is completely depleted in an on-state (i.e., a state that a channel is formed).

[00039] The amorphous silicon film 302 may be formed by low pressure CVD or plasma CVD. A silicon film containing germanium as represented by Si_1−xGe_x may be used instead of an amorphous silicon film.

[00040] Then, the amorphous silicon film 302 is crystallized in the following manner. The technique disclosed in Japanese Unexamined Patent Publication No. Hei. 7-130652 of the present inventors is used as a crystallization method. Although the method of either the first embodiment or the second embodiment of this publication can be used, it is preferable to utilize the technique described in the second embodiment (described in more detail in Japanese Unexamined Patent Publication No. Hei. 8-78329).

[00041] In the technique disclosed in the publication No. Hei. 8-78329, first, a mask insulating film 303 for selecting adding regions for a material for promoting crystallization of silicon is formed. To allow addition of a material for promoting crystallization of silicon, the mask insulating film 303 has openings at a plurality of positions. The positions of crystal regions can be determined by the positions of the openings.

[00042] A nickel (Ni) containing layer 304 is then formed by applying, by spin coating, a solution containing nickel as a material for accelerating crystallization of the amorphous silicon film 302 (see FIG. 3A). Examples of the material other than nickel are germanium (Ge), cobalt (Co), iron (Fe), palladium (Pd), platinum (Pt), copper (Cu), and gold (Au).

[00043] The material may be added by ion implantation or plasma doping using a resist mask. These techniques are effective in constructing a miniaturized circuit because they facilitate reduction of the areas occupied by addition regions for the material for promoting crystallization of silicon and control of the growth lengths of lateral growth regions.

[00044] After completion of the material adding step, hydrogen removal is performed at 450° C. for about 1 hour. Then, the amorphous silicon film 302 is crystallized by performing a heat treatment at 500° C.-700° C. (typically 550° C.-650° C.) for 4-24 hours in an inert atmosphere, a hydrogen atmosphere, or an oxygen atmosphere. In this embodiment, a heat treatment is performed at 570° C. for 14 hours in a nitrogen atmosphere.

[00045] In this step, crystallization of the amorphous silicon film 302 proceeds with priority from nickel addition regions 305 and 306, whereby crystal regions 307 and 308 are formed that have grown approximately parallel with the surface of the substrate 301 (see FIG. 3B). The inventors call the crystal regions 307 and 308 lateral growth regions.

[00046] After completion of the heat treatment for crystallization, the mask insulating film 303 is removed and patterning is performed to form island-like semiconductor layers (active layers) 309-311 each of which is part of the lateral growth region 307 or 308 in its entirety. Reference numeral 309 denotes the active layer of an n-type TFT to constitute a CMOS circuit, 310 denotes the active layer of a p-type TFT to constitute the CMOS circuit, and 311 denotes the active layer of an n-type TFT (pixel TFT) to constitute a pixel matrix circuit (see FIG. 3C).

[00047] After the formation of the active layers 309-311, a gate insulating film 312a that is an insulating film containing silicon is formed thereon (see FIG. 3C). The thickness (after increase in a later thermal oxidation step) of the gate insulating film 312a may be adjusted in a range of 20-250 nm. The film forming method may be a known vapor-phase method (plasma CVD, sputtering, or the like).

[00048] Then, as shown in FIG. 3D, a heat treatment (a process for gettering the material for promoting crystallization of silicon) is performed to remove or reduce the concentration of the material (nickel). In this heat treatment, a halogen element is contained in a processing atmosphere and the metal element gettering effect of the halogen element is utilized.

[00049] To allow the halogen element to fully exhibit its gettering effect, it is preferable to perform the above heat treatment at a temperature higher than 700° C. At a temperature of 700° C. or less, there is a possibility that a halogen compound in the processing atmosphere is hard to decompose and the gettering effect is not obtained.

[00050] Therefore, in this embodiment, the heat treatment is performed at a temperature higher than 700° C., preferably 800° C.-1,000° C. (typically 950° C.), for 0.1-6 hours (typically 0.5-1 hour).

[00051] In this embodiment, for example, a heat treatment is performed at 950° C. for 30 minutes in an oxygen atmosphere containing hydrogen chloride (HCl) at 0.5-10 vol % (typically 3 vol %). An HCl density higher than the above range is not preferable because asperity on approximately the same level as the thickness of the active layers 309-311 is formed on their surfaces.

[00052] The compound (gas) containing a halogen element other than HCl can be one or a plurality of compounds selected from HF, NF₃, HBr, Cl₂, ClF₃, BCl₃, F₂, Br₂ and the like.

[00053] It is considered that in this step nickel in the active layers 309-311 is removed in such a manner that it is gettered by the action of chlorine and escapes into the air in the form of volatile nickel chloride. After execution of this step, the nickel concentration in the active layers 309-311 is reduced to 5×10¹⁷ atoms/cm³ or less.

[00054] The value 5×10¹⁷ atoms/cm³ is a lower detection limit of SIMS (secondary ion mass spectroscopy). At present, we can only say that the nickel concentration is reduced down to the SIMS lower detection limit. However, it seems that actually the nickel concentration is reduced to 1×10¹⁴ to 1×10¹⁷ atoms/cm³.

[00055] When TFTs were manufactured experimentally and analyzed by the inventors, no influence of nickel on the TFT characteristics was found if the nickel concentration was 1×10¹⁸ atoms/cm³ or less (preferably 5×10¹⁷ atoms/cm³ or less). In this specification, an impurity concentration is defined by a minimum value of measurement results of a SIMS analysis.

[00056] During the above heat treatment, a thermal oxidation reaction proceeds at the interfaces between the active layers 309-311 and the gate insulating film 312a and, as a result, the thickness of the gate insulating film 312b increases by the thickness of a resulting thermal oxidation film. Forming a thermal oxidation film in this manner provides semiconductor/insulating film interfaces in which the concentration of interface states is very low, as well as an effect of preventing erroneous formation (edge thinning) of a thermal oxidation film at the edges of the active layers 309-311.

[00057] It is effective to improve the film quality of the gate insulating film 312b by performing a heat treatment at 950° C. for about 1 hour in a nitrogen atmosphere after the heat treatment in a halogen-containing atmosphere.

[00058] It was also confirmed by a SIMS analysis that the halogen element that had been used in the gettering step remained in the active layers 309-311 at a concentration of 1×10¹⁵ to 1×10²⁰ atoms/cm³, and that the halogen element exist at a high concentration between the active layers 309-311 and the thermal oxidation film formed by the heat treatment.

[00059] Thereafter, a metal film (not shown) having aluminum as the main component is formed and then patterned into starting members 313-315 of gate electrodes that will be formed later (see FIG. 4A). In this embodiment, an aluminum film containing scandium at 2 wt % is formed. Other examples of the metal film are a tantalum film and a conductive silicon film.

[00060] In this state, the technique disclosed in Japanese Unexamined Patent Publication No. Hei. 7-135318 is utilized in the following manner. This publication discloses a technique of forming source and drain regions and low-concentration impurity regions in a self-aligned manner by using oxide films formed by anodization.

[00061] First, porous anodic oxide films 316-318 are formed by performing anodization in a 3%-aqueous solution of oxalic acid in a state that a resist mask (not shown) that was used in patterning the aluminum film is left.

[00062] The thickness of the porous anodic oxide films 316-318 increases in proportion to the processing time. Since the resist mask remains on top of the gate electrode starting members 313-315, the porous anodic oxide films 316-318 are formed only on the side faces of the starting members 313-315. According to the technique of the publication No. Hei. 7-135318, the thickness of the porous anodic oxide films 316-318 is equal to the length of low-concentration impurity regions (also called LDD regions) that will be formed later. In this embodiment, the anodization is performed under such conditions that the thickness becomes 700 nm.

[00063] Thereafter, the resist mask (not shown) is removed and then anodization is performed in an electrolyte obtained by mixing tartaric acid in an ethylene glycol solution at 3%. In this step, dense, non-porous anodic oxide films 319-321 are formed. Since the electrolyte permeates the porous anodic oxide films 316-318, the non-porous anodic oxide films 319-321 are also formed inside the porous anodic oxide films 316-318, respectively.

[00064] The thickness of the non-porous anodic oxide films 319-321 is determined by the application voltage. In this embodiment, the anodization is performed with the application voltage set at 80 V so as to provide a thickness of about 100 nm.

[00065] Aluminum films 322-324 that remain after the above two anodization steps will substantially function as gate electrodes (see FIG. 4B).

[00066] After the state of FIG. 4B has been obtained, the gate insulating film 312b is etched by dry etching with the gate electrodes 322-324 and the porous anodic oxide films 316-318 used as masks. Then, the porous anodic oxide films 316-318 are removed. The end portions of gate insulating films 325-327 thus formed are exposed by the thickness of the porous anodic oxide films 316-318 (see FIG. 4C).

[00067] Then, impurity ions for imparting n-type conductivity (although phosphorus is used in this embodiment, arsenic may be used instead) are added in two steps as described below.

[00068] In this embodiment, the first impurity addition is performed at a high acceleration voltage and n⁻ regions are formed. Because of the high acceleration voltage (about 80 kV), impurity ions are added to not only the exposed surface portions of the active layers 309-311 but also their portions under the exposed end portions of the gate insulating films 325-327. An adjustment is so made that the P ion concentration of the n⁻ regions becomes 1×10¹⁸ to 1×10¹⁹ atoms/cm³.

[00069] Then, the second impurity addition is performed at a low acceleration voltage and n⁺ regions are formed. Because of the low acceleration voltage (about 10 kV), the gate insulating films 325-327 function as masks. An adjustment is so made that the sheet resistance of the n⁺ regions become 500 Ω or less (preferably 300 Ω or less).

[00070] As a result of the execution of the above steps, a source region 328, a drain region 329, low-concentration impurity regions 330, and a channel forming region 331 of an n-type TFT to constitute a CMOS circuit are formed. Further, a source region 332, a drain region 333, low-concentration impurity regions 334, and a channel forming region 302 of an n-type TFT (pixel TFT) are defined (see FIG. 4D).

[00071] In the state of FIG. 4D, the active layer of a p-type TFT to constitute the CMOS circuit has the same structure as the active layer of the n-type TFT to constitute the CMOS circuit.

[00072] Thereafter, a resist mask 336 is formed so as to cover the n-type TFTs and then impurity ions for imparting p-type conductivity (boron is used in this embodiment) are added.

[00073] This impurity addition step is performed in two steps as in the case of the above step. Since inversion from the n type to the p type is needed, B ions are added at a concentration several times higher than the concentration of P ions in the above step.

[00074] As a result, a source region 337, a drain region 338, low-concentr ation impurity regions 339, and a channel forming region 340 of the p-type TFT to constitute the CMOS circuit are formed (see FIG. 5A).

[00075] After completion of the active layers, impurity ions are activated by a combination of furnace annealing, laser annealing, lamp annealing, etc. At the same time, damage of the active layers that has been caused by the impurity adding steps is repaired.

[00076] Then, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an organic resin film, or a laminated film thereof is formed as an interlayer insulating film 341. In this embodiment, a laminated film is used in which a 25-nm-thick silicon nitride film is formed first and a 900-nm-thick silicon oxide film is deposited thereon.

[00077] Thereafter, contact holes are formed and then source electrodes 342-344 and drain electrodes 345 and 346 are formed (see FIG. 5B). In this embodiment, since the drain electrode 346 of the pixel TFT is used as a bottom electrode of an auxiliary capacitor, it is shaped so as to be suitable for-that purpose.

[00078] Then, a silicon nitride film 347 of 10-50 nm in thickness is formed and a 100-nm-thick capacitor electrode 348 is formed thereon to form the auxiliary capacitor. In this embodiment, a titanium film is used as the capacitor electrode 348 and the auxiliary capacitor is formed by the capacitor electrode 348 and the drain electrode 346.

[00079] The silicon nitride film 347 is suitable as a dielectric because it has large relative permittivity. An aluminum film or a chromium film may be used instead of a titanium film.

[00080] Since this embodiment is directed to the case of manufacturing a TFT substrate of a reflection-type liquid crystal display device, the space under a pixel electrode can be utilized freely unlike the case of a transmission-type device (i.e., it is not necessary to take the aperture ratio into consideration). This is the reason why the auxiliary capacitor can be formed in the above manner.

[00081] Then, an organic resin film as a second interlayer insulating film 349 is formed at a thickness of 0.5-3 μm. Examples of the organic resin are polyimide, acrylic, polyamide, and polyimideamide. Advantages of using the organic resin film are (1) a film can be formed easily, (2) the thickness can be increased easily, (3) the parasitic capacitance can be reduced because of small relative permittivity, and (4) the flatness is high.

[00082] Then, a pixel electrode 350 is formed by forming a conductive film on the interlayer insulating film 349 and patterning it. Since this embodiment is directed to the reflection-type device, a material having aluminum as the main component is used as the conductive film for forming the pixel electrode 350 to allow the pixel electrode 350 to function as a reflection film.

[00083] Then, the entire device is hydrogenated by heating the entire substrate at 350° C. for 1-2 hours in a hydrogen atmosphere, whereby dangling bonds in the films (particularly in the active layers) are compensated for. As a result of the execution of the above steps, CMOS circuits and a pixel matrix circuit are formed on the same substrate.

[heading-00084] Features of Crystalline Silicon Film used in the Invention

[00085] First, features of a TFT active layer used in the invention will be described. An active layer that has been subjected to the gettering process by a halogen element is a crystalline silicon film having a very characteristic structure.

[00086] Specifically, an observation by a TEM (transmission electron microscope) method shows that an active layer is a crystal structural body in which rod-like or flat-rod-like crystals are arranged macroscopically in a particular direction. The crystals are approximately parallel with each other.

[00087] The phrase “having regularity in a particular direction” means that the growth directions of a plurality of rod-like or flat-rod-like crystals are approximately the same. Since it is considered that carriers move through the inside of each rod-like or flat-rod-like crystal with priority as if they flew in a trough, it can be said that this crystal structure is anisotropic to carriers.

[00088] The inventors have obtained TFTs having very high operation speed by equalizing the growth direction to the channel direction (i.e., the direction in which carriers move when the TFT is in an on-state).

[00089] In the gettering process, the number of dangling bonds greatly decreases because at boundaries between crystals (i.e., grain boundaries) Si—Ni bonds are disconnected and recombination occurs to form Si—Si bonds. Therefore, lattice defects do not occur in most of grain boundaries and continuity is held there, and hence substantially no capturing of carriers occurs at grain boundaries. This means increase in carrier mobility, and TFT characteristics that will be described later are considered due to this type of crystal structure.

[00090] In connection with the above, the inventors observed lattice fringes of grain boundaries and their vicinities by an HR-TEM (high-resolution transmission electron microscope) method and found that lattice fringes of different crystals had one-to-one correspondence with the crystals and were continuous with each other. That is, it has been found that at grain boundaries crystal lattices have continuity and there are almost no crystal defects such as dangling bonds.

[00091] Further, it has been confirmed by a TEM observation that the number of internal defects in a crystal that has been subjected to the gettering process is smaller than in a crystal that has just been crystallized. This is considered due to an effect of the heat treatment at a high temperature (higher than 700° C.).

[00092] That is, the annealing step (in this embodiment, the step of FIG. 3D) that is executed at a temperature higher than the crystallization temperature in forming a crystalline silicon film of the invention plays an important role in reducing the number of defects in crystal grains. This will be explained below.

[00093] FIG. 17A is a TEM photograph, with a magnification of 250,000, of a crystalline silicon film in a state that the crystallization step of FIG. 3B has finished. A zigzagged defect indicated by an arrow is seen in a crystal grain in FIG. 17A (black portions and white portions appear owing to a difference in contrast).

[00094] Such defects are mainly stacking faults in which the stacking order of atoms of silicon crystal lattice planes is incorrect, and may be of other types such as a dislocation. The defect in FIG. 17A seems to be a stacking fault whose defect plane is parallel with the {111} plane. This is inferred from the fact that the zigzagged defect is bent at about 70°.

[00095] On the other hand, in a crystalline silicon film of the invention shown in FIG. 17B (same magnification), it is seen that there are almost no defects such as stacking faults and dislocations and the crystallinity is very high. This tendency holds over the entire film surface. Although it is difficult under the current technologies to zero the number of defects, the number of defects can be reduced to such an extent as to be substantially regarded as zero.

[00096] That is, the number of defects in each crystal grain is reduced to a negligible level in crystalline silicon films according to the invention, and they can be regarded as a single crystal or can be so regarded substantially because grain boundaries cannot be barriers to carrier movement because of a high level of continuity at the grain boundaries.

[00097] As described above, although the crystalline silicon films shown in the photographs of FIGS. 17A and 17B are approximately equivalent in the level of continuity at grain boundaries, they are much different in the number of defects in each crystal grain. The fact that crystalline silicon films of the invention exhibit much superior electrical characteristics to those of the crystalline silicon film of FIG. 17A is largely due to the difference in the number of defects.

[00098] The above discussion leads to a conclusion that the step of FIG. 3D is indispensable for the invention. The inventors have conceived the following models for the phenomena occurring in the step of FIG. 3D.

[00099] First, it is considered that in the state of FIG. 17A atoms of a material for promoting crystallization of silicon (typically nickel) are segregated at defects (mainly stacking faults) in each crystal grain, that is, many bonds in the form of Si—Ni—Si exist there.

[00100] However, Si—Ni bonds are disconnected when Ni atoms are removed from the defects as a result of execution of the material gettering process. Resulting excess dangling bonds of silicon atoms immediately form Si—Si bonds to establish a stable state. The defects disappear in this manner.

[00101] Naturally, it is known that defects in a crystalline silicon film disappear when thermal annealing has been performed at a high temperature. However, it is inferred that in the invention the silicon recombination occurs more smoothly because many dangling bonds are generated owing to disconnection of Si—Ni bonds.

[00102] It is considered that at the same time, excess silicon atoms that are generated when the crystalline silicon film is thermally oxidized move to defects to establish a stable state and greatly contribute to the formation of Si—Si bonds. This notion is known as the reason why the number of defects is small in each crystal grain of what is called a high-temperature polysilicon film.

[00103] The inventors have conceived a model that when a heat treatment has been performed at a temperature (typically 700° C.-1,100° C.) higher than the crystallization temperature, the crystalline silicon film is fixed to the underlying member and the adhesion is increased, as a result of which defects disappear.

[00104] The crystalline silicon film and a silicon oxide film as an undercoat film are different from each other in thermal expansion coefficient by a factor close to 10. Therefore, very strong stress is exerted on the crystalline silicon film when the crystalline silicon film is cooled after the conversion from the amorphous silicon film to the crystalline silicon film (FIG. 17A).

[00105] This will be explained below with reference to FIGS. 18A-18C. FIG. 18A shows a heat history that will be applied to a crystalline silicon film that has just been obtained by the crystallization step. First, the crystalline silicon film that has been crystallized at a temperature t₁ is cooled to room temperature in a cooling period (a).

[00106] FIG. 18B shows a crystalline silicon film in the cooling period (a). Reference numerals 80 and 81 denote a quartz substrate and a crystalline silicon film, respectively. It is considered that in this state, the adhesion at an interface 82 between the crystalline silicon film 81 and the quartz substrate 80 is not high and a number of defects are generated in each crystal grain owing to such insufficient adhesion.

[00107] That is, it is considered that the crystalline silicon film 81 that is being pulled because of the difference in thermal expansion coefficient is very easy to move on the quartz substrate 80 and defects 83 such as stacking faults and dislocations are easily generated by forces such as tensile stress.

[00108] The crystalline silicon film shown in FIG. 17A is in this state. Thereafter, the material gettering step is executed at a temperature t₂ as shown in FIG. 18A, whereby the defects in the crystalline silicon film disappear for the reasons described above.

[00109] It is an important fact that as a result of the execution of the material gettering step the crystalline silicon film is fixed to the quartz substrate to increase the adhesion therebetween. That is, it is considered that the gettering step also serves as a step of fixing the crystalline silicon film to the quartz substrate (underlying member).

[00110] After completion of the gettering and fixing step, the crystalline silicon film is cooled to room temperature in a cooling period (b). The cooling period (b) is different from the cooling period (a) that immediately follows the crystallization step in that an interface 85 between the quartz substrate 80 and an annealed crystalline silicon film 84 is in a state of very high adhesion (see FIG. 18C).

[00111] Since such high adhesion means that the crystalline silicon film 84 is completely fixed to the quartz substrate 80, defects are not generated even if stress is exerted on the crystalline silicon film 84 while it is cooled. That is, it can be prevented that defects are generated again.

[00112] Although FIG. 18A shows the process in which the temperature is decreased to room temperature after execution of the crystallization step, the temperature may immediately be increased after completion of the crystallization step to execute the gettering and fixing step. A crystalline silicon film according to the invention can also be obtained by this type of process.

[00113] A crystalline silicon film of the invention (see FIG. 17B) obtained in the above manner has a feature that the number of defects in each crystal grain is much smaller than that of a crystalline silicon film (see FIG. 17A) that has merely been subjected to crystallization.

[00114] The difference in the number of defects appears in the form of a difference in spin density in an electron spin resonance (ESR) analysis. At present, it has been found that the spin density of crystalline silicon films according to the invention is at most 5×10¹⁷ spins/cm³ or less (preferably 3×10¹⁷ spins/cm³ or less). It is presumed that actually the spin density is lower than the above measurement value, because the measurement value is close to the detection limits of currently available measuring instruments.

[00115] The crystalline silicon film of the invention having the above-described crystal structure and features is called a continuous grain silicon (CGS).

[heading-00116] Electrical Characteristics of TFT of the Invention

[00117] Next, a description will be made of results of studies on the electrical characteristics of thin-film transistors manufactured according to this embodiment. Measurements were conducted by using an instrument on the market (Type No. 4145B of Hewlett-Packard Co.).

[00118] First, a first test conducted by the inventors will be described. The inventors measured TFTs by using the above instrument and obtained curves (called a Id-Vg characteristic) that were plotted in such a manner that the horizontal axis represents the gate voltage and the vertical axis represents the drain current. During measurements, a control was so made that the temperature of a sample was kept at room temperature, by means of a thermo-chuck (having a temperature control function) for supporting the sample.

[00119] There were two kinds of TFT sizes: L/W=8/8 μm (FIG. 1A) and 8/200 μm (FIG. 1B), where L is the channel length and W is the channel width.

[00120] The degree of deterioration of TFTs were studied in such a manner that first an Id-Vg characteristic in the initial state (i.e., an initial characteristic) was measured and then a deterioration acceleration test was conducted that was 10 times of repetitive measurements under the same conditions.

[00121] FIGS. 1A and 1B show results of the test. In FIG. 1A, curve 101 (solid line) is an initial Id-Vg characteristic and curve 102 (broken line) is an Id-Vg characteristic measured after 10 times of repetitive measurements.

[00122] In FIG. 1A, curve 103 (solid line) and curve 104 (broken line) represent variations of field-effect mobility corresponding to the Id-Vg characteristics 101 and 102, respectively. The mobility is an index of operation speed of a TFT and is obtained by a theoretical calculation from data of an Id-Vg characteristic.

[00123] Similarly, in FIG. 1B, curve 105 (solid line) and 106 (broken line) are an initial Id-Vg characteristic and an Id-Vg characteristic measured after the acceleration test, and curve 107 (solid line) and curve 108 (broken line) are initial mobility and mobility after the acceleration test.

[00124] Knowledge that the inventors have acquired from the above test results will be described below. In the case of FIG. 1A, while the maximum mobility value close to 300 cm²/Vs is obtained in the initial state, the maximum mobility value is decreased to about 220 cm²/Vs after the acceleration test. The drain current in the gate voltage range below 0 V (called an off-current here) is approximately doubled after the acceleration test.

[00125] In contrast, in the case of FIG. 1B, there is no large difference between the initial mobility (curve 107) and the mobility after the acceleration test (curve 108); that is, there is almost no deterioration. No large variation is found in the off-current, either.

[00126] The above results show that as for the acceleration test that is 10 times of repetitive measurements a TFT having a larger channel width is more resistant to deterioration. It is noted that the inventors confirmed this tendency in tens of TFTs.

[00127] After studying differences in TFT properties due to a difference in channel width based on the above results, the inventors paid attention to self-heating that is caused by large current when the channel width is large. The inventors intentionally heated TFTs having the same structure and conducted acceleration tests (repetitive measurements) in the heated state.

[00128] FIGS. 2A and 2B show results of the acceleration tests. FIG. 2A shows results obtained at room temperature with a triple-gate TFT of L/W=6.6/2 μm. FIG. 2B shows results obtained with the same triple-gate TFT that was heated to 125° C.

[00129] As shown in FIG. 2A, in the case of the acceleration test at room temperature, while no variation is found between an initial Id-Vg characteristic 201 (solid line) and an Id-Vg characteristic 203 (broken line) after the acceleration test, mobility 204 (broken line) after the acceleration test is deteriorated from initial mobility 203 (solid line) by an amount close to 20% in terms of the maximum value.

[00130] In contrast, as shown in FIG. 2B, in the case of the acceleration test at 125° C., almost no variation is found between an initial Id-Vg characteristic 205 (solid line) and an Id-Vg characteristic 206 (broken line) after the acceleration test, and no large variation is found between initial mobility 207 (solid line) and mobility 208 (broken line) after the acceleration test.

[00131] These results verify that TFTs used in the invention have the property that they become more resistant to deterioration when they are heated. This effect becomes remarkable at 80° C. or more, and occurs up to about 250° C. According to experiments by the inventors, this effect was stable in a temperature range of 100° C.-200° C.

[00132] Therefore, as for the test results of FIGS. 1A and 1B, an explanation is made that the TFT having a larger channel width was self-heated and its deterioration was thereby reduced. When a TFT whose channel width is 100 μm or more is observed with an emission microscope, light emission due to heating is found in the channel and its vicinity when it is in an on-state. This is probably light emission due to heating to 100° C. or more.

[00133] In experiments in which the channel length L and the channel width W were set at various values, the above effect of the invention was obtained when the channel width was 100 μm or more. In particular, the effect was remarkable when a relationship L/W≦0.01 is satisfied (for example, W≧200 μm if L=2 μm).

[00134] The effect that deterioration is prevented or inhibited by heat is a phenomenon that is specific to TFTs used in the invention. When the inventors conducted similar tests on what is called low-temperatu re polysilicon TFTs, threshold voltages V_th were much shifted by heating and the TFTs were rendered of no use.

[00135] The above tests were conducted on TFTs using a low-temperature polysilicon film that was crystallized by using a material for promoting crystallization of silicon such as nickel and a low temperature polysilicon film that was crystallized only by laser annealing without using a material for promoting crystallization of silicon, and results of the two kinds of TFTs were the same.

[heading-00136] Inference Relating to TFT of the Invention

[00137] The above-described deterioration of a TFT is particularly remarkable in n-type TFTs in which carriers are electrons. As a matter of fact, almost no deterioration was found under any conditions in p-type TFTs manufactured according to this embodiment.

[00138] This is readily understood from the fact that typical causes of TFT deterioration are CHE (channel hot electron) injection and (DAHC) drain avalanche hot carrier) injection.

[00139] The CHE injection is a phenomenon that electrons in the channel are given high energy by an electric field in the direction along the channel and finally injected into the gate insulating film. The DAHC injection is a phenomenon that electron-hole pairs that are generated by collision between high-energy electrons and lattices and resulting ionization of the high-energy electrons are injected into the gate insulating film (refer to Mistumasa Koyanagi: “Submicron Devices II,” Maruzen Co., Ltd., p. 125, 1998).

[00140] The above deterioration phenomenon occurs in such a manner that electrons injected in the gate insulating film cause variations in electrical characteristics. It is considered that deterioration due to the CHE injection and the DAHC injection proceeded also in the above-described deterioration acceleration test that is repetitive measurements.

[00141] The inventors infer that the reason why the deterioration due to the CHE injection and the DAHC injection can be inhibited by heating a TFT that is used in the invention is that thermal energy causes electrons captured in the gate insulating film to be re-emitted to the active layer.

[00142] Being of the full depletion (FD) type, TFTs used in the invention have a feature that the carrier mobility is very large. As a matter of fact, the mobility values shown in FIGS. 1A-1B and 2A-2B exceed 200 cm²/Vs on average. Those TFTs realize electrical characteristics that are never attained by general TFTs.

[00143] On the other hand, those TFTs are prone to be deteriorated by the CHE injection and the DAHC injection. TFTs that exhibit very high performance and are highly reliable are realized by preventing or inhibiting such deterioration by heating those.

[heading-00144] Embodiment 2

[00145] This embodiment is directed to a manufacturing method for obtaining a gettering effect by the element of phosphorus in addition to the gettering effect by a halogen element that has been described in the first embodiment. This embodiment will be described with reference to FIGS. 6A-6E.

[00146] First, the steps to the gettering process by a halogen element are executed in the same manner as in the first embodiment. In FIG. 6A, reference numerals 601-603 denote a quartz substrate, an active layer, and a gate insulating film, respectively.

[00147] Then, a gate electrode 604 is formed that is a laminated film of a tantalum film and a film having tantalum as the main component. Then, an anodic oxide film 605 is formed by anodizing the surface of the gate electrode 604 (see FIG. 6A). The anodic oxide film 605 functions as a protective film.

[00148] Then, the gate insulating film 602 is etched by dry etching with the gate electrode 604 used as a mask. Thereafter, impurity regions 606 and 607 are formed by adding phosphorus by ion implantation (see FIG. 6B).

[00149] Then, sidewalls 608 are formed by forming a thick silicon nitride film and etching it back by dry etching. Subsequently, a source region 609 and a drain region 610 are formed by adding phosphorus again (see FIG. 6C).

[00150] In the second phosphorus doping step, phosphorus is not added to the regions under the sidewalls 608 and an a pair of low-concentrat ion impurity regions 611 containing phosphorus at a lower concentration than the source region 609 and the drain region 610 are formed there. The region under the gate electrode 604 becomes a channel forming region 612.

[00151] After the state of FIG. 6C has been obtained in the above manner, a heat treatment is performed at 450° C.-650° C. (typically 600° C.) for 8-24 hours (typically 12 hours).

[00152] Although this heat treatment is intended to cause gettering of the material for promoting crystallization of silicon (in this embodiment, nickel) by the element of phosphorus, at the same time the impurity is activated and damage of the active layer caused by the ion implantation operations is repaired.

[00153] In this step, the heat treatment causes nickel remaining in the channel forming region 612 to move to the source region 609 and the drain region 610, where nickel is gettered and inactivated. That is, nickel remaining inside the channel forming region 612 can be removed.

[00154] Since the source region 609 and the drain region 610 can function as electrodes as long as they are conductive, whether the nickel is present in or absent from the source region 609 and the drain region 610 does not influence the electrical characteristics. This is the reason why the source region 609 and the drain region 610 can function as gettering sites.

[00155] After the state of FIG. 6D has been obtained in the above manner, an interlayer insulating film 613, a source electrode 614, and a drain electrode 615 are formed in the same manner as in the first embodiment, whereby a thin-film transistor is completed as shown in FIG. 6E.

[00156] Although in this embodiment tantalum is used as the material of the gate electrode, a conductive crystalline silicon film may be used instead. Further, the method of forming the low-concentration impurity regions is not limited to the method of this embodiment.

[00157] The most important feature of this embodiment is that the material remaining in the channel forming region is moved to the source and drain regions and gettered there. This aspect of the invention has been conceived by paying attention to the metal element gettering effect of the element of phosphorus. This embodiment is directed to the n-type TFT. In the case of the p-type TFT, it is necessary to add both phosphorus and boron to the source and drain regions because addition of only boron cannot provide a gettering effect.

[heading-00158] Embodiment 3

[00159] This embodiment is directed to cases where TFT structures different than in the first embodiment are employed. FIG. 7A shows a structure in which sidewalls are used in forming low-concentration impurity regions.

[00160] In this case, non-porous anodic oxide films are formed in the state of FIG. 4A and the gate insulating film is etched with the gate electrodes and the anodic oxide films used as masks. In this state, impurities are added to form n⁻ regions and p⁻ regions.

[00161] Thereafter, sidewalls 701-703 are formed by etch back and then impurities are added to form n⁺ regions and p⁺ regions. As a result of those steps, low-concentration impurity regions (n⁻ regions and p⁻ regions) are formed under the sidewalls 701-703.

[00162] In the example of FIG. 7A, metal silicide layers 704-706 formed by a known salicide (self-aligned silicide) technique. Example metals for formation of a salicide structure are titanium, tantalum, tungsten, and molybdenum.

[00163] FIG. 7B shows a structure that is characterized in that gate electrodes 707-709 are crystalline silicon films that are given one conductivity type. Usually, the gate electrodes 707-709 are given n-type conductivity. There may be formed dual-gate TFTs in which the gate electrodes of an n-type TFT and a p-type TFT are given different conductivity types.

[00164] A salicide structure is also employed in the structure of FIG. 7B. In this case, metal silicide layers 710-712 are also formed on the top surfaces of the respective gate electrodes 707-709.

[00165] The structures of this embodiment are so designed as to be suitable for TFTs having high operation speed. In particular, the salicide structure is a technique that is very useful in realizing operation frequency of several gigahertz.

[heading-00166] Embodiment 4

[00167] This embodiment is directed to cases where an auxiliary capacitor having a different structure than in the first embodiment is formed.

[00168] FIG. 8A shows a structure in which a drain region 801 of an active layer is so formed as to be larger than necessary and part of the drain region 801 is used as the bottom electrode of an auxiliary capacitor. In this case, a gate insulating film 802 is laid on the drain region 801 and a capacitor electrode 803 is formed on the gate insulating film 802. The capacitor electrode 803 is made of the same material as the gate electrodes.

[00169] The portion of the drain region 801 with which the auxiliary capacitor is to be formed may be rendered conductive either by adding an impurity to it in advance or by utilizing an inversion layer that is formed by applying a constant voltage to the capacitor electrode 803.

[00170] Since the structure of FIG. 8A is of a reflection-type liquid crystal display device, the auxiliary capacitor can be formed by utilizing the space on the back side of the pixel electrode to the maximum and hence a very large capacitance can be secured. Although naturally this structure can also be applied to a transmission-type liquid crystal display device, in such a case sufficient care should be taken of the fact that the aperture ratio decreases if the area occupied by the auxiliary capacitor is made unduly large.

[00171] FIG. 8B shows a structure of a transmission-type liquid crystal display device. In this structure, a drain electrode 804 is used as the bottom electrode of an auxiliary capacitor and a silicon nitride film 805 and a black matrix 806 is formed on the drain electrode 804. An auxiliary capacitor is formed by the drain electrode 804 and the black matrix 806.

[00172] Thus, the structure of FIG. 8B is characterized in that the black matrix 806 also serves as the top electrode of the auxiliary capacitor.

[00173] Because of the transmission-type device, a pixel electrode 807 is a transparent conductive film (e.g., an ITO film).

[00174] The structure as shown in FIG. 8B can increase the aperture ratio because the auxiliary capacitor, which tends to occupy a large area, is formed on a TFT. Further, since large-permittivity silicon nitride film that is as thin as about 25 nm can be utilized, a very large capacitance can be secured in a small area.

[heading-00175] Embodiment 5

[00176] This embodiment is directed to a case where the invention is applied to a thin-film transistor having a different structure than in the first embodiment. This embodiment will be described with reference to FIGS. 9A-9E.

[00177] First, a gate electrode 902 is formed on a quartz substrate 901. The gate electrode 902 is formed as a highly heat-resistant electrode that is made of tantalum, silicon, or the like so as to be able to sustain later thermal oxidation steps.

[00178] Then, a gate insulating film 903 is formed so as to cover the gate electrode 902 and a 50-nm-thick amorphous silicon film 904 that will become an active layer is formed on the gate insulating film 903. Thereafter, a mask insulating film 905 having an opening is formed and then a nickel-containing layer 906 is formed, in the same manner as in the first embodiment.

[00179] After the state of FIG. 9A has been obtained in the above manner, a heat treatment for crystallization is performed, whereby a crystalline silicon film 907 that is a lateral growth region is obtained (see FIG. 9B).

[00180] Thereafter, the mask insulating film 905 is removed and then a heat treatment is performed in an atmosphere containing a halogen element. The conditions of the heat treatment may be the same as in the first embodiment. In this step, nickel is removed from the crystalline silicon film 907 into the vapor phase through gettering (see FIG. 9C).

[00181] After completion of the gettering process, an active layer 908 that is part of the lateral growth layer its entirety is formed by patterning and a silicon nitride film as a channel stopper 909 is formed thereon (see FIG. 9D).

[00182] After the state of FIG. 9D has been obtained, a crystalline silicon film having n-type conductivity is formed and patterned into a source region 910 and a drain region 911. Then, a source electrode 912 and a drain electrode 913 are formed.

[00183] Finally, the entire device is subjected to a heat treatment in a hydrogen atmosphere, whereby an inverted staggered structure TFT is completed as shown in FIG. 9E. Having the active layer that is the same crystalline silicon film as in the first embodiment, the inverted staggered structure TFT of this embodiment also has the feature that the resistance to deterioration is improved when it is heated.

[00184] The structure of the inverted staggered structure TFT described in this embodiment can be applied to the structures shown in FIG. 5C (embodiment 1), FIGS. 7A and 7B (embodiment 3), FIGS. 8A and 8B (embodiment 4).

[00185] Moreover, the structure of the inverted staggered structure TFT described in this embodiment is just an example and the invention is not limited to such a case. Further, the invention can be applied to not only the inverted staggered structure TFT but also other kinds of bottom-gate TFTs.

[heading-00186] Embodiment 6

[00187] This embodiment is directed to a case where a liquid crystal panel is formed by using TFTs according to any of the first to fifth embodiments. FIG. 10 is a simplified sectional view of an active matrix liquid crystal panel in which a CMOS circuit is formed in an area where driver circuits and logic circuits are formed and a pixel TFT is formed in an area where a pixel matrix circuit is formed.

[00188] Since the structures (TFT structures) of a CMOS circuit and a pixel matrix circuit have already been described in the first embodiment, only necessary portions will be described in this embodiment.

[00189] First, the state of FIG. 5C is obtained by the manufacturing steps of the first embodiment. A party who practices the invention can make desired modifications such as employing a multi-gate structure in the pixel TFT.

[00190] Then, an alignment film 1001 is formed as a preparation on the TFT substrate side. Then, an opposed substrate is prepared that is composed of a glass substrate 1002, a transparent conductive film 1003, and an alignment film 1004. If necessary, a black matrix and color filters (omitted in FIG. 10) are formed on the opposed substrate side.

[00191] The active matrix substrate (TFT substrate) and the opposed substrate thus prepared are bonded to each other by a known cell assembling step. A liquid crystal material 1005 is sealed in a space between the two substrates, whereby a liquid crystal panel shown in FIG. 10 is completed.

[00192] Various known liquid crystal materials such as twistednematic liquid crystal, polymer dispersion liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, and a mixture of ferroelectric and anti-ferroelectric liquid crystals may be used in the liquid crystal panel of this embodiment.

[00193] Moreover, the liquid crystal material needs to be selected in accordance with the operation mode (ECB mode, guest-host mode, or the like) of the liquid crystal. With an assumption that the liquid crystal panel is used in an environment where the liquid crystal panel is likely heated (for example, a case where it is used in a projection TV), it is preferable to use a liquid crystal material that is high in heat resistance.

[00194] As described later, where the invention is applied to a rear projection TV, an advantage is obtained that the use of TFTs as described in the first embodiment makes it unnecessary to use an air-cooling fan (i.e., the reliability is high in a temperature range of about 80° C.-250° C.).

[00195] Therefore, to effectively utilize the invention, it is necessary to use a liquid crystal material whose clearing point (the temperature at which a liquid crystal material starts to be isotropic) is at least 100° C. or more (preferably 150° C. or more).

[00196] FIG. 11 shows a simplified appearance of an active matrix substrate as shown in FIG. 5C. In FIG. 11, reference numeral 1101 denotes a quartz substrate; 1102, a pixel matrix circuit; 1103, a source driver circuit; 1104, a gate driver circuit; and 1105, a logic circuit.

[00197] In a broad sense, the logic circuit 1105 includes all logic circuits that are constituted of TFTs. However, for distinction from circuits that are conventionally called a pixel matrix circuit and a driver circuit, in this embodiment this term means signal processing circuits (a D/A converter etc.) other than those circuits.

[00198] The liquid crystal panel thus formed is provided with FPC (flexible print circuit) terminals as external terminals. In general, a liquid crystal module is a liquid crystal panel to which an FPC is attached.

[heading-00199] Embodiment 7

[00200] This embodiment is directed to an example of an optical system (optical engine) for projecting an image that is displayed on a liquid crystal module onto a screen in a projection TV. FIGS. 12A and 12B show an example of a single-panel optical engine in which a microlens array is provided on the opposed substrate side.

[00201] Strong light emitted from a lamp light source 11 such as a halogen lamp or a metal halide lamp enters dichroic mirrors 12-14. In this embodiment, an R (red) component beam is reflected by the dichroic mirror 12, a B (blue) component beam is reflected by the dichroic mirror 13, and a G (green) component beam is reflected by the dichroic mirror 14 (or a full-reflection mirror).

[00202] The dichroic mirrors 12-14 are arranged so as to form slight angles with each other rather than parallel with each other, whereby the R, B, and G component beams enter a liquid crystal panel 15 at different incident angles. (FIG. 12A).

[00203] The liquid crystal panel 15 is composed of a microlens array 16, an opposed substrate 17, a liquid crystal layer 18, and an active matrix substrate 19. Reference numerals 20-22 denote pixels corresponding to R, B, and G, respectively. (FIG. 12B)

[00204] The beams that have entered the liquid crystal panel 15 at the incident angles that are slightly different from each other are focused at three different positions after passage through the microlens array 16. Therefore, for example, it is possible to input only the R component beam selectively to the corresponding pixel 20 by disposing the pixel 20 at the position where the R component beam is focused.

[00205] With such arrangement design, the R, G, and B component beams are incident selectively on the respective pixels 20-22. This special arrangement enables a single-panel optical engine without the need for using color filters.

[00206] Light beams carrying information of the respective pixels are formed as a result of passage through the liquid crystal panel 15. The resulting light beams are converged by a Fresnel lens 23 and guided to a projection lens (not shown). R, G, and B images are finally combined on the screen.

[00207] With the configuration of this embodiment, because it is not necessary to use color filters, the screen can be made several times brighter than in conventional product types having the equivalent resolution.

[heading-00208] Embodiment 8

[00209] This embodiment is directed to a case where a three-panel optical engine is constructed by using a transmission-type liquid crystal module. This embodiment will be described with reference to FIG. 13.

[00210] In FIG. 13, reference numeral 31 denotes a lamp light source; 39 and 33, R and G dichroic mirrors, respectively; 34-36, full-reflection mirrors; 37-39, R, G, and B transmission-type liquid crystal panels, respectively; 40, a dichroic prism; and 41, a projection lens.

[00211] Strong light is emitted from the lamp light source 31 and only the R component beam is reflected by the dichroic mirror 32. The R component beam is changed in traveling direction by the full-reflectio n mirror 36 and enters the R liquid crystal panel 37.

[00212] Only the G component beam is reflected by the G dichroic mirror 33 and enters the G liquid crystal panel 38.

[00213] The B component beam that has passed through the dichroic mirrors 32 and 33 is reflected by the full-reflection mirrors 34 and 35 and enters the B liquid crystal panel 39.

[00214] Light beams carrying video information that have passed through the R, G, and B liquid crystal panels 37-39, respectively, in the above manner are recombined by the dichroic prism 40 and projected onto a screen by a projection lens.

[00215] In the optical engine shown in FIG. 13, optical system tenses such as a condenser lens are omitted. Actually, optical adjustments are made by a fly-eye lens, a condenser lens, etc.

[00216] Although this type of optical system using a dichroic prism requires high-level techniques to secure the accuracy of the prism, it is very useful in utilizing light effectively. Further, a projection lens can be made smaller because of, for example, advantages that color composition is made easier and the back focal length of the projection lens can be shortened.

[00217] Therefore, it can be said that the configuration of this embodiment is advantageous in terms of reduction in the size and weight of the optical engine and the reduction in size leads to a marked advantage in cost.

[00218] Naturally it is possible to construct an optical engine without using a dichroic prism. Modifications of this kind are just design items that a party who practice the invention can change properly when necessary.

[heading-00219] Embodiment 9

[00220] This embodiment is directed to a case where a reflection-type three-panel optical engine is used. This embodiment will be described with reference to FIG. 14, where optical system lenses such as a fly-eye lens and a condenser lens are omitted as in the case of the eighth embodiment.

[00221] In FIG. 14, reference numeral 42 denotes a lamp light source; 43 and 44, dichroic mirrors; 45, a full-reflection mirror; 46-48, polarizing beam splitters (PBSs); 49-51, R, G, and B liquid crystal panels; 52, a dichroic prism; 53, a projection lens.

[00222] Strong light is emitted from the lamp light source 42 and only the R component beam is transmitted by the dichroic mirror 43 and G and B component beams are reflected by the same. Only the G component beam is reflected by the dichroic mirror 44.

[00223] The R component beam that has passed through the dichroic mirror 43 is reflected by the full-reflection mirror 45 and input to the polarizing beam splitter 46. The G and B component beams are input to the polarizing beam splitters 47 and 48, respectively.

[00224] The polarizing beam splitters 46-48 have a function of separating input light into P-polarization light and S-polarization light as well as a property of transmitting only the P-polarization light. Therefore, the R, G, and B liquid crystal panels 49-51 receive R, G, and B S-polarization beams, respectively.

[00225] In each of the liquid crystal panels 49-51, liquid crystal molecules are so aligned as to reflect incident light without causing any change in polarization direction when a pixel is in an off-state. When a pixel is in an on-state, the orientation of liquid crystal molecules is changed and the polarization direction of output light is changed accordingly.

[00226] Therefore, only portions of the S-polarization beams incident on portions of the liquid crystal panels 49-51 where pixels are in an on-state are converted to P-polarization beams through reflection. That is, only light beams that have been reflected by on-state pixels can pass through the polarization beam splitters 46-48.

[00227] Light beams carrying video information that have passed through the polarizing beam splitters 46-48 in this manner are combined by the dichroic prism 52 and input to the projection lens 53. Combined light is projected onto a screen by the projection lens 53.

[00228] Because of the use of the dichroic prism, the reflection-type optical engine of this embodiment can also be reduced in size and weight. Also in this embodiment, a modification that does not use a dichroic prism is just a change in a non-essential design item.

[heading-00229] Embodiment 10

[00230] This embodiment is directed to a projection TV set that incorporates an optical engine according to any of the seventh to ninth embodiments. This projection TV is one that is commonly called a rear projection TV. FIG. 15A is a side view showing an internal structure in a simplified manner. FIG. 15B is a perspective view from above.

[00231] In FIGS. 15A and 15B, reference numeral 61 denotes a main body; 62, an optical engine; 63, a reflector; and 64, a screen. Although actually a complex system is configured with addition of other optical systems, only the general configuration will be described in this embodiment.

[00232] The optical engine 62 may have any of the configurations shown in FIGS. 12-14. The liquid crystal module incorporated in the optical engine 62 includes the liquid crystal panel(s) having the structure as described in the sixth embodiment.

[00233] This liquid crystal module can be configured so as to deal with any of NTSC, PAL and digital video signals by using a proper semiconductor circuit that is constituted of TFTs (described in the first embodiment) and integrated with other circuits on the same substrate.

[00234] Further, even if a video signal is one that accommodates different resolutions such as in XGA, SXGA, and UXGA, reduction in resolution can be avoided by taking a proper measure such as black-displaying unnecessary portions by means of a logic circuit or the like.

[00235] The most important advantage of the projection TV of the invention is that an air-cooling fan for cooling the liquid crystal panel(s) is not necessary.

[00236] Usually, in an optical engine, very strong light is applied to the liquid crystal panel and hence the liquid crystal panel is heated to a very high temperature. In general projection TVs, the liquid crystal panel is cooled with an air-cooling fan or the like during operation because excessive application of heat deteriorates the TFT characteristics and impairs the reliability to a large extent.

[00237] However, since the air-cooling fan sucks external air, it has a problem of sucking also minute dust etc. in the air. That is, there is a problem that dust that has been sucked by the air-cooling fan may stick to the back side of the screen to deteriorate the image quality.

[00238] In particular, this problem is very serious in rear projection TVs that are commonly used in homes. That is, usual home users are obliged to request a manufacturer or an electric appliance store to perform maintenance work because they cannot do it by themselves.

[00239] In contrast, the projection TV of this embodiment enables a configuration that does not require an air-cooling fan, because it uses TFTs whose reliability increases when they are heated as described in the first embodiment. Since it is not necessary to take external air into the inside of the main body, the problem that dust sticks to the back side of the screen can be avoided.

[00240] Even with the configuration that does not use an air-cooling fan, almost no deterioration due to temperature increase occurs in the TFTs and hence the liquid crystal module is kept very high in reliability. Therefore, this embodiment realizes a projection TV that is kept highly reliable even if the TFT operation temperature (i.e., the environment temperature of the TFTs during operation) is increased to 80° C.-250° C. (preferably 100° C.-200° C.).

[00241] It goes without saying that also in this case the clearing point of the liquid crystal material used in the liquid crystal panel is 100° C. or more (preferably 150° C. or more).

[heading-00242] Embodiment 11

[00243] This embodiment is directed to a projection TV having a different configuration than in the 10th embodiment. This projection TV is one that is commonly called a front projection TV.

[00244] FIGS. 16A and 16B show a simplified configuration of a front projection TV. In FIGS. 16A and 16B, reference numerals 71-73 denote a projection apparatus main body, a projection lens, and a screen, respectively.

[00245] An optical engine as described in any of the seventh to ninth embodiments is provided inside the apparatus main body 71. Light carrying video information is projected onto the screen 73 by the projection lens 72.

[00246] In this embodiment, a three-panel transmission-type optical engine (eighth embodiment) is used as an example of the internal structure of the apparatus main body 71.

[00247] The most important feature of front projection TVs is that an image is displayed on a large-size screen, and hence front projection TVs have a great demand for conference or presentation purposes. Typical screen sizes are 100 inches and 200 inches.

[00248] However, general front projection TVs necessarily require a measure against thermal deterioration because heat is easily accumulated inside the apparatus main body. This is a factor of obstructing reduction in the size and weight as well as the cost of the apparatus.

[00249] In contrast, the front projection TV of this embodiment is highly resistant to heat and can be highly reliable even when it is heated. Therefore, it can be said that the front projection TV of this embodiment can readily attain miniaturization etc. of the apparatus.

[00250] Further, as in the case of the rear projection TV of the 10th embodiment, the front projection TV of this embodiment can be configured so as to deal with various video signals such as an NTSC signal, a PAL signal, and a digital signal or various resolution ranges from VGA to UXGA.

[00251] As described above, according to the invention, a projection TV is provided with a liquid crystal module using TFTs as described in the first embodiment having a property that the reliability is increased by heating. By providing this configuration, the invention realizes a projection TV that is highly resistant to heat and hence is highly reliable.

[00252] The invention also enables manufacture of a rear projection TV that does not use an air-cooling fan because of its high resistance to heat. This type of rear projection TV is free of the problem that dust sticks to the back side of the screen, and has an advantage of being maintenance free. This is particularly advantageous for use in general homes.