US 6,844,203 B2Grant

Gate oxides, and methods of forming

Issue Date:2005-01-18

•34 Claims

•7 Drawing Sheets

Abstract

A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO₂gate oxides are provided. Also shown is a gate oxide with a conduction band offset of 2 eV or greater. Gate oxides formed from elements such as yttrium and gadolinium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.

Metadata

Assignee

Micron Technology, Inc.

Inventors

Kie Y. Ahn
Leonard Forbes

Application Information

Application Number:US 09/944,981

Filing Date:2001-08-30

Priority Date:2001-08-30

Art Unit:2812

Patent Drawings (7 sheets)

Description

FIELD OF THE INVENTION

[00002] The invention relates to semiconductor devices and device fabrication. Specifically, the invention relates to gate oxide layers of transistor devices and their method of fabrication.

BACKGROUND OF THE INVENTION

[00003] In the semiconductor device industry, particularly in the fabrication of transistors, there is continuous pressure to reduce the size of devices such as transistors. The ultimate goal is to fabricate increasingly smaller and more reliable integrated circuits (ICs) for use in products such as processor chips, mobile telephones, or memory devices such as DRAMs. The smaller devices are frequently powered by batteries, where there is also pressure to reduce the size of the batteries, and to extend the time between battery charges. This forces the industry to not only design smaller transistors, but to design them to operate reliably with lower power supplies.

[00004] A common configuration of a transistor is shown in FIG. 1. While the following discussion uses FIG. 1 to illustrate a transistor from the prior art, one skilled in the art will recognize that the present invention could be incorporated into the transistor shown in FIG. 1 to form a novel transistor according to the invention. The transistor 100 is fabricated in a substrate 110 that is typically silicon, but could be fabricated from other semiconductor materials as well. The transistor 100 has a first source/drain region 120 and a second source/drain region 130. A body region 132 is located between the first source/drain region and the second source/drain region, the body region 132 defining a channel of the transistor with a channel length 134. A gate dielectric, or gate oxide 140 is located on the body region 132 with a gate 150 located over the gate oxide. Although the gate dielectric can be formed from materials other than oxides, the gate dielectric is typically an oxide, and is commonly referred to as a gate oxide. The gate may be fabricated from polycrystalline silicon (polysilicon) or other conducting materials such as metal may be used.

[00005] In fabricating transistors to be smaller in size and reliably operating on lower power supplies, one important design criteria is the gate oxide 140. A gate oxide 140, when operating in a transistor, has both a physical gate oxide thickness and an equivalent oxide thickness (EOT). The equivalent oxide thickness quantifies the electrical properties, such as capacitance, of a gate oxide 140 in terms of a representative physical thickness. EOT is defined as the thickness of a theoretical SiO₂layer that describes the actual electrical operating characteristics of the gate oxide 140 in the transistor 100. For example, in traditional SiO₂gate oxides, a physical oxide thickness may be 5.0 nm, but due to undesirable electrical effects such as gate depletion, the EOT may be 6.0 nM. A gate oxide other than SiO₂may also be described electrically in terms of an EOT. In this case, the theoretical oxide referred to in the EOT number is an equivalent SiO₂oxide layer. For example, SiO₂has a dielectric constant of approximately 4. An alternate oxide with a dielectric constant of 20 and a physical thickness of 100 nm would have an EOT of approximately 20 nm (100*(4/20)), which represents a theoretical SiO₂gate oxide.

[00006] Lower transistor operating voltages and smaller transistors require thinner equivalent oxide thicknesses (EOTs). A problem with the increasing pressure of smaller transistors and lower operating voltages is that gate oxides fabricated from SiO₂are at their limit with regards to physical thickness and EOT. Attempts to fabricate SiO₂gate oxides thinner than today's physical thicknesses show that these gate oxides no longer have acceptable electrical properties. As a result, the EOT of a SiO₂gate oxide 140 can no longer be reduced by merely reducing the physical gate oxide thickness. Attempts to solve this problem have led to interest in gate oxides made from oxide materials other than SiO₂. Certain alternate oxides have a higher dielectric constant (k), which allows the physical thickness of a gate oxide 140 to be the same as existing SiO₂limits or thicker, but provides an EOT that is thinner than current SiO₂limits.

[00007] A problem that arises in forming an alternate oxide layer on the body region of a transistor is the process in which the alternate oxide is formed on the body region. Recent studies show that the surface roughness of the body region has a large effect on the electrical properties of the gate oxide, and the resulting operating characteristics of the transistor. The leakage current through a physical 1.0 nm gate oxide increases by a factor of 10 for every 0.1 increase in the root-mean-square (RMS) roughness. In forming an alternate oxide layer on the body region of a transistor, a thin layer of the alternate material to be oxidized (typically a metal) must first be deposited on the body region. Current processes for depositing a metal or other alternate layer on the body region of a transistor are unacceptable due to their effect on the surface roughness of the body region.

[00008] FIG. 2a shows a surface 210 of a body region 200 of a transistor. The surface 210 in the Figure has a high degree of smoothness, with a surface variation 220. FIG. 2b shows the body region 200 during a conventional sputtering deposition process stage. During sputtering, particles 230 of the material to be deposited bombard the surface 210 at a high energy. When a particle 230 hits the surface 210, some particles adhere as shown by particle 235, and other particles cause damage as shown by pit 240. High energy impacts can throw off body region particles 215 to create the pits 240. A resulting layer 250 as deposited by sputtering is shown in FIG. 2c. The deposited layer/body region interface 255 is shown following a rough contour created by the sputtering damage. The surface of the deposited layer 260 also shows a rough contour due to the rough interface 255.

[00009] In a typical process of forming an alternate material gate oxide, the deposited layer 250 is oxidized to convert the layer 250 to an oxide material. Existing oxidation processes do not, however, repair the surface damage created by existing deposition methods such as sputtering. As described above, surface roughness has a large influence on the electrical properties of the gate oxide and the resulting transistor.

[00010] What is needed is an alternate material gate oxide that is more reliable at existing EOTs than current gate oxides. What is also needed is an alternate material gate oxide with an EOT thinner than conventional SiO₂. What is also needed is an alternative material gate oxide with a smooth interface between the gate oxide and the body region. Because existing methods of deposition are not capable of providing a smooth interface with an alternate material gate oxide, what is further needed is a method of forming an alternate material gate oxide that maintains a smooth interface.

[00011] Additionally, at higher process temperatures, any of several materials used to fabricate the transistor, such as silicon, can react with other materials such as metals or oxygen to form unwanted silicides or oxides. What is needed is a lower temperature process of forming gate oxides that prevents the formation of unwanted byproduct materials.

SUMMARY OF THE INVENTION

[00012] A method of forming a gate oxide on a surface such as a transistor body region is shown where a metal layer is deposited by thermal evaporation on the body region, the metal being chosen from a group consisting of the group IIIB elements and the rare earth series of the periodic table. The metal layer is then oxidized to convert the metal layer to a gate oxide. In one embodiment, the metal layer includes yttrium (Y). In one embodiment, the metal layer includes gadolinium (Gd). One embodiment of the invention uses an electron beam source to evaporate the metal layer onto the body region of the transistor. The oxidation process in one embodiment utilizes a krypton(Kr)/oxygen (O₂) mixed plasma process.

[00013] In addition to the novel process of forming a gate oxide layer, a transistor formed by the novel process exhibits novel features that may only be formed by the novel process. Thermal evaporation deposition of a metal layer onto a body region of a transistor preserves an original smooth surface roughness of the body region in contrast to other prior deposition methods that increase surface roughness. The resulting transistor fabricated with the process of this invention will exhibit a gate oxide/body region interface with a surface roughness variation as low as 0.6 nm.

[00014] These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[00015] FIG. 1 shows a common configuration of a transistor.

[00016] FIG. 2a shows a smooth surface of a body region of a transistor.

[00017] FIG. 2b shows a deposition process according to the prior art.

[00018] FIG. 2c shows a deposited film on a body region according to the prior art.

[00019] FIG. 3a shows a deposition process according to the invention.

[00020] FIG. 3b shows a magnified view of a deposited film on a body region from FIG. 3a.

[00021] FIG. 4a shows a deposited film on a body region according to the invention.

[00022] FIG. 4b shows a partially oxidized film on a body region according to the invention.

[00023] FIG. 4c shows a completely oxidized film on a body region according to the invention.

[00024] FIG. 5 shows a perspective view of a personal computer.

[00025] FIG. 6 shows a schematic view of a central processing unit.

[00026] FIG. 7 shows a schematic view of a DRAM memory device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[00027] In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form the integrated circuit (IC) structure of the invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is understood to include semiconductors, and the term insulator or dielectric is defined to include any material that is less electrically conductive than the materials referred to as conductors.

[00028] The term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizonal as defined above. Prepositions, such as “on”, “side” (as in “sidewall”), “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

[00029] FIG. 3a shows an electron beam evaporation technique to deposit a material on a surface such as a body region of a transistor. In FIG. 3a, a substrate 310 is placed inside a deposition chamber 300. The substrate in this embodiment is masked by a first masking structure 312 and a second masking structure 314. In this embodiment, the unmasked region 316 includes a body region of a transistor, however one skilled in the art will recognize that other semiconductor device structures may utilize this process. Also located within the deposition chamber 300 is an electron beam source 330, and a target material 334. Although in this embodiment, an electron beam evaporation technique is used, it will be apparent to one skilled in the art that other thermal evaporation techniques can be used without departing from the scope of the invention. During the evaporation process, the electron beam source 330 generates an electron beam 332. The electron beam hits the target material 334 and heats a portion of the target material enough to cause the surface of the target material to evaporate. The evaporated material 336 is then distributed throughout the chamber 300, and the material 336 deposits on surfaces that it contacts, such as the exposed body region 316. The depositing material builds up to form a layer 320 of material that is chemically the same as the target material 334.

[00030] In one embodiment of the invention, the deposited material layer 320 includes a pure metal layer chosen from the alkaline earth metals in group IIIB of the periodic table or the rare earth series of the periodic table. In one embodiment of the invention, the deposited material layer 320 includes yttrium (Y). In another embodiment of the invention, the deposited material layer 320 includes gadolinium (Gd). In one embodiment of the invention, the target material is a 99.9999% pure slug of yttrium. In another embodiment of the invention, the target material is a 99.9999% pure slug of gadolinium. The choices of materials were based on the properties of the oxides formed by these materials. Considerations included the thermodynamic stability of the oxide with silicon, the diffusion coefficient of the oxide at high processing temperatures such as 1000° K., the lattice match of the oxide with silicon, the dielectric constant of the oxide, and the conduction band offset of the oxide. In one embodiment, the conduction band offset of the metal oxide formed is over 2 eV. In one embodiment, the deposited material layer 320 is substantially amorphous. A lower presence of grain boundaries in the substantially amorphous material layer 320 reduces the leakage current through the final gate oxide. Although the amorphous form is preferred, the materials chosen for oxidation, such as yttrium and gadolinium are also acceptable in their crystalline form.

[00031] A thermal evaporation process such as the electron beam evaporation technique described above does not cause the surface damage that is inherent in other deposition techniques such as the sputtering technique shown in FIG. 2b. This allows a very thin layer of material to be deposited on a body region of a transistor, while maintaining a smooth interface. A thermal evaporation process such as the electron beam evaporation technique described above also allows low processing temperatures that inhibit the formation of unwanted byproducts such as silicides and oxides. In one embodiment, the thermal evaporation is performed with a substrate temperature between approximately 150 and 200° C.

[00032] FIG. 3b shows a magnified view of the body region 316 and the deposited layer 320 from FIG. 3a. The interface 340 is shown with a roughness variation 346. The deposited layer surface 348 is also shown with a similar surface roughness. One possible surface variation 346 would be an atomic layer variation. In atomic smoothness, the greatest difference in surface features is between a first atomic layer as indicated by layer 342 and a second atomic layer 344. The thermal evaporation deposition technique described above preserves atomic smoothness such as is shown in FIG. 3b, however other acceptable levels of surface roughness greater than atomic smoothness will also be preserved by the thermal evaporation technique.

[00033] FIGS. 4a-4c show a low temperature oxidation process that is used in one embodiment to convert the deposited layer 320 into a gate oxide. A deposited material layer 410 is shown in FIG. 4a on a substrate surface 400. The layer 410 forms an interface 420 with the substrate surface 400, and the layer 410 has an outer surface 430. The layer 410 in this embodiment is deposited over a body region of a transistor, however the layer may be deposited on any surface within the scope of the invention.

[00034] In FIG. 4b, the layer 410 is in the process of being oxidized. In one embodiment, the oxidation process includes a krypton/oxygen mixed plasma oxidation process. The mixed plasma process generates atomic oxygen or oxygen radicals in contrast to molecular oxygen or O₂used in conventional thermal oxidation. The atomic oxygen is introduced to the layer from all exposed directions as indicated by arrows 440, creating an oxide portion 450. The atomic oxygen continues to react with the layer and creates an oxidation interface 422. As the reaction progresses, atomic oxygen diffuses through the oxide portion 450 and reacts at the oxidation interface 422 until the layer is completely converted to an oxide of the deposited material layer. FIG. 4c shows the resulting oxide layer 450 which spans a physical thickness 452 from the outer surface 430 to the interface 420.

[00035] In one embodiment, the processing variables for the mixed plasma oxidation include a low ion bombardment energy of less than 7 eV, a high plasma density above 10¹²/cm³and a low electron temperature below 1.3 eV. In one embodiment, the substrate temperature is approximately 400° C. In one embodiment, a mixed gas of 3% oxygen with the balance being krypton at a pressure of 1 Torr is used. In one embodiment, a microwave power density of 5 W/cm²is used.

[00036] The low temperature mixed plasma oxidation process described above allows the deposited layer to be oxidized at a low temperature, which inhibits the formation of unwanted byproducts such as silicides and oxides. The mixed plasma process in one embodiment is performed at approximately 400° C. in contrast to prior thermal oxidation processes that are performed at approximately 1000° C. The mixed plasma oxidation process has also been shown to provide improved thickness variation on silicon (111) surfaces in addition to (100) surfaces. Although the low temperature mixed plasma process above describes the formation of alternate material oxides, one skilled in the art will recognize that the process can also be used to form SiO₂oxide structures.

[00037] Metals chosen from group IIIB of the periodic table or the rare earth series of the periodic table form oxides that are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. Yttrium and gadolinium are two examples of metals taken from the above listed periodic table groups that form thermodynamically stable gate oxides. In particular, yttrium forms an oxide comprised of Y₂O₃and gadolinium forms a similar oxide of Gd₂O₃. In addition to the stable thermodynamic properties inherent in the oxides chosen, the novel process used to form the oxide layers is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures.

[00038] A transistor made using the novel gate oxide process described above will possess several novel features. By creating an oxide material with a higher dielectric constant (k) and controlling surface roughness during formation, a gate oxide can be formed with an EOT thinner than 2 nm. A thicker gate oxide that is more uniform, and easier to process can also be formed with the alternate material oxide of the present invention, the alternate material gate oxide possessing an EOT equivalent to the current limits of SiO₂gate oxides. The smooth surface of the body region is preserved during processing, and a resulting transistor will have a smooth interface between the body region and the gate oxide with a surface roughness on the order of 0.6 nm.

[00039] Transistors created by the methods described above may be implemented into memory devices and information handling devices as shown in FIGS. 5-7 and described below. While specific types of memory devices and computing devices are shown below, it will be recognized by one skilled in the art that several types of memory devices and information handling devices could utilize the invention.

[00040] A personal computer, as shown in FIGS. 5 and 6, include a monitor 500, keyboard input 502 and a central processing unit 504. The processor unit typically includes microprocessor 606, memory bus circuit 608 having a plurality of memory slots 612(a-n), and other peripheral circuitry 610. Peripheral circuitry 610 permits various peripheral devices 624 to interface processor-memory bus 620 over input/output (I/O) bus 622. The personal computer shown in FIGS. 5 and 6 also includes at least one transistor having a gate oxide according to the teachings of the present invention.

[00041] Microprocessor 606 produces control and address signals to control the exchange of data between memory bus circuit 608 and microprocessor 606 and between memory bus circuit 608 and peripheral circuitry 610. This exchange of data is accomplished over high speed memory bus 620 and over high speed I/O bus 622.

[00042] Coupled to memory bus 620 are a plurality of memory slots 612(a-n) which receive memory devices well known to those skilled in the art. For example, single in-line memory modules (SIMMs) and dual in-line memory modules (DIMMs) may be used in the implementation of the present invention.

[00043] These memory devices can be produced in a variety of designs which provide different methods of reading from and writing to the dynamic memory cells of memory slots 612. One such method is the page mode operation. Page mode operations in a DRAM are defined by the method of accessing a row of a memory cell arrays and randomly accessing different columns of the array. Data stored at the row and column intersection can be read and output while that column is accessed. Page mode DRAMs require access steps which limit the communication speed of memory circuit 608. A typical communication speed for a DRAM device using page mode is approximately 33 MHZ.

[00044] An alternate type of device is the extended data output (EDO) memory which allows data stored at a memory array address to be available as output after the addressed column has been closed. This memory can increase some communication speeds by allowing shorter access signals without reducing the time in which memory output data is available on memory bus 620. Other alternative types of devices include SDRAM, DDR SDRAM, SLDRAM and Direct RDRAM as well as others such as SRAM or Flash memories.

[00045] FIG. 7 is a block diagram of an illustrative DRAM device 700 compatible with memory slots 612(a-n). The description of DRAM 700 has been simplified for purposes of illustrating a DRAM memory device and is not intended to be a complete description of all the features of a DRAM. Those skilled in the art will recognize that a wide variety of memory devices may be used in the implementation of the present invention. The example of a DRAM memory device shown in FIG. 7 includes at least one transistor having a gate oxide according to the teachings of the present invention.

[00046] Control, address and data information provided over memory bus 620 is further represented by individual inputs to DRAM 700, as shown in FIG. 7. These individual representations are illustrated by data lines 702, address lines 704 and various discrete lines directed to control logic 706.

[00047] As is well known in the art, DRAM 700 includes memory array 710 which in turn comprises rows and columns of addressable memory cells. Each memory cell in a row is coupled to a common wordline. Additionally, each memory cell in a column is coupled to a common bitline. Each cell in memory array 710 includes a storage capacitor and an access transistor as is conventional in the art.

[00048] DRAM 700 interfaces with, for example, microprocessor 606 through address lines 704 and data lines 702. Alternatively, DRAM 700 may interface with a DRAM controller, a micro-controller, a chip set or other electronic system. Microprocessor 606 also provides a number of control signals to DRAM 700, including but not limited to, row and column address strobe signals RAS and CAS, write enable signal WE, an output enable signal OE and other conventional control signals.

[00049] Row address buffer 712 and row decoder 714 receive and decode row addresses from row address signals provided on address lines 704 by microprocessor 606. Each unique row address corresponds to a row of cells in memory array 710. Row decoder 714 includes a wordline driver, an address decoder tree, and circuitry which translates a given row address received from row address buffers 712 and selectively activates the appropriate wordline of memory array 710 via the wordline drivers.

[00050] Column address buffer 716 and column decoder 718 receive and decode column address signals provided on address lines 704. Column decoder 718 also determines when a column is defective and the address of a replacement column. Column decoder 718 is coupled to sense amplifiers 720. Sense amplifiers 720 are coupled to complementary pairs of bitlines of memory array 710.

[00051] Sense amplifiers 720 are coupled to data-in buffer 722 and data-out buffer 724. Data-in buffers 722 and data-out buffers 724 are coupled to data lines 702. During a write operation, data lines 702 provide data to data-in buffer 722. Sense amplifier 720 receives data from data-in buffer 722 and stores the data in memory array 710 as a charge on a capacitor of a cell at an address specified on address lines 704.

[00052] During a read operation, DRAM 700 transfers data to microprocessor 606 from memory array 710. Complementary bitlines for the accessed cell are equilibrated during a precharge operation to a reference voltage provided by an equilibration circuit and a reference voltage supply. The charge stored in the accessed cell is then shared with the associated bitlines. A sense amplifier of sense amplifiers 720 detects and amplifies a difference in voltage between the complementary bitlines. The sense amplifier passes the amplified voltage to data-out buffer 724.

[00053] Control logic 706 is used to control the many available functions of DRAM 700. In addition, various control circuits and signals not detailed herein initiate and synchronize DRAM 700 operation as known to those skilled in the art. As stated above, the description of DRAM 700 has been simplified for purposes of illustrating the present invention and is not intended to be a complete description of all the features of a DRAM. Those skilled in the art will recognize that a wide variety of memory devices, including but not limited to, SDRAMs, SLDRAMs, RDRAMs and other DRAMs and SRAMs, VRAMs and EEPROMs, may be used in the implementation of the present invention. The DRAM implementation described herein is illustrative only and not intended to be exclusive or limiting.

Conclusion

[00054] Thus has been shown a gate oxide and method of fabricating a gate oxide that produce a more reliable and thinner equivalent oxide thickness. Gate oxides formed from elements in group IIIB of the periodic table or the rare earth series of the periodic table are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. Yttrium and gadolinium oxides in particular have been shown to provide excellent electrical and thermodynamic properties. In addition to the stable thermodynamic properties inherent in the oxides shown, the process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures.

[00055] Transistors and higher level ICs or devices have been shown utilizing the novel gate oxide and process of formation. The higher dielectric constant (k) oxide materials shown in one embodiment are formed with an EOT thinner than 2 nm, e.g. thinner than possible with conventional SiO₂gate oxides. A thicker gate oxide that is more uniform, and easier to process has also been shown with at EOT equivalent to the current limits of SiO₂gate oxides. In one embodiment of the present invention, the novel gate oxide provides a conduction band offset of 2 eV or greater.

[00056] A novel process of forming a gate oxide has been shown where the surface smoothness of the body region is preserved during processing, and the resulting transistor has a smooth interface between the body region and the gate oxide with a surface roughness on the order of 0.6 nm. This solves the prior art problem of poor electrical properties such as high leakage current, created by unacceptable surface roughness.

[00057] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. It is to be understood that the above description is intended to be illustrative, and not restrictive. Combinations of the above embodiments, and other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention includes any other applications in which the above structures and fabrication methods are used. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

Certificate of Correction present

The claims shown below may not include correction changes. Use the corrected PDF for authoritative text.

1. A method of forming a gate oxide on a transistor body region, comprising:

electron beam evaporation depositing a metal layer on the body region, the metal being chosen from a group consisting of the group IIIB elements and the rare earth series of the periodic table; and

oxidizing the metal layer to form a metal oxide layer on the body region, wherein oxidizing the metal layer includes oxidizing using a krypton (Kr)/oxygen (O2) mixed plasma process.

2. The method of claim 1, wherein evaporation depositing the metal layer includes depositing a metal layer, the metal layer being chosen from a group consisting of yttrium and gadolinium.

3. The method of claim 2, wherein electron beam evaporation depositing the metal layer includes electron beam evaporation of a 99.9999% pure metal target material.

4. The method of claim 1, wherein evaporation depositing the metal layer includes evaporation depositing at a substrate temperature of approximately 150-400° C.

5. The method of claim 1, wherein oxidizing the metal layer includes oxidizing at a temperature of approximately 400° C.

6. The method of claim 1, wherein oxidizing the metal layer includes oxidizing with atomic oxygen.

7. A method of forming a gate oxide on a transistor body region, comprising:

evaporation depositing a metal layer on the body region, the metal being chosen from a group consisting of the group IIIB elements and the rare earth series of the periodic table; and

oxidizing the metal layer using a krypton(Kr)/oxygen (O2) mixed plasma process to form a metal oxide layer on the body region.

8. The method of claim 7, wherein evaporation depositing the metal layer includes depositing a metal layer, the metal layer being chosen from a group consisting of yttrium and gadolinium.

9. The method of claim 7, wherein evaporation depositing the metal layer includes evaporation depositing by electron beam evaporation.

10. The method of claim 9, wherein electron beam evaporation depositing the metal layer includes electron beam evaporation of a 99.9999% pure metal target material.

11. The method of claim 7, wherein evaporation depositing the metal layer includes evaporation depositing at a substrate temperature of approximately 150-400° C.

12. A method of forming a transistor, comprising:

forming first and second source/drain regions;

forming a body region between the first and second source/drain regions;

evaporation depositing a metal layer on the body region, the metal being chosen from a group consisting of the group IIIB elements and the rare earth series of the periodic table;

oxidizing the metal layer to form a metal oxide layer on the body region, wherein oxidizing the metal layer includes oxidizing using a krypton (Kr)/oxygen (O2) mixed plasma process; and

coupling a gate to the metal oxide layer.

13. The method of claim 12, wherein evaporation depositing the metal layer includes depositing a metal layer, the metal layer being chosen from a group consisting of yttrium and gadolinium.

14. The method of claim 12, wherein evaporation depositing the metal layer includes evaporation depositing by electron beam evaporation.

15. The method of claim 14, wherein electron beam evaporation depositing the metal layer includes electron beam evaporation of a 99.9999% pure metal target material.

16. The method of claim 12, wherein evaporation depositing the metal layer includes evaporation depositing at a substrate temperature of approximately 150-400° C.

17. The method of claim 12, wherein oxidizing the metal layer includes oxidizing at a temperature of approximately 400° C.

18. The method of claim 12, wherein oxidizing the metal layer includes oxidizing with atomic oxygen.

19. A method of forming a memory array, comprising:

forming a number of access transistors, including:

forming first and second source/drain regions;

forming a body region between the first and second source/drain regions;

evaporation depositing a metal layer on the body region, the metal being chosen from a group consisting of the group IIIB elements and the rare earth series of the periodic table;

oxidizing the metal layer to form a metal oxide layer on the body region, wherein oxidizing the metal layer includes oxidizing using a krypton (Kr)/oxygen (O2) mixed plasma process;

coupling a gate to the metal oxide layer;

forming a number of wordlines coupled to a number of the gates of the number of access transistors;

forming a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors; and

forming a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors.

20. The method of claim 19, wherein evaporation depositing the metal layer includes depositing a metal layer, the metal layer being chosen from a group consisting of yttrium and gadolinium.

21. The method of claim 19, wherein evaporation depositing the metal layer includes evaporation depositing by electron beam evaporation.

22. The method of claim 21, wherein electron beam evaporation depositing the metal layer includes electron beam evaporation of a 99.9999% pure metal target material.

23. The method of claim 19, wherein evaporation depositing the metal layer includes evaporation depositing at a substrate temperature of approximately 150-400° C.

24. The method of claim 19, wherein oxidizing the metal layer includes oxidizing at a temperature of approximately 400° C.

25. The method of claim 19, wherein oxidizing the metal layer includes oxidizing with atomic oxygen.

26. A transistor formed by the process, comprising:

forming a body region coupled between a first source/drain region and a second source/drain region;

evaporation depositing a metal layer on the body region, the metal being chosen from a group consisting of the group IIIB elements and the rare earth series of the periodic table;

oxidizing the metal layer to form a metal oxide layer on the body region, wherein oxidizing the metal layer includes oxidizing using a krypton (Kr)/oxygen (O2) mixed plasma process; and

coupling a gate to the metal oxide layer.

27. The transistor of claim 26, wherein evaporation depositing the metal layer includes depositing a metal layer, the metal layer being chosen from a group consisting of yttrium and gadolinium.

28. The transistor of claim 26, wherein evaporation depositing the metal layer includes evaporation depositing by electron beam evaporation.

29. A method of forming an information handling system, comprising:

forming a processor;

forming a memory array, including:

forming a number of access transistors, including:

forming first and second source/drain regions;

forming a body region between the first and second source/drain regions;

evaporation depositing a metal layer on the body region, the metal being chosen from a group consisting of the group IIIB elements and the rare earth series of the periodic table;

oxidizing the metal layer to form a metal oxide layer on the body region, wherein oxidizing the metal layer includes oxidizing using a krypton (Kr)/oxygen (O2) mixed plasma process;

coupling a gate to the metal oxide layer;

forming a number of wordlines coupled to a number of the gates of the number of access transistors;

forming a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors;

forming a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors; and

forming a system bus that couples the processor to the memory array.

30. The method of claim 29, wherein evaporation depositing the metal layer includes depositing a metal layer, the metal layer being chosen from a group consisting of yttrium and gadolinium.

31. The method of claim 29, wherein evaporation depositing the metal layer includes evaporation depositing by electron beam evaporation.

32. A method of forming a transistor, comprising:

forming first and second source/drain regions;

forming a body region between the first and second source/drain regions;

evaporation depositing a metal layer on the body region, the metal being chosen from a group consisting of the group IIIB elements and the rare earth series of the periodic table;

oxidizing the metal layer using a krypton(Kr)/oxygen (O2) mixed plasma process to form a metal oxide layer on the body region; and

coupling a gate to the metal oxide layer.

33. The method of claim 32, wherein evaporation depositing the metal layer includes depositing a metal layer, the metal layer being chosen from a group consisting of yttrium and gadolinium.

34. The method of claim 32, wherein evaporation depositing the metal layer includes evaporation depositing by electron beam evaporation.

Patent Citations (128)

Patent	Date	Inventor	Cited By
US3381114(A)	1968-04-01	Nakanuma	Applicant
US4215156(A)	1980-07-01	Dalal et al.	Applicant
US4333808(A)	1982-06-01	Bhattacharyya et al.	Applicant
US4394673(A)	1983-07-01	Thompson et al.	Applicant
US4399424(A)	1983-08-01	Rigby	Applicant
US4413022(A)	1983-11-01	Suntola et al.	Applicant
US4590042(A)	1986-05-01	Drage	Applicant
US4647947(A)	1987-03-01	Takeoka et al.	Applicant
US4767641(A)	1988-08-01	Kieser et al.	Applicant
US4797593(A)	1989-01-01	Saito et al.	Examiner
US4920071(A)	1990-04-01	Thomas	Applicant
US4993358(A)	1991-02-01	Mahawili	Applicant
US5006192(A)	1991-04-01	Deguchi	Applicant
US5055319(A)	1991-10-01	Bunshah et al.	Applicant
US5080928(A)	1992-01-01	Klinedinst et al.	Applicant
US5198029(A)	1993-03-01	Dutta et al.	Applicant
US5595606(A)	1997-01-01	Fujikawa et al.	Applicant
US5621681(A)	1997-04-01	Moon	Applicant
US5698022(A)	1997-12-01	Glassman et al.	Applicant
US5735960(A)	1998-04-01	Sandhu et al.	Applicant
US5744374(A)	1998-04-01	Moon	Applicant
US5789030(A)	1998-08-01	Rolfson	Applicant
US5795808(A)	1998-08-01	Park	Applicant
US5801105(A)	1998-09-01	Yano et al.	Applicant
US5810923(A)	1998-09-01	Yano et al.	Applicant
US5822256(A)	1998-10-01	Bauer et al.	Applicant
US5828080(A)	1998-10-01	Yano et al.	Applicant
US5840897(A)	1998-11-01	Kirlin et al.	Applicant
US5916365(A)	1999-06-01	Sherman	Applicant
US5950925(A)	1999-09-01	Fukunaga et al.	Applicant
US5972847(A)	1999-10-01	Feenstra et al.	Applicant
US6010969(A)	2000-01-01	Vaarstra	Applicant
US6013553(A)	2000-01-01	Wallace et al.	Applicant
US6020024(A)	2000-02-01	Maiti et al.	Examiner
US6025627(A)	2000-02-01	Forbes et al.	Applicant
US6027961(A)	2000-02-01	Maiti et al.	Applicant
US6057271(A)	2000-05-01	Kenjiro et al.	Applicant
US6059885(A)	2000-05-01	Ohashi et al.	Applicant
US6093944(A)	2000-07-01	VanDover	Applicant
US6110529(A)	2000-08-01	Gardiner et al.	Applicant
US6120531(A)	2000-09-01	Zhou et al.	Applicant
US6161500(A)	2000-12-01	Kopacz et al.	Applicant
US6171900(B1)	2001-01-01	Sun	Applicant
US6184072(B1)	2001-02-01	Kaushik et al.	Examiner
US6187484(B1)	2001-02-01	Glass et al.	Applicant
US6203613(B1)	2001-03-01	Gates et al.	Applicant
US6206972(B1)	2001-03-01	Dunham	Applicant
US6207589(B1)	2001-03-01	Ma et al.	Applicant
US6211035(B1)	2001-04-01	Moise et al.	Applicant
US6217645(B1)	2001-04-01	Vaartstra	Applicant
US6225168(B1)	2001-05-01	Gardner et al.	Applicant
US6225237(B1)	2001-05-01	Vaartstra	Applicant
US6232847(B1)	2001-05-01	Marcy, 5th et al.	Applicant
US6273951(B1)	2001-08-01	Vaartstra	Applicant
US6281144(B1)	2001-08-01	Cleary et al.	Applicant
US6291866(B1)	2001-09-01	Wallace et al.	Applicant
US6294813(B1)	2001-09-01	Forbes et al.	Applicant
US6297516(B1)	2001-10-01	Forrest et al.	Applicant
US6297539(B1)	2001-10-01	Ma et al.	Applicant
US6302964(B1)	2001-10-01	Umotoy et al.	Applicant
US6303481(B2)	2001-10-01	Park	Applicant
US6331465(B1)	2001-12-01	Forbes et al.	Applicant
US6348386(B1)	2002-02-01	Gilmer	Applicant
US6368398(B2)	2002-04-01	Vaartstra	Applicant
US6368518(B1)	2002-04-01	Vaartstra	Applicant
US6368941(B1)	2002-04-01	Chen et al.	Applicant
US6380579(B1)	2002-04-01	Nam et al.	Applicant
US6387712(B1)	2002-05-01	Yano et al.	Applicant
US6391769(B1)	2002-05-01	Lee et al.	Applicant
US6404027(B1)	2002-06-01	Hong et al.	Examiner
US6420279(B1)	2002-07-01	Ono et al.	Applicant
US6432779(B1)	2002-08-01	Hobbs et al.	Applicant
US6444039(B1)	2002-09-01	Nguyen	Applicant
US6444895(B1)	2002-09-01	Nikawa	Applicant
US6445023(B1)	2002-09-01	Vaartstra et al.	Applicant
US6448192(B1)	2002-09-01	Kaushik	Applicant
US6451695(B2)	2002-09-01	Sneh	Applicant
US6455717(B1)	2002-09-01	Vaartstra	Applicant
US6458701(B1)	2002-10-01	Chae et al.	Applicant
US6465334(B1)	2002-10-01	Buynoski et al.	Applicant
US6482740(B2)	2002-11-01	Soininen et al.	Applicant
US6495436(B2)	2002-12-01	Ahn et al.	Applicant
US6498063(B1)	2002-12-01	Ping	Applicant
US6514828(B2)	2003-02-01	Ahn et al.	Applicant
US6518610(B2)	2003-02-01	Yang et al.	Applicant
US6521911(B2)	2003-02-01	Parsons et al.	Applicant
US6524867(B2)	2003-02-01	Yang et al.	Applicant
US6524901(B1)	2003-02-01	Trivedi	Applicant
US6534420(B2)	2003-03-01	Ahn et al.	Applicant
US6573199(B2)	2003-06-01	Sandhu et al.	Applicant
US6586792(B2)	2003-07-01	Ahn et al.	Applicant
US6593610(B2)	2003-07-01	Gonzalez	Applicant
US6602338(B2)	2003-08-01	Chen et al.	Applicant
US6608378(B2)	2003-08-01	Ahn et al.	Applicant
US6613702(B2)	2003-09-01	Sandhu et al.	Applicant
US6639267(B2)	2003-10-01	Eldridge	Applicant
US6661058(B2)	2003-12-01	Ahn et al.	Applicant
US6682602(B2)	2004-01-01	Vaartstra	Applicant
US6683005(B2)	2004-01-01	Sandhu et al.	Applicant
US20010002280(A1)	2001-05-01	Sneh	Applicant
US20010009695(A1)	2001-07-01	Saanila et al.	Applicant
US20010042505(A1)	2001-11-01	Vaartstra	Applicant
US20010051442(A1)	2001-12-01	Katsir et al.	Applicant
US20010053082(A1)	2001-12-01	Chipalkatti et al.	Applicant
US20020001971(A1)	2002-01-01	Cho	Applicant
US20020022156(A1)	2002-02-01	Bright	Applicant
US20020089023(A1)	2002-07-01	Yu et al.	Applicant
US20020119297(A1)	2002-08-01	Forrest et al.	Applicant
US20020146916(A1)	2002-10-01	Irino et al.	Applicant
US20020155688(A1)	2002-10-01	Ahn et al.	Applicant
US20020155689(A1)	2002-10-01	Ahn et al.	Applicant
US20020192974(A1)	2002-12-01	Ahn et al.	Applicant
US20030001212(A1)	2003-01-01	Hu et al.	Applicant
US20030001241(A1)	2003-01-01	Chakrabarti et al.	Applicant
US20030003722(A1)	2003-01-01	Vaartstra	Applicant
US20030017717(A1)	2003-01-01	Ahn et al.	Applicant
US20030042526(A1)	2003-03-01	Weimer	Applicant
US20030052356(A1)	2003-03-01	Yang et al.	Applicant
US20030052358(A1)	2003-03-01	Weimer	Applicant
US20030102501(A1)	2003-06-01	Yang et al.	Applicant
US20030119313(A1)	2003-06-01	Yang et al.	Applicant
US20030157764(A1)	2003-08-01	Ahn et al.	Applicant
US20030175411(A1)	2003-09-01	Kodas et al.	Applicant
US20030222300(A1)	2003-12-01	Basceri et al.	Applicant
US20030228747(A1)	2003-12-01	Ahn et al.	Applicant
JP62-199019	1987-09-01		Applicant
JP5090169	1993-04-01		Applicant
JP2001-332546	2001-11-01		Applicant

Non-Patent Literature (146)

Kwo et al., Properties of high K gate dielectrics Gd2O3 and Y2O3 for Si, Oct. 16, 2000, Journal of Applied Physics, vol. 89 No. 7 pp. 3920-3927.*Applicant
Bright, A A., et al., “Low-rate plasma oxidation of Si in a dilute oxygen/helium plasma for low-temperature gate quality Si/Sio2 interfaces”, Applied Physics Letters, (Feb. 1991), pp. 619-621.Applicant
Cheng, Baohong, et al., “The Impact of High-k Gate Dielectrics and Metal Gate Electrodes on Sub-100nm MOSFET's”, IEEE Transactions on Electron Devices, (1999), 1537-1544.Applicant
Fuyuki, Takashi, et al., “Initial stage of ultra-thin SiO2 formation at low temperatures using activated oxygen”, Applied Surface Science, (1997), pp. 123-126.Applicant
Hirayama, Masaki, et al., “Low-Temperature growth of High-Integrity Silicon Oxide Films by Oxygen Radical Generated in High Density Krypton Plasma”, IEDM Technical Digest, (1999), 249-252.Applicant
Hubbard, K. J., et al., “Thermodynamic stability of binary oxides in contact with silicon”, J. Mater. Res., (Nov. 1996), 2757-2776.Applicant
Jeong, Chang-Wook, et al., “Plasma-Assisted Atomic Layer Growth of High-Quality Aluminum Oxide Thin Films”, Japanese Journal of Applied Physics, (Jan. 2001), pp. 285-289.Applicant
Kawai, Y , et al., “Ultra-low temperature growth of high-integrity gate oxide films by low-energy ion-assisted oxidation”, Applied Physics Letters, (Apr. 1994), pp. 2223-2225.Applicant
Kim, C T., et al., “Application of Al2O3 Grown by Atomic Layer Deposition to DRAM and FeRAM”, International Symposium in Integrated Ferroelectrics, (Mar. 2000), pp. 316.Applicant
Kim, Y , et al., “Substrate dependence on the optical properties of Al2O3 films grown by atomic layer deposition”, Applied Physics Letters, (Dec. 1997), pp. 3604-3606.Applicant
Leskela, M , et al., “ALD precursor chemistry: Evolution and future challenges”, Journal de Physique, (1999), pp. 837-852.Applicant
Liu, C. T., “Circuit Requirement and Integration Challenges of Thin Gate Dielectrics for Ultra Small MOSFET's”, IEDM, (1998), 747-750.Applicant
Liu, Y C., et al., “Growth of ultrathin SiO2 by surface irradiation with an O2+Ar election cyclotron resonance microwave plamsa at low temperatures”, Journal of Applied Physics, (Feb. 1999), pp. 1911-1915.Applicant
Martin, P J., et al., “Ion-beam-assisted deposition of thin films”, Applied Optics, (Jan. 1983), pp. 178-184.Applicant
Muller, D. A., “The electronic structure at the atomic scale of ultrathin gate oxides”, Nature, vol. 399, No. 6738, Jun. 24, 1999, (1999), 758-61.Applicant
Nieminen, Minna, et al., “Formation and stability of lanthanum oxide thin films deposited from B-diketonate precursor”, Applied Surface Science, (2001), pp. 155-165.Applicant
Osten, H. J., et al., “High-k Gate Dielectrics with Ultra-low Leakage Current Based on Praseodymium Oxide”, IEEE, (2000), 653-656.Applicant
Pan, Tung M., et al., “High Quality Ultrathin CoTiO3 High-K Gate Dielectrics”, Electrochemical and Solid-State Letters, (2000), pp. 433-434.Applicant
Pan, Tung M., et al., “High-k cobalt-titanium oxide dielectrics formed by oxidation of sputtered Co/Ti or Ti/Co films”, Applied Physics Letters, (Mar. 2001), pp. 1439-1441.Applicant
Qi, Wen-Jie, et al., “MOSCAP and MOSFET characteristics using Cr02 gate dielectric deposited directly on Si”, IEDM Technical Digest, (1999), 145-148.Applicant
Saito, Yuji, et al., “Advantage of Radical Oxidation for Improving Reliability of Ultra-Thin Gate Oxide”, 2000 Symposium on VLSI Technology Digest of Technical Papers, (2000), 176-177.Applicant
Saito, Yuji, et al., “High-Integrity Silicon Oxide Grown at Low-Temperature by Atomic Oxygen Generated in High-Density Krypton Plasma”, Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials, (1999), 152-153.Applicant
Shin, Chang H., et al., “Fabrication and Characterization of MFISFET using Al2O3 Insulating Layer for Non-Volatile Memory”, 12th International Symposium in Integrated Ferroelectrics, (Mar. 2000), 1-9.Applicant
Sze, S M., Physics of Semiconductor Devices, (1981), pp. 431, 473.Applicant
Wolf, Stanley, et al., “Silicon Processing for the VLSI Era—Volume I: Process Technology”, Second Edition, Lattice Press, Sunset Beach, California, (2000), p. 443.Applicant
Ohting, Milton., “The Materials Science of Thin Films”, Academic Press Inc., (1992), 118, 121, 125.Applicant
Aarik, Jaan, et al., “Atomic layer growth of epitaxial TiO/sub 2/ thin films from TiCl/sub 4/ and H/sub 2/O on alpha-Al/sub 2/0/sub 3/ substrates”, Journal of Crystal Growth, 242 (1-2), (2002), 189-198.Applicant
Aarik, Jaan, et al., “Influence of substrate temperature on atomic layer growth and properties of HfO/Sub 2/ thin films”, Thin Solid Films, 340(1-2), (1999), 110-116.Applicant
Aarik, Jaan, et al., “Phase transformations in hafnium dioxide thin films grown by atomic layer doposition at high temperatures”, Applied Surface Science, 173(1-2), (Mar. 2001), 15-21.Applicant
Aarik, Jaan, et al., “Texture Development in nanocrystalline hafnium dioxide thin films grown by atomic layer deposition”, Journal of Crystal Growth, 220, (2000), 105-113.Applicant
Ahn, K. Y., et al., “Electron Beam Deposition of Amorphous Lanthanide-doped TiOx Dielectic Films”, 3 pages.Applicant
Alen, Petra, “Atomic Layer deposition of Ta(Al)N(C) thin films using trimethylaluminum as reducing agent”, Journal of the Electrochemical Society, 148(10), (Oct. 2001), G566-G571.Applicant
Bendoraitis, J G., et al., “Optical energy gaps in the monoclinic oxides of hafnium and zirconium and their solid solutions”, Journal of Physical Chemistry, 69(10), (1965), 3666-3667.Applicant
Braud, F. , “Ultra Thin Diffusion Barriers for Cu Interconnections at The Gigabit Generation and Beyond”, VMIC Conference Proceedings, (1996), 174-179.Applicant
Bunshah, Rointan F., et al., “Deposition Technologies for Films and Coatings: Developments and Applications”, Park Ridge, M.J., U.S.A. : Noyes Publications, (1982), 102-103.Applicant
Cava R J., et al., “Improvement of the dielectric properties of Ta/sub 2/O/sub 5/ through substitution with Al/sub 2/O/sub 3/”, Applied Physics Letters, 70(11), (Mar. 1997), 1396-8.Applicant
Chambers, J J., et al., “Physical and electrical characterization of ultrathin yttrium silicate insulators on silicon”, Journal of Applied Physics, 90(2), (Jul. 15, 2001), 918-33.Applicant
Copel, M. , et al., “Structure and stability of ultrathin zirconium oxide layers on Si(001)”, Applied Physics Letters, 76(4), (Jan. 2000), 436-438.Applicant
De Flaviis, Franco , et al., “Planar microwave integrated phase-shifter design with high purity ferroelectric material”, IEEE Transactions on Microwave Theory & Techniques, 45(6), (Jun. 1997), 963-969.Applicant
Desu, S B., “Minimization of Fatique in Ferroelectric Films”,Physica Status Solidi A, 151(2), (1995), 467-480.Applicant
Ding, “Copper Barrier, Seed Layer and Planerization Technologies”, VMIC Conference Proceedings, (1997), 87-92.Applicant
Dusco, C , et al., “Deposition of tin oxide into porous silicon by atomic layer epitaxy”, Journal of the Electrochemical Society, 143, (1996), 683-687.Applicant
El-Kareh, B , et al., “The evolution of DRAM cell technology”, Solid State Technology, 40(5), (1997), 89-90, 92, 95-6, 98, 100-1.Applicant
Engelhardt, M. , “Modern Applications of Plasma Etching and Patterning in Silicon Process Technology”, Contributions to Plasma Physics, 39(5), (1999), 473-478.Applicant
Fukumoto, Hirofumi , et al., “Heteroepitaxial growth of Y2O3 films on silicon”, Applied Physics Letters, 55(4), (Jul. 24, 1989), 360-361.Applicant
Fuyuki, Takashi, et al., “Electronic Properties of the Interface between Si and TiO2 Deposited at Very Low Temperatures”, Japanese Journal of Applied Physics, vol. 25, No. 9, (1986), 1288-1291.Applicant
Gartner, M , et al., “Spectroellipsometric characterization of lanthanide-doped TiO2 films obtained via the sol-gel technique”, Thin Solid Films, 234(1-2), (1993), 561-565.Applicant
Geller, S. , et al., “Crystallographic Studies of Perovskite-like Compounds. II. Rare Earth Aluminates”, Acta Cryst. vol. 9, (May 1956), 1019-1025.Applicant
Giess, E. A., et al., “Lathanide gallate perovskite-type substrates for epitaxial, high-T/sub c/ superconducting Ba/sub 2/YCu/sub 3/O/sub 7-delta / films”, IBM Journal of Research and Development, 34(6), (Nov. 1990), 916-926.Applicant
Guillaumot, B , et al., “75 nm damascene metal gate and high-k integration for advanced CMOS devices”, Technical Digest of International Electron Devices Meeting 2002, (2002), 355-358.Applicant
Guo, et al., “High Quality Ultra-thin (1.5nm) TiO2/Si3N4 Gate Dielectric fo r Deep Sub-micron CMOS Technology”, Ctied in related application,(1999).Applicant
Gusev, E P., et al., “Ultrathin High-K Dielectrics Grown by Atomic Layer Deposition: A Comparative Study of ZrO2, HfO2, Y2O3 and Al203”, Electrochemical Society Proceedings vol. 2001-9, (2001), 189-195.Applicant
Gutowski, M J., “Thermodynamic stability of high-K dielectric metal oxides ZrO/sub 2/ and HfO/sub 2/ in contact with Si and SiO/sub 2/”, Applied Physics Letters, 80(11), (Mar. 18, 2002), 1897-1899.Applicant
Hunt, C. E., et al., “Direct bonding of micromachined silicon wafers for laser diode heat exchanger applications”, Journal of Micromechanics and Microengineering, 1(3), (Sep. 1991), 152-156.Applicant
Iddles, D M., et al., “Relationships between dopants, microstructure and the microwave dielectric properties of ZrO2-TiO2-SnO2 ceramics”, Journal of Materials Science, 27(23), (Dec. 1992), 6303-6310.Applicant
Iijima, T. , “Microstructure and Electrical Properties of Amorphous W-Si-N Barrier Layer for Cu Interconnections”, 1996 VMIC Conference, (1996), 168-173.Applicant
Jeon, Sanghun , et al., “Excellent electrical characteristics of lanthanide (Pr, Nd, Sm, Gd, and Dy) oxide and lanthanide-doped oxide for MOS gate dielectric applications”, Electron Devices Meeting, 2001, IEDM Technical Digest. International, (2001), 471-474.Applicant
Jeong, Chang-Wook, et al., “Plasma-Assisted Atomic layer Growth of High-Quality Aluminum Oxide Thin Films”, Japanese Journal of Applied Physics, 40, (Jan. 2001),285-289.Applicant
Jung, H S., et al., “Improved current performance of CMOSFETs with nitrogen incorporated HfO/sub 2/-Al/sub 2/O/sub 3/ laminate gate dielectric”, Technical Digest of International Electron Devices Meeting 2002, (2002), 853-856.Applicant
Kang, L , et al., “MOSFET devices with polysilicon on single-layer HfO/sub 2/ high-K dielectrics”, International Electron Devices Meeting 2000. Technical Digest, IEDM, (2000), 35-8.Applicant
Keomany, D. , et al., “Sol gel preparation of mixed cerium-titanium oxide thin films”, Solar Energy Materials and Solar Cells, 33(4), (Aug. 1994), 429-441.Applicant
Kim, Y W., et al., “50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications”, Technical Digest of International Electron Devices Meeting 2002, (2002), 69-72.Applicant
Kim, C. T., et al., “Application of Al3O3 Grown by Atomic Layer Deposition to DRAM and FeRAM”, 12th International Symposium in Integrated Ferroelectrics, (Mar., 2000), 1 page.Applicant
Kim, D. , et al., “Atomic Control of Subsrate Termination and Heteroepitaxial Growth of SrTiO3/LaAlO3 Films”, Journal of the Korean Physical Society, 36(6), (Jun. 2000), 444-448.Applicant
Kim, Byoung-Youp , et al., “Comparison study for TiN films deposited from different method: chemical vapor deposition and atomic layer deposition”, Mechanisms of Surface and Microstructure Evolution in Deposited Films and Film Structures Symposium (Materials Research Society Symposium Proceedings vol. 672), (2001), 7.8.1-7.8.6.Applicant
Kim, Taeseok , et al., “Correlation between strain and dielectric properties in ZrTiO/sub 4/ thin films”, Applied Physics Letters, 76(21), (May 2000),3043-3045.Applicant
Kim, Taeseok , et al., “Dielectric properties and strain analysis in paraelectric ZrTiO/sub 4/ thin films deposited by DC magnetron sputtering”, Japanese Journal of Applied Physics Part 1-Regular Papers Short Notes & Review Papers, vol.39, No. 7A, (2000), 4153-4157.Applicant
Kim, Yongjo , et al., “Effect of microstructures on the microwave dielectric properties of ZrTiO/sub 4/ thin films”, Applied Physics Letters, 78(16), (Apr. 2001),2363-2365.Applicant
Kim, Y , et al., “Substrate dependence on the optical properties of Al/sub 2/O/sub 3/ films grown by atomic layer deposition”, Applied Physics Letters, 71(25, 22), (Dec. 1997),3604-3606.Applicant
Krauter, G. , et al., “Room Temperature Silicon Wafer Bonding with Ultra-Thin Polymer Films”, Advanced Materials, 9(5), (1997),417-420.Applicant
Kukli, Kaupo , “Atomic Layer Deposition of Titanium Oxide from Til4 and H2O2”, Chemical Vapor Deposition, 6(6), (2000),303-310.Applicant
Kukli, K , et al., “Comparison of hafnium oxide films grown by atomic layer deposition from iodide and chloride precursors”, Thin Solid Films, 416, (2002),72-79.Applicant
Kukli, K , et al., “Controlled growth of yttrium oxysulphide thin films by atomic layer deposition”, Materials Science Forum, 315-317, (1999), 216-221.Applicant
Kukli, Kaupo , et al., “Dielectric Properties of Zirconium Oxide Grown by Atomic Layer Deposition from Iodide Precursor”, Journal of The Electrochemical Society, 148(12),(2001),F227-F232.Applicant
Kukli, Kaupo , et al., “Influence of thickness and growth temperature on the properties of zirconium oxide films growth by atomic layer deposition on silicon”, Thin Solid Films 410(1-2), (2002),53-60.Applicant
Kukli, Kaupo , et al., “Low-Temperature Deposition of Zirconium Oxide-Based Nanocrystalline Films by Alternate Supply of Zr[OC(CH3)3]4 and H20”, Chemical Vapor Deposition, 6(6), (2000),297-302.Applicant
Kukli, K J., et al., “Properties of hafnium oxide films grown by atomic layer deposition from hafnium tetraiodide and oxygen”, Journal of Applied Physics, 92(10), (Nov. 15, 2002),5698-5703.Applicant
Kow, J. , et al., “High gate dielectrics Gd2O3 and Y2O3 for silicon”, Applied Physics Letters, 77(1), (Jul. 3, 2000), 130-132.Applicant
Kow, J. , “Properties of high k gate dielectrics Gd2O3 and Y2O3 for Si”, Journal of Applied Physics, 89(7), (2001),3920-3927.Applicant
Laursen, T. , “Encapsulation of Copper by Nitridation of Cu-Ti Alloy/Bilayer Structures”, International Conference on Metallurgical Coatings and Thin Films, Abstract No. H1.03, San Diego, CA,(Apr. 1997),309.Applicant
Lee, Byoung H., et al., “Characteristics of TaN gate MOSFET with ultrathin hafnium oxide (8 A-12 A)”, Electron Devices Meeting, 2000. IEDM Technical Digest. International, (2000),39-42.Applicant
Lee, A E., et al., “Epitaxially grown sputtered LaAlO3 films”, Applied Physics Letters, 57(19), (Nov. 1990),2019-2021.Applicant
Lee, S J., et al., “High quality ultra thin CVD HfO2 gate stack with poly-Si gate electrode”, Electron Devices Meeting, 2000. IEDM Technical Digest. International, (2000),31-34.Applicant
Lee, Cheng-Chung , et al., “Ion-assistend deposition of silver films”, Thin Solid Films, vol. 359, (2000), 95-97.Applicant
Lee, Jung-Hyoung, et al., “Mass production worthy HfO/sub 2/-Al/sub 2/O/sub 3/ laminate capacitor technology using Hf liquid precursor for sub-100 nm DRAMs”, Electron Devices Meeting, 2002. IEDM '02. Digest. International, (2002),221-224.Applicant
Lee, Dong H., et al., “Metalorganic chemical vapor deposition of TiO2:N anatase thin film on Si substrate”, Appl. Phys. Lett., 66(7), (Feb. 1995),815-816.Applicant
Lee, L P., et al., “Monolithic 77 K dc Squid magnetometer”, Applied Physics Letters, 59(23), (Dec. 1991),3051-3053.Applicant
Lee, C. H., et al., “MOS Characteristics of Ultra Thin Rapid Thermal CVD ZrO2 and Zr Silicate Gate Dielectrics”, Electron Devices Meeting, 2000. IEDM Technical Digest. International, (2000),27-30.Applicant
Lee, C H., et al., “MOS Devices with High Quality Ultra Thin CVD ZrO2 Gate Dielectrics and Self-Aligned TaN and TaN/Poly-Si Gate electrodes”, 2001 Symposium on VLSI, Technology Digest of Technical Papers, (2001), 137-138.Applicant
Lee, et al., “Ultrathin Hafnium Oxide with Low Leakage and excellent Reliability fo rAlternative Gae Dielecric Application”, IEEE Technical Digest of International Electron Devices Meeting 1999, (1999), 133-136.Applicant
Leskela, M. , et al., “ALD precursor chemistry: Evolution and future challenges”, J. Phys. IV France, 9, (1999),837-852.Applicant
Luan, et al., “High Quality Ta2O5 Gate Dielectrics and T[. . . ]”, IEEE Technical Digest of Int. Elec. Devices Mtng 1999, (1999), 141-142.Applicant
Lucovsky, G , et al., “Microscopic model for enhanced dielectric constants in low concentration SiO/sub 2/-rich noncrystalline Zr and Hf silicate alloys”, Applied Physics Letters, 77(18), (Oct. 2000),2912-2914.Applicant
Luo, Z J., et al., “Ultra-thin ZrO2 (or Silicate) with High Thermal Stability for CMOS GAte Applications”, 2001 Symposium on VLSI Technology Digest of Technical Papers, (2001), 135-136.Applicant
Martin, et al., “Ion-beam-assisted deposition of thin films”, Applied Optics, 22(1), (1983), 178-184.Applicant
Molodyk, A A., et al., “Volatile Surfactant-Assisted MOCVD: Application to LaAl03 Thin Film Growth”, Chemical Vapor Depostion, 6(3), (Jun. 2000), 133-138.Applicant
Molsa, Heini , et al., “Growth of yttrium oxide thin films from beta -diketonate precursor”, Advanced Materials for Optics and Electronics, 4(6), (Nov.-Dec. 1994),389-400.Applicant
Nakagawara, Osamu , et al., “Electrical properties of Zr, Sn)TiO4 dielectric thin films prepared by pulsed laser deposition”, Journal of Applied Physics, 80(1), (Jul. 1996),388-392.Applicant
Nakajima, Anri , et al., “Atomic-layer deposition of ZrO/sub 2/ with a Si nitride barrier layer”, Applied Physics Letters, vol. 81, No. 15, (Oct. 2002),2824-2826.Applicant
Nakajima, Anri , et al., “NH/sub 3/-annealed atomic-layer-deposited silicon nitride as a high-k gate dielectric with high reliability”, Applied Physics Letters, 80(7), (Feb. 2002), 1252-1254.Applicant
Nakajima, Anri , “Soft breakdown free atomic-layer-deposited silicon-nitride/SiO/sub 2/ stack gate dielectrics”, International Electron Devices Meeting. Technical Digest, (2001),6.5.1-4.Applicant
Neumayer, D A., et al., “Materials characterization of ZrO/sub 2/-SiO/sub 2/ and HfO/sub 2/-SiO/sub 2/ binary oxides deposited by chemical solution deposition”, Journal of Applied Physics, 90(4), (Aug. 15, 2001), 1801-1808.Applicant
Niilisk, A , “Atomic-scale optical monitoring of the initial growth of TiO2 thin films”, Proceedings of the SPIE—The International Society for Optical Engineering, 4318, (2001), 72-77.Applicant
Oates, D E., et al., “Surface impedance measurement of YBa/sub 2/Cu/sub 3/O/sub 7-x/ thin films in stripline resonators”,IEEE Transactions on Magnetics, vol. 27, No. 2, pt.2, (Mar. 1991),867-871.Applicant
Oh, C B., et al., “Manufacturable embedded CMOS 6T-SRAM technology with high-k gate dielectric device for system-on-chip applications”, Technical Digest of International Electron Devices Meeting 2002, (2002),423-426.Applicant
Osten, H J., et al., “High-k Gate Dielectrics with Ultra-low Leakage Current Based on Praseodymium Oxide”, Technical Digest of IEDM, (2000)653-656.Applicant
Park, Jaehoo , et al., “Chemical vapor deposition of HfO/sub 2/thin films using a novel carbon-free precursor: characterization of the interface with the silicon substrate”, Journal of the Electrochemical Soceity, 149(1), (2002),G89-G94.Applicant
Park, Byung-Eun , et al., “Electrical properties of LaAlO3/Si and Sr0.8Bi2.2Ta2O9/LaAlO3/Si structures”, Applied Physics Letters, 79(6), (Aug. 2001),806-808.Applicant
Perkins, Charles M., et al., “Electrical and materials properties of ZrO2 gate dielectrics grown by atomic layer chemical vapor deposition”, Applied Physics Letters, 78(16), (Apr. 2001),2357-2359.Applicant
Poveshchenko, V P., et al., “Investigation of the phas composition of films of zirconium, hafnium and yttrium oxides”, Soviet Journal of Optical Technology, 51(5), (1984),277-279.Applicant
Qi, W , “MOSCAP and MOSFET characteristics using ZrO2 gate dielectric deposited directly on Si”, IEDM—Technical Digest, (1999),145-148.Applicant
Qi, Wen-Jie , et al., “Performance of MOSFET's with ultra thin ZrO/sub 2/ and Zr silicate gate dielectrics”, 2000 Symposium on VLSI Technology, Digest of Technical Papers, (2000),40-41.Applicant
Rahtu, Antti , et al., “Atomic Layer Deposition of Zirconium Titanium Oxide from Titanium Isopropoxide and Zirconium Chloride”, Chemistry of Materials, 13(5), (May 2001), 1528-1532.Applicant
Ramakrishnan, E S., et al., “Dielectric properties of radio frequency magnetron sputter deposited zirconium titanate-based thin films”, Journal of the Electrochemical Society, 145(1), (Jan. 1998),358-362.Applicant
Rayner Jr., G , et al., “The structure of plasma-deposited and annealed pseudo-binary ZrO2-SiO2 alloys”, Materials Research Society Symposium—Proceedings, 611, (2000),C131-C139.Applicant
Ritala, Mikko , “Atomic Layer Epitaxy Growth of Titanium, Zirconium and Hafnium Dioxide Thin Films”, Annales Academiae Scientiarum Fennicae, (1994) 24-25.Applicant
Ritala, Mikko, et al., “Zirconium dioxide thin films deposited by ALE using zirconium tetrachloride as precursor”, Applied Surface Science, 75, (Jan. 1994),333-340.Applicant
Robertson, J. , “Band offsets of wide-band-gap oxides and implications for future electronic devices”, Journal of Vacuum Science & Technology B (Microelectronics and Nanometer Structures), 18(3), (May-Jun. 2000), 1785-1791.Applicant
Rossnagel, S M., et al., “Plasma-enhanced atomic layer deposition of Ta and Ti for Interconnect diffusion barriers”, Journal of Vacuum Science & Technology B(Microelectronics and Nanometer Structures), 18(4), (Jul. 2000),2016-2020.Applicant
Rotondaro, A L., et al., “Advanced CMOS Transistors with a Novel HfSiON Gate Dielectric”, Symposium on VLSI Technology Digest of Technical Papers, (2002), 148-149.Applicant
Ryu, Changsup , “Barriers for Copper Interconnections”, Solid State Technology, 42(4), (Apr. 1999),53-56.Applicant
Saito, Y , “High-Integrity Silicon Oxide Grown at Low-temperature by Atomic Oxygen Generated in High-Density Krypton Plasma”, Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials, (1999), 152-153.Applicant
Shanware, A , et al., “Reliability evaluation of HfSiON gate dielectric film with 12.8 a SiO2 equivalent thickness”, International Electron Devices Meeting. Technical Digest, (2001), 137-140.Applicant
Shin, Chang H., et al., “Fabrication and Characterization of MFISFET Using Al2O3 Insulating Layer for Non-volatile Memory”, 12th International Symposium in Integrated Ferroelectrics, (Mar. 2000), 9 pages.Applicant
Sneh, Ofer , et al., “Thin film atomic layer deposition equipment for semiconductor processing”, Thin Solid Films, 402(1-2), (Jan. 1, 2002),248-261.Applicant
Song, Hyun-Jung , et al., “Atomic Layer Deposition of Ta2O5 Films Using Ta(OC2H5)5 and NH3”, Ultrathin SiO/sub 2/ and High-K Materials for ULSI Gate Dielectrics. Symposium, (1999),469-471.Applicant
Souche, et al., “Visible and infrared ellipsometry study of ion assisted SiO2 films”, (1998),676-681.Applicant
Suntola, T. , “Atomic Layer Epitaxy”, Handbook of Crystal Growth, 3; Thin Films of Epitaxy, Part B: Growth Mechanics and Dynamics, Amsterdam, (1994),602-663.Applicant
Takemoto, J.H., et al., “Microstrip Resonators and Filters Using High-TC Superconducting Thin Films on LaAlO3”, IEEE Transaction on Magnetics, 27(2), (Mar. 1991),2549-2552.Applicant
Tarre, A , et al., “Comparative study of low-temperature chloride atomic-layer chemical vapor deposition of TiO2 and SnO2”, Applied Surface Science, 175-176, (May 2001),111-116.Applicant
Tavel, B , et al., “High performance 40 nm nMOSFETs with HfO/sub 2/ gate dielectric and polysilicon damascene gate”, Technical Digest of International Electron Devices Meetings 2002, (2002),419-432.Applicant
Van Dover, R. B., et al., “Amorphous lanthanide-doped TiOx dielectric films”, Applied Physics Letters, 74(20), (May 17, 1999),3041-3043.Applicant
Van Dover, R B., et al., “Deposition of Uniform Zr-Sn-Ti-O Films by On-Axis Reactive Sputtering”, IEEE Electron Device Letters, 19(9), (Sep. 1998),329-331.Applicant
Van Dover, R. B., et al., “Discovery of a useful thin-film dielectric using a composition-spread approach”, Nature, 392(6672), (Mar. 12, 1998),162-4.Applicant
Viirola, H , “Controlled growth of antimony-doped tin dioxide thin films by atomic layer epitaxy”, Thin Solid Films, 251, (Nov. 1994),127-135.Applicant
Visokay, M R., “Application of HfSiON as a gate dielectric material”, Applied Physics Letters, 80(17), (Apr. 2002),3183-3185.Applicant
Wilk, G D., et al., “Hafnium and zirconium silicates for advanced gate dielectrics”, Journal of Applied Physics, 87(1), (Jan. 2000),484-492.Applicant
Wilk, G. D., et al., “High-K gate dielectrics: Current status and materials properties considerations”, Journal of Applied Physics, 89(10), (May 2001),5243-5275.Applicant
Wolf, Stanley , et al., “Future Trends in Sputter Deposition Processes”, In: Silicon Processing of the VLSI Era, vol. 1, Lattice Press,(1986),374-380.Applicant
Wolfram, G , et al., “Existence range, structural and dielectric properties of ZrxTiySnzO4 ceramics (x + y =2)”, Materials Research Bulletin, 16(11), (Nov. 1981), 1455-63.Applicant
Yamaguchi, Takeshi, “Band Diagram and Carrier Conduction Mechanism in ZrO2/Zr-silicate/Si MIS Structure Fabricated by Pulsed-laser-ablation Deposition”, Electron Devices Meeting, 2000. IEDM Technical Digest, International, (2000),19-22.Applicant
Yamaguchi, Takeshi , et al., “Study on Zr-Silicate Interfacial Layer of ZrO2-MIS Structure FAbricated by Pulsed Laser Ablation Deposition Method”, Solid State Devices and Materials, (2000),228-229.Applicant
Zhang, H. , “Atomic Layer Deposition of High Dielectric Constant Nanolaminates”, Journal of The Electrochemical Society, 148(4), (Apr. 2001),F63-F66.Applicant
Zhang, H , et al., “High permittivity thin film nanolaminates”, Journal of Applied Physics, 87(4), (Feb. 2000), 1921-1924.Applicant
Zhu, W , et al., “HfO2 and HfAlO for CMOS: Thermal Stability and Current Tranport”, IEEE International Electron Device Meeting 2001, (2001),463-466.Applicant
Zucker, O , et al., “Application of Oxygen Plasma Processing to Silicon Direct Bonding”, Sensors and Actuators A, 36, (1993),227-231.Applicant

Abstract