Combined single-ended and differential signaling interface

[0002] This application is a continuation-in-part of application of U.S. Ser. No. 09/062,343 filed on Apr. 17, 1998 now abandoned.

[0003] 1. Field of the Invention

[0004] The present invention relates generally to the field of interface circuits, and more particularly, to interface circuitry for providing selectable single-ended and differential signal output from a CMOS image sensor to an external digital signal processor.

[0005] 2. Description of Related Art

[0006] One of the advantages of CMOS image sensors (CMOS imagers) over CCD imagers is that the CMOS imager chip can include digital signal processing circuitry. In practice, the signal processing is more often performed on a companion chip, in order to provide greater application flexibility. However, CMOS imagers often have integrated analog to digital converters to convert the analog signal to a digital bit stream that can be processed by the companion chip. The digitized information then must be transferred to companion chip or other external devices for picture storage, processing, or transmission. A single-ended interface is the most common and simplest implementation for data transfer. An example of a single-ended interface is shown in FIG. 1. A driver circuit 2 in the CMOS imager 1 outputs a signal to the companion processing chip 3. A receiver 4 receives and amplifies the signal for further processing. FIG. 2 is a schematic of one possible CMOS implementation of the above-described single-ended interface.

[0007] A differential interface can minimize power and noise generation as compared to a single-ended interface, but generally requires twice the number of signal lines. An example of conventional low voltage differential signaling (LVDS) circuit 11 is shown in FIG. 3. The LVDS 11 circuit includes a current source I₁(nominal 3.5 mA) which drives one of the differential pair lines 13, 15. The receiver 17 has a high DC impedance (it does not source or sink DC current), so the majority of driver current flows across the 100 Ω termination resistor R₁generating about 350 mV across the receiver inputs 19, 21. When the driver 23 switches, it changes the direction of current flow across the resistor R₁, thereby creating a valid “one” or “zero” logic state.

[0008] LVDS technology saves power in several important ways. The power dissipated by the load (the 100 Ω termination resistor R₁is a mere 1.2 mW. In comparison, an RS 422 driver typically delivers 3 volts across a 100 Ω termination, for 90 mW power consumption—75 times more than LVDS. Similarly, LVDS devices 11 require roughly one-tenth the power supply current of PECL/ECL devices.

[0009] Aside from the power dissipated in the load and static I_CCcurrent, LVDS also lowers system power requirements through its CMOS current-mode driver design. This design greatly reduces the frequency component of I_CC. The I_CCvs. Frequency plot for LVDS 11 is virtually flat between 10 MHz and 100 MHz for the quad devices (<50 mA total for driver+receiver at 100 MHz). In contrast, single-ended, TTL/CMOS transceivers exhibit dynamic power consumption which increases exponentially with frequency.

[0010] To help ensure reliability, LVDS receivers 17 have a fail-safe feature that guarantees the output to be in a known logic state (HIGH) under certain fault conditions. These conditions include open, shorted, or terminated receiver inputs. If the driver 23 loses power, is disabled or is removed from the line, while the receiver 17 stays powered on with inputs terminated, the receiver output remains in a known state with the fail-safe feature.

[0011] If LVDS receivers 17 did not have the fail-safe feature and one of the fault conditions occurred, any external noise above the receiver thresholds could trigger the output and cause an error. A receiver without fail-safe could even go into oscillation under certain fault conditions. The fail-safe features ensure that the receiver output will be a HIGH—rather than an unknown state—under fault conditions.

[0012] FIG. 4 illustrates CMOS video imaging sensing circuitry according to the preferred embodiment disclosed in co-pending U.S. application Ser. No 09/062,343. This circuitry includes a CMOS image sensor chip 50 and an image processor chip 52. The CMOS image sensor chip 50 typically includes a number of light responsive CMOS pixel sensors which develop analog signals representative of an image. These analog signals are then A to D converted by the ADC circuit to form digital signals Din₀, Din₁. . . Din_n. The image processor chip 52 includes a data processor 53 which performs various manipulations of the image data such as compression and color processing. The processor 53 may be software driven or a hardware embodiment.

[0013] As may be seen, the circuit of FIG. 4 employs a plurality of LVDS circuits 11. Each circuit 11 includes a respective driver 54 and a respective receiver 56. Each driver 54 receives a respective input signal Din₀, Din₁. . . Din_n, which are digital logic levels of, for example, 3.3 volts for logic “1” and zero volts for logic “0”. Changes in state in these signals are transmitted over the differential lines to the respective receivers 56. Each receiver 56 generates a respective output signal Dout₀, Dout₁, . . . Dout_n, which are at the several hundred milli-volt level.

[0014] It is possible to use a differential interface as shown in FIG. 4 instead of a single-ended interface on the imager, but existing image processing devices may only support the common single-ended interface of FIG. 1 and not the differential interface. It is possible to place both interfaces on the imager in order to support both types of companion chips, but this would add pins and cost.

[0015] The best solution would be to implement an interface that could be selected to either support a single-ended interface or a differential interface using the same number of pins (i.e. without requiring twice the number of pins for the differential interface). This would allow flexibility in supporting both commonly available single-ended image processing devices and new image processing devices with the low noise differential interface.

[0016] Using a small number of digital data interface pins will minimize power, IC cost, package cost, and printed circuit board size. However, the data rate per pin is inversely proportional to the number of pins. Higher data rates will result in higher noise such as electromagnetic interference and chip output ground bounce. Also, if the number of digital data interface pins is less than the data word size, then some form of synchronization is often required, which can increase complexity and cost.

[0017] One tested imager device has a 4 bit single-ended pixel data interface. The data word size is 12 bits, so each pixel's data is transferred in three clocks, 4 bits at a time. Because multiple clock cycles are required to transfer each pixel data, synchronization codes are required so that the image processing device can tell whether a 4 bit transfer is the most significant, middle significant, or least significant 4 bits of the pixel data. This synchronization adds complexity and cost to the system.

[0018] As imagers are developed with greater resolution, the number of pixels per frame is much higher. In order to limit the per pin data rate to a reasonable speed, the interface was widened to the width of the 10 bit pixel data. However, the data rate is still high, and will result in fast signal transition times and in ground bounce. Both of these effects may couple noise into the imager silicon substrate, increasing the noise in the image.

[0019] A differential interface may be used, but usually this results in twice the number of pins, because two pins are used for each bit transfer, one for the “true” value (normal value) and another for the “complement” value. Thus, there is a need for an improved interface circuit that would allow either a single-ended or a differential output and using as few pins as possible.

[0020] The present invention is a data interface for CMOS imagers that can be either a single-ended interface or a differential interface. The single-ended interface provides compatibility with many existing external devices. Further, providing a differential interface allows a lower noise and a lower power interface for external devices that can support a differential signal. The combined single-ended and differential signal interface does not increase the number of pins required for a single-ended only interface. The data transfer width is set to the word width, which allows a fixed timing relationship between the clock edge and data transfer in both single-ended and differential modes. In single-ended mode, the data is transferred once per clock, but in the differential mode, the data is transferred twice per clock, once on each clock edge. This fixed timing relationship eliminates the need for and cost of explicit bit synchronization.

[0021] The exact nature of this invention, as well as its objects and advantages, will become readily apparent from consideration of the following specification as illustrated in the accompanying drawings, in which like reference numerals designate like parts throughout the figures thereof, and wherein:

[0022] FIG. 1 is a diagram illustrating a typical single-ended interface implemented in CMOS;

[0023] FIG. 2 is a schematic diagram of the single-ended interface of FIG. 1;

[0024] FIG. 3 is a schematic diagram of a differential interface circuit;

[0025] FIG. 4 is a diagram illustrating an application of the differential interface circuit of FIG. 3 in an imager; and

[0026] FIG. 5 is a schematic diagram of the present invention according to one embodiment.

[0027] The following description is provided to enable any person skilled in the art to make and use the invention and sets forth the best modes contemplated by the inventor for carrying out the invention. Various modifications, however, will remain readily apparent to those skilled in the art, since the basic principles of the present invention have been defined herein specifically to provide an interface circuit for providing a selectable single-ended and differential signal output from a CMOS image sensor to an external digital signal processor.

[0028] The present invention is a data interface that can be either a single-ended interface or a differential interface. A preferred embodiment of the present invention will now be described with reference to FIG. 5. The circuit 100 of FIG. 5 is selectable to provide either a single-ended output or a differential output. If a single-ended output is desired, the ENSE signal is enabled, and if a differential output is desired, the ENDF signal is enabled. Since only one mode can be selected at a time, the ENSE and ENDF signals are complementary. Thus, a single register bit for selecting the type of output may be used. The interface is simplest when the single-ended data interface width is equal to the pixel word width. In the preferred embodiment, the data width is 10 bits, so 10 pins are used. FIG. 5 illustrates the operation for two pins of the circuit, but those skilled in the art will understand how to duplicate the necessary circuitry to produce the desired number of output pins. All of the data bits are transferred on one edge of the clock, for instance on the rising edge of the clock.

[0029] For single-ended operation, the internal digitized signals I_D0and I_D1are clocked through flip-flops 104, 105 and the single-ended output drivers 106, 107 drive the output signal lines. The single-ended outputs D0 and D1 are thus provided to the companion chip or other off-chip circuitry. The differential circuitry 108 is not enabled, and thus does not interfere with the single-ended operation.

[0030] When a differential output is desired, however, the differential circuitry 108 is enabled, and the single-ended circuitry 106, 107 is disabled. In the differential mode, half of the bits are transferred on one edge of the clock and the other half on the other edge of the clock. This clocking scheme uses the same number of pins as used for the single-ended interface. Thus, no explicit synchronization is required when the relationship of clock edge to data transfer is kept constant. The internal digitized signals I_D0and I_D1are clocked through flip-flops 101, 102 and a multiplexer 103 such that on a rising clock edge on signal is selected and on a falling clock edge the other single is selected. The output of the multiplexer 103 is provided to the differential interface circuitry 108 to produce both the normal output and the complement output signal. So on one half of the clock cycle, half the bits are produced in differential form, and on the other half of the clock cycle, the remaining bits are produced. Thus, a differential output is produced without requiring twice the number of pins, or complicated bit synchronization schemes that slow the data transfer.

[0031] All known prior art CMOS imagers have used single-ended interfaces. Allowing the use of a single-ended interface gives the opportunity of interfacing to many existing external devices. Allowing the use of a differential interface will allow a lower noise and a lower power interface. Using a combined single-ended and differential signal interface will not increase the number of pins required for a single-ended only interface. Setting the data transfer width to the word width allows a fixed timing relationship between the clock edge and data transfer in both single-ended and differential modes. This fixed timing relationship eliminates the need for and cost of explicit synchronization. The present invention may be used in place of the exclusively differential interface illustrated in FIG. 4, to provide greater interface flexibility.

[0032] Those skilled in the art will appreciate that various adaptations and modifications of the just-described preferred embodiment can be configured without departing from the scope and spirit of the invention. Therefore, it is to be understood that, within the scope of the appended claims, the invention may be practiced other than as specifically described herein.