Semiconductor package including stacked semiconductor chips

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor package.

[0004] 2. Description of the Background Art

[0005] With higher functionality of personal computers, memory has to be larger in capacity and faster in speed in semiconductor packages. As semiconductor packages corresponding to the increased speed, BGA (Ball Grid Array) packages are most common which require shorter interconnection distances within packages.

[0006] DRAMs (Dynamic Random Access Memory) are representative semiconductor chips used as memory. A DRAM generally has a bonding pad arranged on the center portion of the main surface of the chip. Therefore in mounting a DRAM on a substrate, the substrate is provided with an opening portion like a window frame and the DRAM is bonded on the substrate such that that part of the DRAM at which a bonding pad is arranged can be seen from this opening portion. Here, for the sake of illustration, it is assumed that DRAM is arranged on the upper side of the substrate with the bonding pad directed downward being exposed from the opening portion of the substrate. A bonding pad is also provided at the surrounding of the opening portion of the lower surface of the substrate. Through this opening portion, the bonding pad on the DRAM side is connected to the bonding pad on the substrate side using wire. Thereafter the opening portion is sealed with resin to wrap up that part of the lower surface of the DRAM at which the boding pad is arranged and the wire. The upper side of DRAM is also sealed with resin for protection. Solder balls for external connection are provided on the lower surface of the substrate. This state is generally called a BGA package.

[0007] In order to increase a memory capacity, a technique for stacking the aforementioned BGA packages may be contemplated. When two BGA packages are simply stacked to form a stacked package, a resin sealing portion for protecting a wire bonding portion is protruded on the lower surface of the upper BGA package while a resin sealing portion for protecting the DRAM body itself is protruded on the upper surface of the lower BGA package. Therefore when two BGA packages are stacked, the distance between the substrates is inevitably increased because of the heights of the resin sealing portions respectively protruding from the upper and lower substrates. When the upper and lower substrates are connected with solder balls for external connection of the upper BGA package, it becomes necessary to use a solder ball with a large diameter. To reduce the area occupied by the stacked package, the arrangement of the solder balls is preferably in a line for one side even in the case of the solder balls for connection between substrates. In one line, however, the spacing between solder balls is so narrowed that short-circuit is likely to occur. Furthermore, in the case of such a stacked package, as for the interconnection distance from the solder ball for external connection to DRAM included in each of the upper and lower BGA packages, the upper one is largely longer than the lower one thereby causing a transmission delay of a signal.

[0008] The object of the present invention is to provide a semiconductor package that allows memory to be increased in capacity with a reduced package size as a whole, and is free from a transmission delay between upper and lower levels.

[0009] In order to attain the aforementioned object, a semiconductor package in accordance with the present invention includes: an upper substrate having an opening portion; a solder ball for connection between substrates that is arranged on a lower side of the upper substrate; a lower substrate arranged on a lower side of the solder ball for connection between substrates and having an opening portion; a solder ball for external connection connected on a lower surface of the lower substrate; a first semiconductor chip arranged on an upper surface of the upper substrate; and a second semiconductor chip arranged on a lower surface of the lower substrate. The aforementioned first semiconductor chip is electrically connected to the solder ball for connection between substrates through the opening portion of the upper substrate. The aforementioned second semiconductor chip is electrically connected to the solder ball for connection between substrates through the opening portion of the lower substrate. The aforementioned solder ball for connection between substrates is electrically connected to the solder ball for external connection.

[0010] The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

[0011] FIG. 1 is a planar view of a semiconductor package in accordance with a first embodiment of the present invention.

[0012] FIG. 2 is a side view of the semiconductor package in accordance with the first embodiment of the present invention.

[0013] FIG. 3 is an underside view of the semiconductor package in accordance with the first embodiment of the present invention.

[0014] FIG. 4 is a front view of the semiconductor package in accordance with the first embodiment of the present invention.

[0015] FIG. 5 is a cross sectional view taken along a line V—V viewed in the direction of arrows.

[0016] FIG. 6 is an underside view of the upper BGA package with a resin sealing portion removed for the sake of illustration where the semiconductor package in accordance with the first embodiment of the present invention is separated into two upper and lower BGA packages.

[0017] FIG. 7 is an underside view of the lower BGA package with a resin sealing portion removed for the sake of illustration where the semiconductor package in accordance with the first embodiment of the present invention is separated into two upper and lower BGA packages.

[0018] FIG. 8 is an illustration of an interconnection length for the upper and lower semiconductor chips of the semiconductor package in accordance with the first embodiment of the present invention.

[0019] FIG. 9 is an underside view of the semiconductor package in accordance with a second embodiment of the present invention.

[0020] FIG. 10 is a front view of the semiconductor package in accordance with the second embodiment of the present invention.

[0021] FIG. 11 is a cross sectional view of the semiconductor package in accordance with the second embodiment of the present invention.

[0022] (First Embodiment)

[0023] Referring to FIGS. 1-8, a semiconductor package in accordance with a first embodiment of the present invention will be illustrated. The planar view of the semiconductor package is shown in FIG. 1 and the underside view is shown in FIG. 3. Similarly, the front view is shown in FIG. 4 and the side view is shown in FIG. 2. A cross sectional view taken along a line V—V viewed in the direction of arrows in FIG. 1 or 2 is schematically shown in FIG. 5. As shown in FIG. 5, this semiconductor package includes an upper substrate 13a, and a lower substrate 13bconnected through solder balls on the upper side thereof. Upper substrate 13aand lower substrate 13beach has an opening portion at the center. Upper substrate 13aand lower substrate 13beach has bonding pads on the surface of the surrounding of the opening portion. In a position in FIG. 5, upper substrate 13aand lower substrate 13bare arranged in the direction in which the bonding pads are opposed to each other.

[0024] Semiconductor chip 7a, 7bis for example a DRAM and has a structure having a plurality of bonding pads arranged at the center on the main surface. Semiconductor chip 7ais affixed on the upper surface of upper substrate 13asuch that the bonding pad is exposed downward from the opening portion of upper substrate 13a. Semiconductor chip 7bis affixed on the lower surface of lower substrate 13bsuch that the bonding pad is exposed upward from the opening portion of lower substrate 13b. In other words, semiconductor chips 7aand 7bare arranged in the direction in which the bonding pads are opposed to each other.

[0025] The bonding pads of semiconductor chips 7aand 7band the bonding pads of upper substrate 13aand lower substrate 13bare electrically connected with wires 12 as shown in FIG. 5. Those wire bonding portions are sealed with resin, serving as resin sealing portions 4aand 4brespectively above and below. Resin sealing portion 4aand resin sealing portion 4bare in close proximity above and below but not connected to each other, and they are separately formed resin portions.

[0026] On the upper side of upper substrate 13a, a resin sealing portion 3ais formed to cover the body of semiconductor chip 7afor the purpose of protecting the body of semiconductor chip 7a. On the lower side of lower substrate 13b, a resin portion to cover the body of semiconductor chip 7bdoes not exist.

[0027] In the proximity of the outer edge of the lower surface of lower substrate 13b, a solder ball 6 for external connection is arranged.

[0028] A plurality of lands 11aare arranged on the lower surface of upper substrate 13aand a plurality of lands 11bare also arranged on the upper surface of lower substrate 13b. The lower surface of upper substrate 13aseen from below is shown in FIG. 6 and the upper surface of lower substrate 13bseen from above is shown in FIG. 7 where the semiconductor package in accordance with the present embodiment is separated into upper and lower BGA packages. In a comparison of FIG. 6 and FIG. 7, land 11aand land 11bare arranged in a mirror-image relation to each other, that is, in mirror symmetry. Therefore when upper substrate 13ais affixed to lower substrate 13b, the lands are opposed to each other respectively. Where the lands are opposed respectively, the lands are electrically connected to each other with solder balls 5 interposed therebetween. This state is partially shown in detail, taking solder ball 5 on the right end as an example in FIG. 5. A signal path extending from land 11bis electrically drawn onto the lower surface of lower substrate 13bthrough through-hole 14 passing through lower substrate 13b, to connect to any one of solder balls 6.

[0029] Lands 11aand 11bare electrically connected to any bonding pads 9aand 9bwith substrate wires 10aand 10barranged on the surfaces of the substrates, respectively.

[0030] It is noted that all the lands are not necessarily in mirror symmetry. The lands in mirror symmetry may be part of a plurality of lands and another part of lands are arranged in a manner different between the upper and lower levels.

[0031] As shown in FIG. 6, a bonding pad 8aof semiconductor chip 7aon the upper side is exposed from an opening portion 15aof upper substrate 13a. As shown in FIG. 7, a bonding pad 8bof semiconductor chip 7bon the lower side is exposed from an opening portion 15bof lower substrate 13b. As shown in FIG. 6, boding pad 8aand bonding pad 9aare connected with wire 12, and as shown in FIG. 7, bonding pad 8band bonding pad 9aare connected with wire 12. As can be seen from FIGS. 6 and 7 in comparison, the connection patterns of wire 12 are opposite to each other between the upper level and the lower level. By changing the connection pattern of wire 12 between the upper and lower levels in this way, a connection that appropriately corresponds to the lands arranged in mirror symmetry to each other on the upper and lower levels is realized while the arrangement pattern of the bonding pads of the semiconductor chip is common to the upper and lower levels.

[0032] As an example of the present embodiment, the specific sizes will be shown. In this example, the height of resin sealing portion 4aor 4bprotruded from the substrate surface is not more than 0.15 mm. The arrangement pitch of lands provided on each substrate for connecting solder balls 5 is 0.8 mm. The diameter of solder ball 5 is 0.45 mm. However, this is the case where the total height of resin sealing portions 4aand 4bfrom the substrate surfaces is 0.3 mm. If the total height of resin sealing portions 4aand 4bfrom the substrate surfaces is smaller than 0.3 mm, the diameter of solder ball 5 may be made smaller.

[0033] Solder balls 6 for external connection are arranged with a pitch of 0.5 mm in a line on one side. In case of a pitch of 0.5 mm, the diameter of solder ball 6 may be around 0.3 mm in order to prevent short-circuit. Therefore the height that is protruded from the substrate surface of semiconductor chip 7bon the lower side of lower substrate 13bshould be not more than 0.25 mm.

[0034] In the semiconductor package in accordance with the present embodiment, resin sealing portions 4aand 4bof the wire connection portions are arranged in the direction in which they are opposed to each other to be stacked. Since the height of the resin sealing portion covering wire 12 that is protruded from the substrate surface is generally lower than the height of the resin sealing portion covering semiconductor chip 7aor 7bbody that is protruded from the substrate surface, the distance between the upper and lower substrates can be reduced in the semiconductor package in accordance with the present embodiment, as compared with the conventional stacked structure. Therefore solder ball 5 having a small diameter can be used for the connection between the substrates. Accordingly the arrangement pitch of solder balls 5 can be made small. As a result, an area necessary to arrange solder balls 5 can be reduced.

[0035] In the semiconductor package in accordance with the present embodiment, the body of semiconductor chip 7bthat is protruded on the lower side of lower substrate 13bis lower than solder ball 6 and is not sealed with resin as it is less necessary to be protected. Therefore, as solder ball 6 for external connection arranged on the lower surface of lower substrate 13b, one with a smaller diameter can be used. Therefore the arrangement pitch of solder balls 6 can be reduced. As a result, an area necessary to arrange solder balls 6 can be reduced.

[0036] In the semiconductor package in accordance with the present embodiment, by changing the connection pattern of wire 12 between the upper and lower levels, a connection that appropriately corresponds to the lands arranged in mirror symmetry to each other on the upper and lower levels is realized while the arrangement pattern of the bonding pads of the semiconductor chip is common to the upper and lower levels. Therefore as to semiconductor chips, products in mirror symmetry need not be provided and common products can efficiently be used.

[0037] In the semiconductor package in accordance with the present embodiment, as indicated by bold lines C and D in FIG. 8, the upper and lower semiconductor chips are approximately equal in the interconnection distance to the electrode for external connection. Therefore the problem of a transmission delay between the upper level and the lower level can be eliminated.

[0038] (Second Embodiment)

[0039] Referring to FIGS. 9 to 11, the semiconductor package in accordance with a second embodiment of the present invention will be described. The semiconductor package in accordance with the present embodiment is similar to that illustrated in the first embodiment in the basic structure but is different in some points. First, the arrangement of solder balls 6 for external connection is different. More specifically, as shown in FIG. 9, solder balls 6 are arranged in two lines on one side in a zigzag pattern. As to the specific sizes, as shown in FIG. 9, the pitch in the longitudinal direction is 0.8 mm, and the center-to-center distance between the outer line and the inner line is 0.69 mm. The outer line is shifted from the inner line by 0.4 mm in arrangement.

[0040] Next, the present embodiment is different from the first embodiment in that a resin sealing portion 3bcovering semiconductor chip 7bis provided.

[0041] In this manner, if solder balls 6 for external connection are arranged in two lines on one side in a zigzag pattern, the number of solder balls that can be arranged can largely be increased only by increasing the package width.

[0042] Furthermore, as described above, when the pitch of solder balls 6 in the longitudinal direction is 0.8 mm, the diameter of solder ball 6 may be around 0.45 mm in order to prevent short-circuit. Therefore a solder ball having a diameter of around 0.3 mm is used in the first embodiment whereas a solder ball having a larger diameter of about 0.45 mm can be used in the present embodiment. With a larger diameter of a solder ball for external connection, the upper limit of the protrusion of the resin sealing portion that is allowable on the lower side of lower substrate 13bis increased from 0.25 mm of the first embodiment to 0.35 mm. Therefore semiconductor chip 7bprotruding downward may also be covered with resin for protecting the body itself. It is for this reason that resin sealing portion 3bis provided in FIG. 11.

[0043] It is noted that even if the solder balls for external connection are arranged in two lines on one side, an arrangement other than a zigzag pattern may be possible. However the zigzag pattern is preferable as it allows for a higher density.

[0044] Furthermore, even if the solder balls for external connection are arranged in two lines on one side as in the present embodiment, whether resin sealing portion 3bis provided for semiconductor chip 7bprotruding downward may be selected as appropriate.

[0045] In accordance with the present invention, the distance between the upper and lower substrates can be reduced as compared with the conventional structure having BGA packages simply stacked in the same direction. Therefore a solder ball having a small diameter can be used for the connection between the substrates. Accordingly the arrangement pitch of solder balls can be reduced. As a result, an area necessary to arrange the solder balls can be reduced.

[0046] Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.