Clock divider and method for dividing a clock signal in a DLL circuit

[0002] A clock divider and a method for dividing a clock signal in a DLL circuit of a semiconductor memory device are disclosed.

[0003] Generally, clock signals are used as reference signals to set operation timing in a system or a circuit, and to ensure high-speed operation of the system or circuit without any errors. When a clock signal from an external circuit is used internally within a circuit, a time delay, i.e., a clock skew may be generated due to the internal circuit. A delay locked loop (DLL) circuit may be used to ensure that the internal clock signal of the circuit has the same phase as the external clock signal by compensating for the clock skew.

[0004] Important characteristics of a DLL circuit include small size, low jitter, and fast locking time. These characteristics may require semiconductor memory devices of the future, which may also require low power consumption and high-speed operation. A DLL circuit is less influenced by noise than a phase locked loop (PLL) circuit. As a result, a DLL circuit may be used in a synchronous semiconductor memory device, such as, for example, a DDR SDRAM (double data rate synchronous DRAM) or the like. A DLL circuit of a register type is frequently used in many kinds of DLL circuits.

[0005] FIG. 1 is a block diagram illustrating a conventional resister-control-type DLL circuit of a typical DDR SDRAM.

[0006] The conventional register-control-type DLL circuit of the typical DDR SDRAM includes a clock buffer 110, a first clock divider 130, a delay circuit 150, a clock multiplexer 170, a second clock divider 190, a delay model 210, a phase comparator 230, and a delay controller 250.

[0007] The clock buffer 110 converts a voltage level of a high frequency external clock signal CLK and a high frequency external clock inversion signal CLKB, both of which are supplied from an external circuit, into a power supply voltage level VDD. The first clock divider 130 outputs a low frequency reference clock signal by dividing a high frequency clock signal CLKD of a VDD level by n, wherein n is a positive integer, (e.g., n is 4). The delay circuit 150 delays the high frequency clock signal CLKD of the VDD level a predetermined delay amount and outputs a delayed clock signal to the clock multiplexer 170. The delay circuit 150 includes a plurality of delay units forming a delay chain and a shift register for controlling the plurality of delay units. Each delay unit includes a NAND gate and an inverter. The clock multiplexer 170 outputs the delayed clock signal OUTPUT DLL_CLK to an external circuit and to the second clock divider 190. The second clock divider 190 divides the delayed clock signal from the clock multiplexer 170 by n, wherein n is a positive integer (e.g., n is 4). The delay model 210 is configured so that a feedback signal has an identical delay condition as the real clock signal path.

[0008] The phase comparator 230 compares the phase of the internal feedback signal outputted from the delay model 210 with the phase of the reference clock signal REF. The delay controller 250 outputs shift control signals SR and SL for controlling a shift direction of the shift register in the delayed circuit 150 and a delay locking signal representing that delay locking is achieved in response to control signals EARLY and LATE outputted from the phase comparator 230.

[0009] The delay model 210, also called a replica circuit, includes a dummy clock buffer, a dummy output buffer, and a dummy load. A delay time of the delay model 210 is generated that is identical to a delay time generated in the real clock signal path. Because of the delay circuit 150, the delay controller 250, and the phase comparator 230 delay the external clock signal CLK a desired delay amount, they are called a delay unit.

[0010] Because the delay model 210 includes a dummy clock buffer, a dummy output buffer and a dummy load, a delay time of the clock signal generated from the delay model 210 can be compensated. At this time, since the external clock signal is not synchronized with the internal clock signal, the delay operation for synchronizing the external clock signal with the internal clock signal is repeated in the delay circuit 150. Since the delay amount of the delay model 210 cannot be changed to achieve locking, the total delay amount has to be adjusted in the delay circuit 150. A condition for achieving locking is as follows:

[0011] DD+RR=nT  (Eq. 1)

[0012] Where, DD is a delay amount of the delay circuit 150, RR is a delay amount of the delay model 210, T is a period of the external clock signal, and n is an integer, e.g., 1 or 2.

[0013] DD=nT−RR  (Eq. 2)

[0014] Accordingly, an output DLL clock signal OUTPUT_DLL_CLK is provided by repeatedly delaying the high frequency clock signal CLKD by as much as DD, which is the delay amount that is repeatedly adjusted in the delay circuit 150. Additionally, a negative delay that precedes the external clock signal by as much as RR may be achieved in the DLL circuit.

[0015] FIG. 2A is a timing diagram illustrating one period (1T) based dividing of a clock signal capable of being used in a low frequency band. FIG. 2B is a timing diagram illustrating two periods (2T) based dividing of a clock signal capable of being used in a high frequency band.

[0016] Referring to FIG. 2A, since a rising edge of the feedback clock signal, which is compared to the reference clock signal REF in the phase comparator 230 in the low frequency band, is before the rising edge of the reference clock signal REF, locking can be achieved by repeatedly increasing the delay amount in the delay circuit 150. In this case, because the pulse width of the divided reference clock signal REF corresponds to one period of the external clock signal CLK, it is called one-period-based dividing or 1T-based dividing.

[0017] Referring to FIG. 2B, since a rising edge of the feedback clock signal, which is compared to the reference clock signal REF in the phase comparator 230 in the high frequency band, is before the rising edge of the reference clock signal REF, locking can be achieved by repeatedly increasing the delay amount in the delay circuit 150. Accordingly, because the pulse width of the divided reference clock signal REF corresponds to two periods of the external clock signal CLK, locking can be achieved. Additionally, because the pulse width of the divided reference clock signal REF corresponds to two periods of the external clock signal CLK, it is called two-periods-based dividing or 2T-based dividing.

[0018] FIG. 3A is a circuit diagram illustrating a conventional four-dividing circuit for one-period-based dividing of a clock signal in which the pulse width of the divided reference clock signal REF is not adjustable. The four-dividing circuit may be located in the clock dividers, e.g. the the first clock divider 130 and the second clock divider 190, according to the prior art. FIG. 3B is a timing diagram showing the operation of the conventional four-dividing circuit of FIG. 3A.

[0019] If the clock signal CLKD from the clock buffer 110 is provided as an input to the first dividing unit 310 in response to a DLL enable signal DLL_ENABLE, the clock signal CLKD is divided by two and a two-divided clock signal DIVIDE_2 is outputted. Thereafter, if the two-divided clock signal DIVIDE_2 is provided as an input to a second dividing unit 330, the two-divided clock signal is divided again by two and a four-divided clock signal DIVIDE_4 is outputted. The four-divided clock signal is maintained in a high state for one period of the externally supplied clock signal CLKD and then is maintained in a low state.

[0020] FIG. 4A is a circuit diagram illustrating a conventional four-dividing circuit for one-period-based dividing in which the pulse width of the divided reference clock signal REF is adjustable. The four-dividing circuit may be located in the clock dividers, e.g., the first clock divider 130 and the second clock divider 190, according to the prior art. FIG. 4B is a timing diagram showing the operation of the conventional four-dividing circuit of FIG. 4A.

[0021] If the clock signal CLKD from the clock buffer 110 is provided as an input to a third dividing unit 410 in response to a DLL enable signal DLL_ENABLE, the clock signal CLKD is divided by two and a two-divided clock signal DIVIDE_2 is outputted. Thereafter, if the two-divided clock signal DIVIDE_2 is provided as an input to a fourth dividing unit 430, the two-divided clock signal DIVIDE_2 is divided by 2 and a four-divided clock signal is outputted. The four-divided clock signal DIVIDE_4 of the fourth dividing unit 430 is maintained in a high state for two periods of the externally supplied clock signal CLKD and then is maintained in a low state.

[0022] As shown in the timing diagrams in FIGS. 3B and 4B, the pulse width of the divided reference clock signal REF can be changed based on the frequency bands.

[0023] Currently, when the externally supplied input clock signal is a high frequency signal, the two-periods-based dividing is carried out to secure correct operation in the high frequency band. Even if two-periods-based dividing results in good performance in the high frequency band, noise may be generated in the low frequency band. As a result, malfunctions of the semiconductor memory device may frequently occur in the low frequency band.

[0024] Additionally, when one-period-based dividing is carried out to reduce noise, it is difficult for operating frequencies to become greater than 100 MHz to 133 MHz. Moreover, the size of the semiconductor memory device is increased due to the numerous delay circuits.

[0025] A clock divider capable of reducing jitter due to noise associated with an external power supply voltage and that reduces the size of the DLL circuit is disclosed. Additionally, a method for dividing a clock signal in a DLL circuit of a semiconductor memory device is also disclosed.

[0026] A clock divider in a DLL circuit for generating an internal clock signal synchronized with an external clock signal in a semiconductor memory device includes: a first clock dividing circuit for generating a first clock signal by dividing an input clock signal having a same period as a period of the external clock signal; a second clock dividing circuit for generating both a second clock signal and a third clock signal by dividing the first clock signal from the first clock dividing circuit; a selection signal generation circuit for generating a selection signal in response to a plurality of control signals; and a clock signal selection circuit for selectively outputting the second clock signal or the third clock signal in response to the selection signal; wherein one period of the first clock signal corresponds to two periods of the input clock signal; and

[0027] wherein the second clock signal is a one-period-based dividing clock signal in which one period of the one-period-based dividing clock signal corresponds to four periods of the input clock signal, the one-period-based dividing clock signal being maintained in a first logic state for one period of the input clock signal and being maintained in a second logic state for three periods of the input clock signal.

[0028] A method for dividing an input clock signal of a DLL circuit in a semiconductor memory device is disclosed, the DLL circuit being used to generate an internal clock signal synchronized with an external clock signal. The method includes: generating a first clock signal by dividing the input clock signal, which has a same period as a period of the external clock signal; generating both a second clock signal and a third clock signal by dividing the first clock signal; generating a selection signal by receiving: a long locking signal that is generated when a high frequency clock signal is provided as an input to the DLL circuit, a DLL enable signal that is generated when the DLL circuit is enabled, and a dividing clock selection enable signal that is in a logic high state for an initial four cycles after the DLL circuit is turned on; and selectively outputting the second clock signal associated with the high frequency clock signal or outputting the third clock signal associated with a low frequency clock signal in response to the selection signal.

[0029] The above and other features of the disclosed clock divider and method will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, wherein:

[0030] FIG. 1 is a block diagram illustrating a conventional register-control-type DLL circuit of a typical DDR SDRAM;

[0031] FIG. 2A is a timing diagram illustrating one period (1T) based dividing of a clock signal capable of being used in a low frequency band;

[0032] FIG. 2B is a timing diagram illustrating two periods (2T) based dividing of a clock signal capable of being used in a high frequency band;

[0033] FIG. 3A is a circuit diagram illustrating a conventional four-dividing circuit for one-period-based dividing of a clock signal;

[0034] FIG. 3B is a timing diagram showing the operation of the conventional four-dividing circuit of FIG. 3A;

[0035] FIG. 4A is a circuit diagram illustrating another conventional four-dividing circuit for one-period-based dividing of a clock signal;

[0036] FIG. 4B is a timing diagram showing the operation of the conventional four-dividing circuit of FIG. 4A;

[0037] FIG. 5 is a block diagram illustrating a four-dividing clock divider capable of adjusting the pulse width of a clock signal;

[0038] FIG. 6A is a circuit diagram illustrating a four-dividing clock divider capable of adjusting the pulse width of a clock signal;

[0039] FIG. 6B is a timing diagram illustrating the operation of the four-dividing clock divider of FIG. 6A;

[0040] FIG. 7 is a circuit diagram illustrating the selection signal generator of FIG. 5;

[0041] FIG. 8 is a timing diagram showing the operation of the four-dividing clock divider for a high frequency operation; and

[0042] FIG. 9 is a timing diagram showing the operation of the four-dividing clock divider for a low frequency operation.

[0043] A clock divider of a DLL circuit, which is capable of adjusting the pulse width of a clock signal, will be described in detail referring to the accompanying drawings.

[0044] FIG. 5 is a block diagram illustrating a four-dividing clock divider capable of adjusting the pulse width of a clock signal.

[0045] The four-dividing clock divider includes a first clock divider 510, a second clock divider 530, a selection signal generator 550, and a clock selector 570. The first clock divider 510 is a two-dividing circuit and generates a first clock signal by receiving an input clock signal CLKD having an identical period with a period of an external clock signal. The first clock signal is a divided clock signal that is generated by the first clock divider 510 by dividing the input clock signal CLKD by 2. The second clock divider 530 generates a 1T-based dividing clock signal and a 2T-based dividing clock signal. The selection signal generator 550 generates a selection signal for selecting one of the 1T-based dividing clock signal and the 2T-based dividing clock signal. The clock selector 570 outputs one of the 1T-based dividing clock signal and the 2T-based dividing clock signal in response to the selection signal.

[0046] It should be understood that the four-dividing clock divider can be applied to the first clock divider 130 and the second clock 190 of FIG. 1. An example in which the four-dividing clock divider is applied to the first clock divider 510 of FIG. 5 will be described.

[0047] The first clock divider 510 receives the input clock signal CLKD having an identical period as a period of the external clock signal and generates a two-divided clock signal. The two-divided clock signal is maintained in a first logic state for one period of the input clock signal CLKD and is maintained in a second logic state for one period of the input clock signal CLKD.

[0048] The second clock divider 530 receives the two-divided clock signal and generates the 1T-based dividing clock signal and the 2T-based dividing clock signal. The 1T-based dividing clock signal is maintained in a first logic state for one period of the input clock signal CLKD and is maintained in a second logic state for three periods of the input clock signal CLKD. The 2T-based dividing clock signal is maintained in a first logic state for two periods of the input clock signal CLKD and is maintained in a second logic state for two periods of the input clock signal CLKD.

[0049] The selection signal generator 550 receives a long locking signal LONG_LOCK, a DLL enable signal DLL_ENABLE and a dividing clock selection enable signal TCK_SET ENABLE, and generates the selection signal for selecting one of the 1T-based dividing clock signal and the 2T-based dividing clock signal according to the frequency of the external clock signal. The clock selector 570 selectively outputs one of the 1T-based dividing clock signal and the 2T-based dividing clock signal in response to the selection signal.

[0050] FIG. 6A is a circuit diagram illustrating a four-dividing clock divider capable of adjusting the pulse width of a clock signal in accordance with a preferred embodiment.

[0051] The first clock divider 510 receives the input clock signal CLKD and the DLL enable signal DLL_ENABLE and outputs the two-divided clock signal DIVIDE_2. The second clock divider 530 receives the two-divided clock signal DIVIDE_2 and generates the 1T-based dividing clock signal and the 2T-based dividing clock signal, both of which correspond to the four-divided clock signal. The 1T-based dividing clock signal or the 2T-based dividing clock signal generated from the second clock divider 530 is selectively outputted through the clock selector 570 in response to the selection signal TCK_CTRL generated from the selection signal generator 550. of FIG. 5.

[0052] FIG 6B is a timing diagram illustrating the operation of the four-dividing clock divider of FIG. 6A.

[0053] When the selection signal TCK_CTRL is maintained in a logic high state, the 1T-based dividing clock signal is outputted and when the selection signal TCK_CTRL is maintained in a logic low state; the 2T-based dividing clock signal is outputted.

[0054] FIG. 7 is a circuit diagram illustrating the selection signal generator 550 of FIG. 5.

[0055] As illustrated in FIG. 7, the selection signal generator 550 receives the long locking signal LONG_LOCK, the DLL enable signal DLL_ENABLE and the dividing clock selection enable signal TCK_SET ENABLE, and generates the selection signal TCK_CTRL. The long locking signal LONG_LOCK is a deactivated signal that is outputted from the phase comparator 230 of FIG. 1 when the delay amount DD+RR of Eq. 1 becomes greater than one period of the external clock signal. The DLL enable signal DLL_ENABLE is generated when the DLL circuit is enabled. The dividing clock selection enable signal TCK_SET ENABLE is maintained in a logic high state for the initial four cycles after the DLL circuit is turned on. Because the dividing clock selection enable signal TCK_SET ENABLE may be easily generated by using a D flip/flop and a latch located inside or outside of the DLL circuit, a circuit for generating the dividing clock selection enable signal TCK_SET ENABLE is not described.

[0056] When the dividing clock selection enable signal TCK_SET ENABLE is in a logic high state, the selection signal generator 550 determines whether the selection signal TCK_CTRL is in a logic high state or in a logic low state.

[0057] Since the delay amount DD+RR of Eq. 1 is greater than one period of the external clock signal in a high frequency band, the long locking signal LONG_LOCK is generated by the phase comparator 230 of FIG. 1. If the long locking signal LONG_LOCK is enabled in a logic low state, the output NET2 of a first NAND gate ND1 becomes a logic high state. Since the dividing clock selection enable signal TCK_SET ENABLE becomes a logic high state for initial four cycles after the DLL circuit is turned on, the output NET4 of a third NAND gate ND3 becomes a logic low state. Since the DLL enable signal DLL_ENABLE and the dividing clock selection enable signal TCK_SET ENABLE are in a logic high state, the output NET3 of a second NAND gate ND2 becomes a logic low state and the output NET5 of a fourth NAND gate ND4 becomes a logic high state. Since the output of a fifth NAND gate ND5 becomes a logic high state by receiving the output NET4 in a logic low state, the output of a sixth NAND gate ND6 becomes a logic low state. Therefore, the selection signal TCK_CTRL is generated in a logic low state through inverters INV1 and INV2.

[0058] Since the delay amount DD+RR of Eq. 1 is less than one period of the external clock signal in a low frequency band, the long locking signal LONG_LOCK is not generated by the phase comparator 230 of FIG. 1. If the long locking signal LONG_LOCK is disabled with in a logic high state, the output NET2 of the first NAND gate ND1 becomes a logic low state. Since the dividing clock selection enable signal TCK_SET ENABLE becomes a logic high state for an initial four cycles after the DLL circuit is turned on, the output NET4 of the third NAND gate ND3 becomes a logic high state. Since the DLL enable signal DLL_ENABLE and the dividing clock selection enable signal TCK_SET ENABLE are in a logic high state, the output NET3 of the second NAND gate ND2 becomes a logic high state, and the output NET5 of the fourth NAND gate ND4 becomes a low state. Since the output of the sixth NAND gate ND6 becomes a logic high state by receiving the output NET5 in a logic low state, the selection signal TCK_CTRL is generated in a logic high state through inverters INV1 and INV2.

[0059] FIGS. 8 and 9 are timing diagrams showing the operation of the four-dividing clock divider.

[0060] FIG. 8 is a timing diagram showing the operation of the four-dividing clock divider for a high frequency operation, and FIG. 9 is a timing diagram showing the operation of the four-dividing clock divider for a low frequency operation.

[0061] As shown in FIG. 8, the selection signal TCK_CTRL is transitioned from a logic high state to a logic low state when the long locking signal LONG_LOCK is generated in the high frequency band.

[0062] As shown in FIG. 9, the selection signal TCK_CTRL is maintained in a logic high state since the long locking signal LONG_LOCK is not generated in the low frequency band.

[0063] In FIGS. 8 and 9, the reference signal is an inverted output signal selectively outputted as the 1T-based dividing clock signal or the 2T-based dividing clock signal from the clock selector 570 in response to the selection signal TCK_CTRL.

[0064] Accordingly, since the four-dividing clock divider can be applied over a wide frequency band, the size of the DLL circuit can be reduced. Also, since the four-dividing clock divider is strong for a noise of the external power supply voltage, jitter is reduced by ⅓.

[0065] While the disclosed clock divider and method of dividing a clock signal in a DLL circuit have been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of this disclosure, which is limited only by the following claims.