High-efficiency mixed voltage/current mode output driver

[0002] The present invention relates to circuitry for drivers for digital outputs.

[0003] The digital revolution has produced a need for analog circuitry that can be used for digital purposes, especially in the fields of telecommunications and networking.

[0004] Modern applications in the above fields require high efficiency driver circuitry that can drive both receiver and transmitter end terminations in a networked data communications link. Such an application requires an output voltage swing with a controllable amplitude along with high efficiency. Driver efficiency is dependent on the amount of drive current required to drive a given output voltage swing. Controllability is quantified by the ability to control dynamically the output voltage swing. Such controllability must also allow for the use of pre-emphasis and the use of variable output levels.

[0005] A number of solutions have been presented in the past that sought to provide the desired controllability and efficiency. Three architectures predominate in these solutions

[0006] a single differential pair (Class A output driver),

[0007] a class AB driver commonly used with LVDs (Low Voltage Differential Signalling) output drivers, and

[0008] a series terminated voltage mode driver.

[0009] The class A output driver consists of a CMOS current source I drive connected to a differential pair of transistors that are, in turn, connected to the output resistors. The resistors act as parallel termination to the transmission line. The differential pair switches the current between the resistors depending on whether a logic 1 or a logic 0 is required to be driven on the transmission line. A schematic diagram of a class A single differential pair output driver circuit is illustrated in FIG. 1.

[0010] While the class A output driver is very simple and easy to implement, it is not very efficient. For 50 Ohm drivers (as in FIG. 1), this driver requires that Idrive=4×Vswing/100 to generate a differential output voltage swing of Vswing. This value for Idrive is 4 times the ideal current drive. The output voltage swing is controllable by adjusting the amount of current (Idrive) in the tail of the differential pair. The voltage Vswing is also controllable by putting many of these types of drivers in parallel to generate a larger swing.

[0011] A second known architecture is discussed below, and utilizes a class AB driver illustrated in FIG. 2. This circuit consists of two CMOS differential pairs of transistors. The top differential pair switches a PMOS current source and the bottom differential pair switches an NMOS current source. The outputs of these differential pairs are connected to a 100 Ohm differential termination resistor.

[0012] The circuit in FIG. 2 requires that Idrive (2×Vswing)/100 to generate a differential output voltage swing of Vswing. The output voltage swing is controllable by adjusting the amount of current in the tail of the current sources of the differential pairs. The swing can also be controlled by placing multiple instances of this circuit in parallel. This circuit has a very controllable output swing but it is not very efficient.

[0013] A third known architecture is that illustrated in FIG. 3. This circuit is a class AB voltage mode series terminated output driver implemented as a CMOS inverter drive with series termination. As can be seen, the circuit consists of two inverter circuits connected by a resistor divider circuit. An input signal and its complement are fed to the driver and, depending on the input, the inverters route current one way or the other. The inverters will always act in opposite directions and the direction of the current through the middle resistor in the resistor divider circuit determines whether the output is a logic 1 or a logic 0.

[0014] This third architecture, if designed properly, only requires that Idrive=Vswing/100 to drive an output voltage of Vswing. Unfortunately, the output swing is not adjustable and is completely dependent on the ratio of the resistor divider and the supply voltage level. Since the supply level and the resistor divider ratio are not easily dynamically controllable, the output voltage swing is not easily dynamically controllable.

[0015] From the above, the issues with the three architectures are clear—the single differential pair architecture and the class AB driver (FIGS. 1 and 2) both have controllable output voltage swing levels but are not very efficient. While the voltage mode driver has the desired efficiency, it does not have an easily controllable output voltage swing. What is therefore required is a driver that has the controllability of the first two designs and the efficiencies of the voltage mode driver.

[0016] The present invention provides circuits and devices for an efficient, controllable output driver. The output driver circuit includes a series terminated voltage mode driver circuit in parallel with a current mode driver circuit. This output driver allows for a highly efficient driver but with an easily controllable output. It can be used for driving single ended or differentially doubly terminated transmission lines. The efficiency is in the reduced amount of current drawn from the supply for a given output swing across a doubly terminated transmission line. The driver is capable of pre-emphasis and dynamically controllable output swings.

[0017] In a first aspect the present invention provides a driver circuit including:

[0018] an input,

[0019] a voltage mode driver circuit connected in parallel with a current mode driver circuit, between a voltage source and ground,

[0020] the outputs of said voltage and current mode drivers being connected in parallel and to a transmission line.

[0021] In a second aspect the present invention provides a driver circuit comprising:

[0022] a pair of inputs comprising a first input and a second input;

[0023] a series terminated voltage mode driver sub-circuit;

[0024] at least one current mode driver sub-circuit;

[0025] a pair of outputs comprising a first output and a second output, wherein

[0026] each of the sub-circuits is coupled in parallel to each one of the pair of outputs;

[0027] at least two of the sub-circuits are coupled in parallel to each one of the pair of inputs.

[0028] A better understanding of the invention may be obtained by reading the detailed description of the invention below, in conjunction with the following drawings, in which:

[0029] FIG. 1 is a schematic diagram of a class A single differential pair output driver circuit according to the prior art;

[0030] FIG. 2 is a schematic diagram of a class AB differential output driver circuit according to the prior art;

[0031] FIG. 3 is a schematic diagram of a voltage mode driver according to the prior art;

[0032] FIG. 4 is a schematic diagram of a mixed voltage/current mode output driver circuit according to one embodiment of the invention;

[0033] FIG. 5 is a schematic diagram of a simplified equivalent circuit when the circuit of FIG. 4 outputs a logic 1;

[0034] FIG. 6 is a single ended implementation of a voltage/current mode driver circuit;

[0035] FIG. 7 is a schematic diagram of an ideal single ended driver in which the transistors are replaced by symbolic switches;

[0036] FIG. 8 is an idealized schematic similar to FIG. 7 using many current mode sources in parallel; and

[0037] FIG. 9 is a schematic diagram of an alternative embodiment to the circuit in FIG. 4 using a pre-emphasis sub-circuit.

[0038] Referring to FIG. 4, a schematic diagram of a mixed voltage/current mode output driver according to one embodiment of the invention is presented. The driver 10 consists of a first sub-circuit 20 coupled in parallel with a second sub-circuit 30. A pair of differential inputs (SP,SN) are coupled in parallel to both of the sub-circuits 20 and 30. Similarly, a pair of differential outputs (OUTP, OUTN) are coupled in parallel to both of the sub-circuits 20 and 30.

[0039] The first sub-circuit 20 is a series terminated voltage mode driver circuit consisting of a pair of inverters 50 and 60 with a resistor divider circuit 70 consisting of resistors R0, R1, and R2 coupled between the inverters 50 and 60. Each of the pair of inputs SP and SN is coupled to a different inverter. Thus, the input SP is coupled to inverter 60 and input SN is coupled to inverter 50.

[0040] Each of the inverters 50 and 60 consists of a pair of transistors—a PMOS transistor (M0, M1) 75 and an nMOS transistor (M2, M3) 77. The inverters are arranged with the drain leads of both transistors coupled to a common output node 80. The source leads of the pMOS transistors 75 are connected to a voltage source (VDD) while the source leads of the nMOS transistors 77 are connected to ground.

[0041] Regarding the resistor divider circuit, three resistors R0, R1, R2, are connected in series between the respective common output nodes 80 of the two inverters 50, 60. Of the pair of outputs OUTN, OUTP, one (OUTN) is tapped from the junction node of resistors R0 and R1 while the other (OUTP) is tapped from the Junction node of resistors R1 and R2.

[0042] It should be noted that the input SP is coupled to an input node 90, and input SN is coupled to a common input node 91.

[0043] The second sub-circuit 30 is a current mode driver circuit, preferably of the class AB type. As can be seen, the sub-circuit 30 consists of two current sources, 100A, 100B, along with two pairs of transistors 110 and 120. Each pair consists of a pMOS transistor (M4, M5) and an nMOS transistor (M6, M7). For each pair of transistors 110, 120, the source lead of the pMOS transistors M4 and M5 are coupled to the current source 100A, the drain leads are coupled to output nodes 130 and the gate leads are coupled to an input node 140. For each of the nMOS transistors M6 and M7, the source lead is coupled to the current source 100B, the drain leads are coupled to the output nodes 130, and the gate leads are coupled to the Input nodes 140. As can be seen in FIG. 4, for each pMOS transistor that has a gate lead coupled to an input, the nMOS transistor that has its gate lead coupled to the same input must also have its drain lead coupled to the same output as the drain output of the pMOS transistor.

[0044] It should be noted that each of the inputs SP and SN is coupled to one of the input nodes 140. Also, each of the output nodes 130 is coupled to one the outputs OUTN and OUTP. It should also be noted that the two inputs SP, SN are complements of one another and that the outputs OUTN, OUTP are also complements of one another. The logical output of output OUTP mirrors the logical input of input SP. Also, the logical output of output OUTN mirrors the logical input of input SN.

[0045] The inputs SP, SN are rail-to-rail CMOS inputs such that a logic 1 is denoted as the difference between output node voltages (OUTP-OUTN) is positive, and a logic 0 is derived as when the difference output node voltages (OUTP-OUTN) is negative such that current sources 100A, 100B are compatible with the transistors. That is, the current source 100A is a pMOS current source and the current source 100B is an nMOS current source.

[0046] Ideally, the two pMOS transistors (M4, M5) in the second sub-circuit 30 are a differential pair and the two nMOS transistors M6, M7 in the same sub-circuit 30 are also a differential pair.

[0047] In order to output a logic 1 in the output OUTP, the input signal SP must be high (logic 1) and input SN must be low (logic 0). When this is the input, transistors M0, M3, M4, and M7 are off and transistors M1, M2, M5 and M6 are on. The resulting circuit is illustrated in FIG. 5.

[0048] In order to calculate the current transfer of the output driver, the external receiver end termination resistor (REXT) in FIG. 5 must be accounted for. For standard 50-Ohm transmission lines this impedance is 100 ohms. In order to have transmitter end termination for a 50-Ohm transmission line the input impedance of the driver need only be 50 ohms. This means that the combination input impedance through the resistor network of R0, R1 and R2 looks like 50 ohms from the outside. However, ideal current efficiency occurs when R1 is sufficiently large and R0 and R2 are 50 ohms. The resistance R1 can be set large enough such that it had an insignificant impact on the output swing. The output swing can be calculated as: $\begin{array}{cc}{V}_{\mathrm{swing}}=\mathrm{OUTP}-\mathrm{OUTN}=\frac{\mathrm{VDD}*\mathrm{REXT}}{\mathrm{R2}+\mathrm{R0}+\mathrm{REXT}}+\mathrm{I1}*\mathrm{REXT}& \left(1\right)\end{array}$

[0049] Since REXT=Zo=(R2+R0)|R1 and, for this example, R1 is sufficiently large, the equation (1) becomes; $\begin{array}{cc}{V}_{\mathrm{swing}}=\mathrm{OUTP}-\mathrm{OUTN}=\frac{\mathrm{VDD}}{2}+\mathrm{I1}*\mathrm{REXT}& \left(2\right)\end{array}$

[0050] To measure current efficiency, this can be seen as the ratio between the amount of current that is drawn from the supply and the amount of current dissipated across the resistive load REXT. A ratio of 1 denotes 100% efficiency. Since it is obvious from FIG. 5 that if R1 is significantly large all the current flows through the receiver end termination resistor REXT, this driver is 100% efficient.

[0051] In order to output a logic “0” the input signal SP must be low and the input signal SN must be high, in this condition, transistors M0, M3, M4, and M7 are turned on and transistors M1, M2, M5, and M6 are turned off. Using a similar method as with a logic “1” it is easy to show that the output swing is: $\begin{array}{cc}{V}_{\mathrm{swing}}=\mathrm{OUTP}-\mathrm{OUTN}=\frac{-\mathrm{VDD}}{2}-\mathrm{I1}*\mathrm{REXT}& \left(3\right)\end{array}$

[0052] The driver of FIG. 4 may also be used in single ended situations as shown in FIG. 6 where an inverter consisting of NMOS transistor M0 and PMOS transistor M2 form a differential pair output driver with its output in parallel with a current mode driver formed of CMOS transistors M4 and M6, which are connected to current sources 100A and 100B. In a single ended application, a series terminated voltage driver can be used in parallel with a current drive source to generate an output swing of controllable amplitude for doubly terminated transmission lines.

[0053] FIG. 6 illustrates such a single ended driver, where a series terminated voltage drive M0, M2 is connected in parallel with a current mode driver at point 150 which is connected to a 50 ohm termination resistor which in turn is connected to a voltage source VDD/2. An idealized equivalent circuit is shown in FIG. 7, where transistor pairs are replaced with equivalent switches SW1, SW2 SW3. A further abstraction of the single ended application is shown in FIG. 8, in which plural current sources 100A and 100B are connected to further current mode drivers in parallel. There may be many current mode drivers and many voltage mode drivers with the inputs different signals. The voltage mode driver need not have the same input as the current mode driver in the general case.

[0054] In FIGS. 6, 7 and 8 for full efficiency, INV1 should be the same as INC1, however they do not have to be the same signal. Some applications could require that those signals be different.

[0055] The mixed voltage/current mode driver may contain multiple voltage mode drivers and multiple current mode driver stages. These can be controlled separately or together. One example of such a set-up is to use a pre-emphasis driver. A separate LVDS type driver can be used to drive the voltage level on the output higher for the transition period of the output signal.

[0056] FIG. 9 illustrates such an implementation. The circuit in FIG. 9 is similar to that illustrated in FIG. 4 except that an extra LVDS type driver sub-circuit 150 is coupled in parallel with the two previous sub-circuits. This third sub-circuit 150 is coupled in parallel to the two outputs OUTN and OUTP. A pair of pre-emphasis inputs PREP and PREN are fed into the third subcircuit 150. The arrangement of the third sub circuit 150 is identical to the arrangement of the second sub-circuit 30 in FIG. 4 except that the inputs to the third sub-circuit 150 are provided by the pre-emphasis inputs PREN and PREP and not by the regular inputs SP and SN. Other extra subcircuits may be coupled to either of the arrangements in FIGS. 4 and 9 to provide different performance characteristics.

[0057] As can be seen in FIG. 9, two pairs of pre-emphasis transistors M8 and M10, M9 and M11 are provided along with two pre-emphasis current sources 100C, 100D. Each pair of pre-emphasis transistors consists of a pMOS transistor M8, M9 and of nMOS transistors M10, M11. For each pair of transistors the gate leads of one pMOS transistor and of one nMOS transistor are coupled to a pre-emphasis input. Similarly, for each pair of transistors the drain leads of one pMOS transistor and of one nMOS transistor are coupled to one of the outputs OUTP and OUTN. The source lead of each transistor is coupled to one of the other of the pre-emphasis current sources. It should be noted that if a pMOS transistor and an nMOS transistor have their gate leads coupled to the same pre-emphasis input, these two transistors should have their drain leads coupled to the same output.