US 6,800,563 B2Grant
Forming tapered lower electrode phase-change memories
Issue Date:2004-10-05
•10 Claims
•5 Drawing Sheets
Abstract
A phase-change memory may have a tapered lower electrode coated with an insulator. The coated, tapered electrode acts as a mask for a self-aligned trench etch to electrically separate adjacent wordlines. In some embodiments, the tapered lower electrode may be formed over a plurality of doped regions, and isotropic etching may be used to taper the electrode as well as part of the underlying doped regions.
Metadata
Assignee
- Ovonyx, Inc.
Inventor
- Daniel Xu
Application Information
Application Number:US 09/975,163
Filing Date:2001-10-11
Priority Date:2001-10-11
Art Unit:7
Classifications
IPC:
H01L 21302
Field of Search:
438978438FOR 458438FOR 439438FOR 212438689438718438719438 2438 29438 32438 95438128438130438164438237438238438197438240438900257 4257E21574257E21591257E21592
Patent Drawings (5 sheets)
Description
Background
[0002] This invention relates generally to memories that use phase-change materials.
[0003] Phase-change materials may exhibit at least two different states. The states may be called the amorphous and crystalline states. Transitions between these states may be selectively initiated. The states may be distinguished because the amorphous state generally exhibits higher resistivity than the crystalline state. The amorphous state involves a more disordered atomic structure and the crystalline state involves a more ordered atomic structure. Generally, any phase-change material may be utilized; however, in some embodiments, thin-film chalcogenide alloy materials may be particularly suitable.
[0004] The phase-change may be induced reversibly. Therefore, the memory may change from the amorphous to the crystalline state and may revert back to the amorphous state thereafter or vice versa. In effect, each memory cell may be thought of as a programmable resistor, which reversibly changes between higher and lower resistance states in response to temperature changes. The temperature changes may be induced by resistive heating.
[0005] In some situations, the cell may have a large number of states. That is, because each state may be distinguished by its resistance, a number of resistance-determined states may be possible, allowing the storage of multiple bits of data in a single cell.
[0006] A variety of phase-change alloys are known. Generally, chalcogenide alloys contain one or more elements from column VI of the periodic table. One particularly suitable group of alloys are GeSbTe alloys.
[0007] In any memory, it is desirable to pack the individual memory cells as closely as possible. With conventional phase-change memory materials, there is no real way to self-align the trenches that separate adjacent rows of memory cells from one another. Therefore, critical alignment processing may be necessary to accurately space one wordline from the next. Moreover, extra real estate may be needed between adjacent wordlines to make up for any misalignment between the trenches and the adjacent memory cells.
[0008] Thus, there is a need for better ways to form trenches for phase-change memories.
Brief Description of the Drawings
[0009] FIG. 1 is an enlarged cross-sectional view in accordance with one embodiment of the present invention;
[0010] FIG. 2 is an enlarged cross-sectional view of the structure described in FIG. 1 at an early stage fabrication, in accordance with one embodiment of the present invention;
[0011] FIG. 3 is a cross-sectional view of the embodiment depicted in FIG. 2 after subsequent processing;
[0012] FIG. 4 is a cross-sectional view of the embodiment depicted in FIG. 3 after further processing;
[0013] FIG. 5 shows subsequent processing on the structure shown in FIG. 4 in accordance with one embodiment of the present invention;
[0014] FIG. 6 shows subsequent processing on the structure shown in FIG. 5, in accordance with one embodiment of the present invention;
[0015] FIG. 7 shows subsequent processing on the structure shown in FIG. 6 in accordance with one embodiment of the present invention;
[0016] FIG. 8 is an enlarged, cross-sectional view of the structure shown in FIG. 7 after additional processing in accordance with one embodiment of the present invention; and
[0017] FIG. 9 is a schematic depiction of a processor-based system in accordance with one embodiment of the present invention.
Detailed Description
[0018] Referring to FIG. 1, in one embodiment of the invention, a memory cell 10 may include a suitable phase change material 32 disposed between a tapered lower electrode 22 and an upper electrode 31. One suitable type of phase change material may be an alloy that includes at least one chalcogen element, and a transition element among others. Examples of such alloys are alloys of Germanium, Antimony and Tellerium.
[0019] The lower electrode 22 may be formed over a substrate 12. The substrate 12 may include a lower substrate portion 12aof a first conductivity type that, in one embodiment of the present invention, may be a P− material. A conical substrate portion 12bmay extend upwardly from the lower portion 12ato the lower electrode 22. The conical substrate portion 12bmay include a plurality of layers 14-20.
[0020] In one embodiment, the layers 14, 16, and 18 may be of a second conductivity type opposite to the first conductivity type. For example, the layer 14 may be an N− layer, the layer 16 may be an N+ layer, and the layer 18 may be an N− layer, in accordance with one embodiment of the present invention. Together the layers 14, 16, and 18 may form a buried wordline, in one embodiment of the present invention.
[0021] Over the layers 14, 16, and 18, may be a layer 20 of the first conductivity type, which, in one embodiment of the present invention, may be a P+ layer. The juxtaposition of the layers 14, 16, and 18 of a second conductivity type below the layer 20 of a first conductivity type may form a diode.
[0022] The tapered shape of the lower electrode 22 reduces the contact area between the electrode 22 and the phase-change material 32. This increases the resistance at the point of contact, increasing the ability of the electrode 22 to heat the layer 32. In some embodiments, the lower electrode 22 may be made of cobalt silicide and may be covered by interfacial layers.
[0023] The conical substrate portion 12bmay be covered with a suitable dielectric 30 such as silicon dioxide. Further, each wordline may be electrically isolated from two adjacent wordlines by trenches 33 that may be filled with insulator 34 such as silicon dioxide.
[0024] The sidewalls of the conical substrate portion 12bmay be covered with dielectric layers 26 and 28. In some embodiments the layer 26 may be silicon dioxide and the layer 28 may be silicon nitride. The layers 26 and 28 may aid in the formation of the trenches 33.
[0025] The upper electrode 31 may be made of any suitable electrical conductor. In some embodiments the electrode 31 may be covered by barrier or adhesion layers.
[0026] Turning next to FIG. 2, the formation of the memory cell 10 may begin with the formation of the layers 14-20. The substrate 12 may be subjected to a sequence of ion implantation steps. The energy, dose, and angle of ion beams of a series of implants may be selected to achieve the doping profile of the layers 14, 16, 18 and 20 shown in FIG. 2.
[0027] While the exact nature of the ion implantation steps may be subject to considerable variation, an initial implantation may be utilized to form a P-type well. This may be followed by P type and N type implants to form the layers 14-20. These implants in turn may be followed by one or more additional implants, in some embodiments, to create the profiles indicated in FIG. 2. In some embodiments, P type regions may be formed by a boron implant and N type regions may be formed by a phosphorus implant.
[0028] The same implantation process may simultaneously be used to define structures in a large number of surrounding memory cells (not shown) also formed in the substrate 10. This implantation process may be done in a blanket fashion without masking between cells, in some embodiments.
[0029] The lower electrode 22 may be deposited over the region 20 as depicted in FIG. 3. A mask 24, which may be made of photoresist, may be patterned over each electrode 22 on the substrate 12 to form circular patches, in some embodiments. The structure, shown in FIG. 3, may be isotropically etched. Mask and etch parameters are selected so that the vertical and lateral etch rates are sufficient to cut through layers 16, 18 and 20 and achieve a taper on the electrode 22. The deposition of the lower electrode 22 may also simultaneously form the lower electrodes 22 of a number of surrounding memory cells (not shown) without the need to mask off the electrodes 22 for each cell.
[0030] The substrate portion 12bis conically shaped as a result of the etching as shown in FIG. 4. The etched dimension of the lower electrode 22 may be smaller than that of the mask 24 due to undercutting. The isotropic etching also separates the electrodes 22 of each memory cell 10 from the electrodes 22 of surrounding cells. The mask 24 may be subsequently removed, for example by ashing, to expose the lower electrode 22.
[0031] In some embodiments, the size of the closed region of mask 24 may be the minimum feature size attainable. Other methods to reduce the area of the upper surface of the lower electrode 22 may include reactive means such as oxidation.
[0032] The conical substrate portion 12bmay be covered with dielectric layers 26 and 28 as shown in FIG. 5. A process such as low-pressure chemical vapor deposition (LPCVD) may be used to deposit each material. Again, the portions 12bof a large number of surrounding memory cells (not shown) may be covered in the same blanket deposition without masking between the cells.
[0033] Subsequently the dielectric layer 28 may be etched selectively with respect to the dielectric layer 26 by any anisotropic means such as reactive ion etching. The residual dielectric region 28 over the conical substrate portion 12bis removed from horizontal surfaces as a result of anisotropic etching as shown in FIG. 6.
[0034] Further, the conical substrate portion 12bmay be covered with an insulator 30, as shown in FIG. 7. This insulator 30 is chemically distinct from dielectric layer 28 and, in some embodiments, may be high-density plasma (HDP) oxide. Planarization of the insulator 30, for example, by chemical mechanical planarization (CMP) may expose (and perhaps flatten) the tip 27 of the lower electrode 22.
[0035] A pair of spaced trenches 33, electrically isolating a wordline of cells 10 from adjacent wordlines, may be etched through the insulator 30 on either side of the memory cell 10 using suitable patterning and etching methods. In particular, the etch parameters are selected to etch the insulator 30 selectively with respect to the dielectric region 28.
[0036] In regions of slight mask misalignment, the dielectric layer 28 reduces the etching of the conical substrate portion 12bconfining the etch to the region between adjacent wordlines. Thus, the dielectric layers 26 and 28 enable the etching of the trenches 33 in close proximity to the conical substrate portion 12bof surrounding memory cells 10 without the need for a critical mask alignment.
[0037] The etched trenches 33 extend into the lower substrate portion 12ato electrically isolate the wordline of cells 10. The cells in each wordline may be simultaneously severed from adjacent wordlines by severing the connection that remains via the layer 14. Thus, a plurality of wordlines may be electrically isolated by the same self-aligned trench isolation step.
[0038] Referring to FIG. 8, the phase-change material 32 may be deposited over the lower electrode 22 and the insulator 30. A suitable conductive region may be deposited over the deposited lower electrode 22 to form the upper electrode 31 by patterning and etching the phase-change material 32/lower electrode 22 stack.
[0039] The memory cell 10 shown in FIG. 1 may be replicated to form a memory array containing many cells. Such memory arrays can be used as the memory of a wide variety of processor-based systems, such as system 40 in FIG. 9, or in processor-based appliances.
[0040] FIG. 9 depicts one possible embodiment of a computer system 40 that might use a plurality of such memory cells, or memory array, in different configurations. The phase change memory 48 formed according to the principles described herein, may act as a system memory. The memory 48 may be coupled to an interface 44, for instance, which in turn is coupled between a processor 42, a display 46 and a bus 50. The bus 50 in such an embodiment is coupled to an interface 52 that in turn is coupled to another bus 54.
[0041] The bus 54 may be coupled to a basic input/output system (BIOS) memory 62 and to a serial input/output (SIO) device 56. The device 56 may be coupled to a mouse 58 and a keyboard 60, for example. Of course, the architecture shown in FIG. 9 is only an example of a potential architecture that may include the memory 48 using the phase-change material.
[0042] While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.
Claims
What is claimed is:
1. A method of forming a phase-change memory cell comprising: forming a tapered electrode for a phase-change memory cell over a substrate; forming junctions below said tapered electrode; forming a plurality of layers of different doping levels in said substrate; and forming a trench in said layers using the tapered electrode as a mask.
2. The method of claim 1 including covering said tapered electrode with an insulator.
3. The method of claim 1 including covering said electrode with an insulator and forming a pair of trenches using said electrode as a mask.
4. The method of claim 1 including self-aligning the trench to the tapered electrode.
5. The method of claim 1 including forming a tapered electrode by isotropically etching.
6. The method of claim 1 including forming said layers by ion implantation.
7. The method of claim 1 including etching said layers using the same isotropic etch used to form said tapered electrode.
8. The method of claim 7 including forming a tapered substrate portion below said tapered electrode.
9. The method of claim 8 including forming a conical-shaped substrate portion covered by said tapered electrode.
10. The method of claim 8 including covering said tapered substrate portion with an insulator and anisotropic etching said covered tapered substrate portion.
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