Root solver and associated method for solving finite field polynomial equations

[0002] The present invention relates to the field of data storage, and particularly to systems and methods employing a error correction algebraic decoder. More specifically, the present invention describes a key equation solver that calculates the roots of finite field polynomial equations of degree up to six, which lends itself to efficient hardware implementation and low latency direction calculation.

[0003] The use of cyclic error correcting codes in connection with the storage of data in storage devices is well established and is generally recognized as a reliability requirement for the storage system. Generally, the error correcting process involves the processing of syndrome bytes to determine the location and value of each error. Non-zero syndrome bytes result from the exclusive-ORing of error characters that are generated when data is written on the storage medium.

[0004] The number of error correction code (ECC) check characters employed depends on the desired power of the code. As an example, in many present day ECC systems used in connection with the storage of 8-bit bytes in a storage device, two check bytes are used for each error to be corrected in a codeword having a length of at most 255 byte positions. Thus, for example, six check bytes are required to correct up to three errors in a block of data having 249 data bytes and six check bytes. Six distinctive syndrome bytes are therefore generated in such a system. If there are no errors in the data word comprising the 255 bytes read from the storage device, then the six syndrome bytes are the all zero pattern. Under such a condition, no syndrome processing is required and the data word may be sent to the central processing unit. However, if one or more of the syndrome bytes are non-zero, then syndrome processing involves the process of identifying the location of the bytes in error and further identifying the error pattern for each error location.

[0005] The underlying mathematical concepts and operations involved in normal syndrome processing operations have been described in various publications. These operations and mathematical explanations generally involve first identifying the location of the errors by use of what has been referred to as the “error locator polynomial”. The overall objective of the mathematics involved employing the error locator polynomial is to define the locations of the bytes in error by using only the syndrome bytes that are generated in the system.

[0006] The error locator polynomial has been conventionally employed as the start of the mathematical analysis to express error locations in terms of syndromes, so that binary logic may be employed to decode the syndrome bytes into first identifying the locations in error, in order to enable the associated hardware to identify the error patterns in each location. Moreover, error locations in an on-the-fly ECC used in storage or communication systems are calculated as roots of the error locator polynomial.

[0007] Several decoding techniques have been used to improve the decoding performance. One such technique is minimum distance decoding whose error correcting capability relies only upon algebraic redundancy of the code. However, the minimum distance decoding determines a code word closest to a received word on the basis of the algebraic property of the code, and the error probability of each digit of the received word does not attribute to the decoding. That is, the error probability of respective digits are all regarded as equal, and the decoding becomes erroneous when the number of error bits exceeds a value allowed by the error correcting capability which depends on the code distance.

[0008] Another more effective decoding technique is the maximum likelihood decoding according to which the probabilities of code words regarded to have been transmitted are calculated using the error probability of each bit, and a code word with the maximum probability is delivered as the result of decoding. This maximum likelihood decoding permits the correction of errors exceeding in number the error correcting capability. However, the maximum likelihood decoding technique is quite complex and requires significant resources to implement. In addition, the implementation of the maximum likelihood decoding technique typically disregards valuable data such as bit reliability information.

[0009] However, in conventional decoding schemes the Reed Solomon code is not optimized to create the maximum number of erasures for given reliability/parity information, mainly due to the fact that such information is largely unavailable to the Reed Solomon decoder. Furthermore, the key equation solvers implemented in conventional decoders are not designed to solve a weighted rational interpolation problem.

[0010] Thus, there is still a need for a decoding method that reduces the complexity and resulting latency of the likelihood decoding technique, without significantly affecting its performance, and without losing bit reliability information.

[0011] Attempts to render the decoding process more efficient have been proposed. Reference is made to N. Kamiya, “On Acceptance Criterion for Efficient Successive Errors-and-Erasures Decoding of Reed-Solomon and BCH Codes,” IEEE Transactions on Information Theory, Vol. 43, No. 5, September 1997, pages 1477 -1488. However, such attempts generally require multiple recursions to calculate the error locator and evaluator polynomials, thus requiring redundancy in valuable storage space. In addition, such attempts typically include a key equation solver whose function is limited to finite field arithmetic, thus requiring a separate module to perform finite precision real arithmetic, which increases the implementation cost of the decoding process.

[0012] In addition, the decoder of a linear cyclic error correction code, specifically for Reed-Solomon Error correcting code, calculates the error locator polynomial from the syndromes by using an iterative algorithm called the key equation solver. Once the error locator polynomial coefficients have been calculated, the roots of this polynomial, which are the error locations, need to be found.

[0013] The subject of this invention addresses the process of finding the roots of such a polynomial equation. Generally, a simple procedure known as Chien search, which is an iterative search over all possible finite field elements, can be used. The problem associated with this solution is the resulting latency which is as long as the number of codeword symbols. Though it might be possible to speed up the search by conducting several parallel searches, this solution will require the storage of as many copies of the polynomial coefficients as parallel searches used, as well as employing as many sets of constant multipliers as the number of searches used. This would necessitate excessive use of hardware.

[0014] There is thus a need for a method by which roots of finite field polynomial equations can be computed in a direct, non-iterative manner. This method becomes increasingly more complicated when used to solve, in a direct manner, polynomial equations of degree higher than four. As an example, a method of linearizing the algebraic problem and solving for the roots by using Gaussian elimination, converts the polynomial into a matrix and reduces the Gaussian elimination to an efficient circuit implementation. The transformations required to reduce the polynomial to a matrix become increasingly complex as the degree of the polynomial of the equation to be solved increases. Furthermore, the processing of the solutions of the Gaussian elimination required to reduce them to the roots of the original polynomial equation become increasingly complex as the degree of the original polynomial increases. Reference is also made to U.S. Pat. No. 6,154,868 to Cox, et al., titled “Method and Means for Computationally Efficient On-The-Fly Error Correction in Linear Cyclic Codes Using Ultra-Fast Error Location,” which is assigned to the same assignee as the present invention, and which is incorporated herein by reference, and to Hassner et al., “Root Finding Algorithms for GF(2-8) Polynomial Equations of Degree up to 4,” IBM Technical Disclosure Bulletin, Vol. 34, No. 4B, September 1991.

[0015] There is thus a further need to simplify the calculations involved in the transformation of the polynomial to a matrix as well as to introduce a simplifying structure into the set of Gaussian elimination solutions.

[0016] In accordance with the present invention, an error correction algebraic decoder and an associated algebraic algorithm that use a key equation solver for calculating the roots of finite field polynomial equations of degree up to six, which lends itself to efficient hardware implementation and low latency direction calculation.

[0017] The key equation solver generally uses a two-step process. The first step is the conversion of quintic equations into sextic equations, and the second step is the adoption of an invertible Tschirnhausen transformation to reduce the sextic equations by eliminating the degree 5 term. The application of the Tschirnhausen transformation considerably decreases the complexity of the operations required in the transformation of the polynomial equation into a matrix.

[0018] The second step represents an algorithm that defines a specific Gaussian elimination problem, such that an arbitrary solution of this elimination leads to the splitting of the problem of solving quintic and sextic polynomial equations into a problem of finding roots of a quadratic equation and a quartic equation.

[0019] The various features of the present invention and the manner of attaining them will be described in greater detail with reference to the following description, claims, and drawings, wherein reference numerals are reused, where appropriate, to indicate a correspondence between the referenced items, and wherein:

[0020] FIG. 1 is a schematic illustration of a data storage system such as a disk drive, that implements an on-the-fly algebraic error correction code (ECC) according to the present invention;

[0021] FIG. 2 is a block diagram detailing the architecture of a buffered hard disk controller that includes an on-the-fly (OTF) error correction code (ECC) system for implementing the on-the-fly error correction code according to the present invention;

[0022] FIG. 3 is a block diagram of the data storage system of FIG. 1, depicting data flow along a read channel and a write channel of the hard drive controller of FIG. 2, and illustrating an exemplary on-the-fly error correction code system comprised of an ECC read processor and an ECC write processor;

[0023] FIG. 4 is a block diagram of the data storage system of FIG. 1, detailing the main components of an error correction code module that forms part of the ECC read processor and the ECC write processor of FIG. 3;

[0024] FIG. 5 is a functional flow chart that illustrates a general method for implementing an error correction code by means of a key equation solver that calculates the roots of finite field polynomial equations of degree up to six for use in the data storage system of FIG. 4; and

[0025] FIG. 6 is comprised of FIGS. 6A, 6B, 6C, and 6D, and represents a functional flow chart of a specific example of the error correction code method of FIG. 5.

[0026] FIG. 1 illustrates a disk drive 10 comprised of a head stack assembly 12 and a stack of spaced apart magnetic, optical and/or MO data storage disks or media 14 that are rotatable about a common shaft 16. The head stack assembly 12 includes a number of actuator arms 20 that extend into spacings between the disks 14, with only one disk 14 and one actuator arm 20 being illustrated for simplicity of illustration. The disk drive 10 further includes a preamplifier 44, a read/write channel 48 that includes a byte reliability generator 49, and a hard disk controller 50 that includes an error correction algebraic decoder 200 of the present invention.

[0027] The head stack assembly 12 also includes an E-shaped block 24 and a magnetic rotor 26 attached to the block 24 in a position diametrically opposite to the actuator arms 20. The rotor 26 cooperates with a stator (not shown) for the actuator arms 20 to rotate in a substantially radial direction, along an arcuate path in the direction of an arrow A. Energizing a coil of the rotor 26 with a direct current in one polarity or the reverse polarity causes the head stack assembly 12, including the actuator arms 20, to rotate around axis P in a direction substantially radial to the disks 14. A head disk assembly 33 is comprised of the disks 14 and the head stack assemblies 12.

[0028] A transducer head 40 is mounted on the free end of each actuator arm for pivotal movement around axis P. The magnetic rotor 26 controls the movement of the head 40 in a radial direction, in order to position the head 40 in registration with data information tracks or data cylinders 42 to be followed, and to access particular data sectors on these tracks 42.

[0029] Numerous tracks 42, each at a specific radial location, are arrayed in a concentric pattern in a magnetic medium of each surface of data disks 14. A data cylinder includes a set of corresponding data information tracks 42 for the data surfaces of the stacked disks 14. Data information tracks 42 include a plurality of segments or data sectors, each containing a predefined size of individual groups of data records that are saved for later retrieval and updates. The data information tracks 42 can be disposed at predetermined positions relative to a servo reference index.

[0030] FIG. 2 illustrates an exemplary architecture of a buffered hard disk controller 50 that comprises an on-the-fly (OTF) error correction code (ECC) system 100 for implementing the on-the-fly error correction code according to the present invention. It should be clear that the present invention is not limited to this specific architecture and that it can be implemented by, or in conjunction with other architectures.

[0031] The hard drive controller 50 includes a logic drive circuit 105 that formats data from the hard disk assembly 33, for example from 8 bits to 32 bits. A FIFO register 110 stores the formatted data and exchanges the same with a sector buffer 120. The ECC system 100 receives the formatted data from the drive logic circuit 105 and performs the error correction coding algorithm of the present invention, as described herein.

[0032] A buffer manager 115 controls data traffic between the ECC system 100, a sector buffer (i.e., random access memory) 120, and a microprocessor 125. Another FIFO register 130 stores data and exchanges the same with the sector buffer 120. A sequence controller 135 is connected between the drive logic circuit 105, the microprocessor 125, and a host interface 140, to control the sequence operation of the data traffic and various commands across the hard drive controller 50. The host interface 140 provides an interface between the hard drive controller 50 and a host 60 (FIG. 1).

[0033] FIG. 3 represents a block diagram of the hard disk controller 50 of FIG. 2 that includes an on-the-fly error correction code system 100 comprised of an ECC read processor 163 and an ECC write processor 167. When sequences of digital binary data are to be written onto the disk 14, they are placed temporarily in a buffer 165 and subsequently processed and transduced along a write path or channel (157,167 and 169).

[0034] First, a predetermined number of binary data elements, also termed bytes, in a data string are moved from the buffer 165 and streamed through an ECC write processor 167. In the ECC write processor 167, the data bytes are mapped into codewords drawn from a Reed-Solomon code. Next, each codeword is mapped in a write path signal-shaping unit 169 into a run length limited or other bandpass or spectral-shaping code and changed into a time-varying signal. The write path signal-shaping unit 169 includes an encoder 202 (FIG. 4) for encoding the signals as described herein. The time-varying signal is applied through an interface read/write transducer interface 157 and thence to the write element in a magnetoresistive or other suitable transducer head 40 for conversion into magnetic flux patterns.

[0035] All the measures starting from the movement of the binary data elements from buffer 165 until the magnetic flux patterns are written on a selected disk track 42 (FIG. 1) as the rotating disk 14 passes under the head 40 are synchronous and streamed. For purposes of efficient data transfer, the data is destaged (written out) or staged (read) a disk sector at a time. Thus, both the mapping of binary data into Reed-Solomon codewords and the conversion to flux producing time-varying signals must be done well within the time interval defining a unit of recording track length moving under the transducer. Typical units of recording track length are equal fixed-length byte sectors of 512 bytes.

[0036] When sequences of magnetic flux patterns are to be read from the disk 14, they are processed in a read path or channel (157,159,161, and 163) and written into the buffer 165. The time-varying signals sensed by transducer 40 are passed through the read/write transducer interface 157 to a digital signal extraction unit 159. Here, the signal is detected and a decision is made as to whether it should be resolved as a binary 1 or 0. As these 1′s and 0′s stream out of the signal extraction unit 159, they are arranged into codewords in the formatting unit 11.

[0037] Since the read path is evaluating sequences of Reed Solomon codewords previously recorded on the disk 14, then, absent error or erasure, the codewords should be the same. In order to test whether that is the case, each codeword is applied to an ECC read processor 163 over a path from a formatter 161. Also, the output from the ECC processor 163 is written into buffer 165. The read path also operates in a synchronous datastreaming manner such that any detected errors must be located and corrected within the codeword well in time for the ECC read processor 163 to receive the next codeword read from the disk track 42. The buffer 165 and the read and write channels may be monitored and controlled by the microprocessor 125 (FIG. 2) to ensure efficacy where patterns of referencing may dictate that a path not be taken down, such as sequential read referencing.

[0038] Having described the general environment in which the ECC system 100 of the present invention operates, the error correction algebraic decoder (ECC decoder) 200, forming part of the ECC system 100 will now be described. Each of the ECC read processor 163 and the ECC write processor 167 includes an ECC decoder 200 that can be implemented in hardware using digital logic. The main components of the ECC decoder 200 are illustrated in FIG. 4.

[0039] The ECC system 100 of FIG. 4 includes several functional units such as the encoder 202, the preamplifier 44, the read / write channel 48, a syndrome generator 205, and a key equation solver that contains the ECC decoder 200 of the present invention. The syndrome generator 205 generates syndromes 305 (FIG. 5) as is known, or available in the field.

[0040] As it will be detailed more fully in FIGS. 5 and 6, the ECC decoder 200 uses a two-step process to calculate the roots of finite field polynomial equations of degree up to six and to generate error locator and evaluator polynomials 450. In turn, the error locator and evaluator polynomials 450 are solved to generate the error locations and values 460 as described, for example, in U.S. Pat. No. 5,428,628 to Hassner et al., which is assigned to the same assignee as the present invention, and which is incorporated herein by reference.

[0041] The operation of the ECC decoder 200 will now be described in detail in connection with FIGS. 5 and 6 in view of a specific example, for the purpose of illustration and not limitation. Referring now to FIG. 5, the decoding method 500 receives the syndromes 505 and adopts, at step 510, an invertible Tschirnhausen transformation to reduce the sextic equations by eliminating the degree 5 term. The application of the Tschirnhausen transformation considerably decreases the complexity of the operations required in the transformation of the polynomial equation into a matrix. The normalized equations are illustrated by block 515.

[0042] The method 500 then defines a specific Gaussian elimination at step 520, such that an arbitrary solution of this elimination leads to the splitting of the problem of solving quintic and sextic polynomial equations into a problem of finding roots of quadratic equation and quartic equations 530.

[0043] Referring now to FIG. 6, the method 500 of FIG. 5 will be described in more detail. The syndrome generator 205 of FIG. 4 generates a sextic error locator polynomial 505 with coefficients {1, f₅, f₄, f₃, f₂, f₁, f₀}, as follows:

[0044] X⁶+f₅.X⁵+f₄.X⁴+f₃.X³+f₂.X²+f₁.X+f₀=0.

[0045] It is an object of the key equation solver 450 of FIG. 4 to determine the roots of this sextic polynomial according to the teaching of the present invention.

[0046] The method 500 performs a normalization process at steps 510 (FIG. 5) which is illustrated by steps 605 through 640 in FIG. 6. The purpose of the normalization process is to transform the error locator polynomial 505 to eliminate one or more of the coefficients 1, f5, f4, f3, f2, f1, f0. In the example illustrated in FIG. 6, coefficient f5 is eliminated.

[0047] At step 615, the method 500 carries out a first normalization step by transforming the coefficients 1, f5, f4, f3, f2, f1, f0 and calculating a new set of coefficients {N1} 610, as follows:

[0048] t:=f₂+f₅(f₃+f₅·f₄)

[0049] f₁:=f₅·t+f₁

[0050] t₂:=f₅³+f₃

[0051] C₄:=f₅·t₂

[0052] C₀:=f₅·f₁

[0053] C₃:=f₅²+f₄

[0054] At step 615, the method 500 checks for degenerative situations, that it is checks whether the error locator polynomial 505 is a square of a cubic polynomial, in which event the sextic error locator polynomial 505 will have three rather than six roots, significantly reducing the complexity of the solution. To this end, the method 500 checks for the equality of two of the transformed coefficients (i.e., f1 and t2) to zero.

[0055] If such equality is confirmed at decision step 615, the existence of degenerative situations is validated, and the method 500 defines three monic quadratic equations 620 with three roots {γ₁, γ₂, γ₃}, from which the six roots 625 of the sextic error locator polynomial 505 could be derived.

[0056] Returning now to decision step 615, if the method 500 confirms the absence of degenerative situations, it proceeds to step 630 (FIG. 6B) and completes the normalization step 630, and transforms the set of coefficients {N1} into a new set of coefficients {N2} 635, as follows:

[0057] C₁:=f²+t·C₀+f₀·C₄

[0058] C₂:=C₃·C₀+t·(t+C₄)

[0059] C₃:=C₃·C₄=t₂²=C₀

[0060] C₄:=C₄+(f₅²+f₄)²

[0061] C₀:=f₀(f₀+C₀)

[0062] This second normalization step 630 results in normalized sextic coefficients 1, 0, C4, C3, C2, C1, C0, eliminating one of the original coefficients (i.e., f5). The normalized coefficients 1, 0, C4, C3, C2, C1, C0 are also denoted by block 515 in FIG. 5.

[0063] Having normalized the coefficients, the method 500 proceeds with the specific Gaussian elimination process, as illustrated by steps 645 through 685 in FIG. 6 and step 520 in FIG. 5. At step 645 the method 500 calculates matrices t and M, as indicated by block 650:

[0064] t:=C₁.C₂. C₃+C₀. C₃²+C₁². C₄

[0065] M:=C₃. t+C₁³

[0066] The method 500 then proceeds to decision step 655 where it checks the equality of matrix M to zero. If it determines that matrix M is equal to zero, then method 500 confirms the existence of degenerative solutions and the existence of double roots 660 in the form of quadratic equations 665. In this example, method 500 calculates the special roots {γ₁, γ₂} and proceeds to step 700 of FIG. 6D, as it will explained later.

[0067] Returning to decision step 655, if method 500 confirms the non equality of matrix M to zero, it proceeds to step 670 where it calculates the matrix M for Gaussian evaluation, as shown in block 680:

[0068] M:=M+(t+C₀²)·S²,

[0069] t:=C₄·t

[0070] M:=M+(t+C₁(C₁·C₂+C₀·C₃))·S

[0071] t:=C₂²+C₁·C₃

[0072] M:=M+t(C₃²)·S

[0073] M:=M+(t·C₄²+C₃⁴)·S²

[0074] M:=M+t(t+C₄⁴)·S³+·S⁴

[0075] At step 685, method 500 performs Gaussian elimination with g₁, as the solution (g₁:=X), as illustrated in block 695, where q₂(X) is a transformed quadratic equation, as follows:

[0076] h₃:=g₁³+C₄·g₁+C₃

[0077] h₄:=g₁·h₃

[0078] d₁:=(C₃·h₃+C₁·g₁)

[0079] d₀:=h₄·(h₄+C₂)+C₁·h₃+C₀·g₁²

[0080] q₂(X):=d₁X²+d₁·g₁X+d₀

[0081] Having determined the quadratic equation q₂(X), method 500 calls upon a quadratic equation solver to calculate the roots {γ₁, γ₂} at step 690. Method 500 then proceeds to step 700 where it inverts the roots {γ₁, γ₂} to generate the roots {X₁, X₂} of the original equation (block 505) as illustrated in block 710: $D_0\left(y\right)=\left(\left(y+f_5^2+f_4\right)·y+t\right)y+f_1$ $D_1\left(y\right)=f_1+y·t_2$ $X_i=\frac{D_0\left({\gamma }_i\right)}{D_1\left({\gamma }_i\right)}i=1,2$

[0082] Using the roots {X₁, X₂}, method 500 defines, at step 711 a quartic polynomial, as illustrated in block 730, from the original sextic polynomial by removing the roots {X₁, X₂} generated at step 700 (and block 710). Method 500 then resolves the quartic equation at step 720 to obtain the roots {X₃, X₄, X₅, X₆} of the polynomial the original sextic polynomial:

[0083] S₀:=X₁·X₂

[0084] S₁:=X₁+X₂

[0085] f₅:=f₅+S₁

[0086] f₂:=f₂+S₀·(S₀+f₄)

[0087] f₄:=S₁·f_5+f4+S₀

[0088] f₃:=S₁·f₄+f₃

[0089] f₂:=S₁·f₃+f₂

[0090] f₃:=f₃+f₅·S₀

[0091] q₄(X):=x⁴+f₅·x³+f₄·x²+f₃·x+f₂

[0092] It is to be understood that the specific embodiments of the invention that have been described are merely illustrative of certain application of the principle of the present invention. Numerous modifications may be made to the error correcting system and associated method described herein, without departing from the spirit and scope of the present invention. Moreover, while the present invention is described for illustration purpose only in relation to a data storage system, it should be clear that the invention is applicable as well to various communications and data processing systems.