Personal communications device with ratio counter

[0002] This invention is generally related to a personal communications device and, more particularly, to a system and method for determining the ratio between the frequency of two clocks within the personal communications device.

[0003] In communications devices such as that described in U.S. Pat. No. 5,945,944 to Krasner et al. for a Method and apparatus for Determining Time For GPS Receivers, the disclosure of which is hereby incorporated herein by reference, it is common for there to be multiple clocks or oscillators that provide clock signals of varying characteristics, including frequency, to device circuitry. In order for the device to operate properly, it is often necessary for certain device operations which operate at different clock frequencies to be synchronized. In order to accomplish this it is necessary to determine the frequency at which a clock operates in relation to a known, or predetermined, reference clock. This is typically done by counting, for a predetermined and known period of time, the number of cycles of a known reference clock having a known frequency, as well as the number of cycles of a second clock of unknown frequency.

[0004] A typical set-up for determining a ration between two clock signals is shown in FIG. 1. With reference to FIG. 1, there is provided a numerator latch 1 for receiving and storing the contents of an incrementing counter 7 when a load count signal LCS is received by the numerator latch 1. Incrementing counter 7 is clocked by a clock signal CLK 1. With each pulse of the clock signal CLK 1 the count value of the incrementing counter 7 increases by a value of one (1). There is also provided a denominator latch 4 which, upon receiving load count signal LCS, receives and stores the contents of a incrementing counter 5. Incrementing counter 5 is clocked by a clock signal CLK 2. The value of incrementing counter 5 increases by a value of one (1) with each pulse of the clock signal CLK 2. Upon receiving the load count signal LCS, numerator latch 1 and denominator latch 4 make their respective values available for output as numerator out signal 8 and denominator out signal 9, respectively. In order to compute the ratio of the two clock signals CLK 1 and CLK 2, the values of numerator out signal 8 and denominator out signal 9, respectively. In order to compute the ratio of the two clock signals CLK 1 and CLK 2, the values of numerator out signal 8 and denominator out signal 9 can be divided to produce the ratio between clock signals CLK 1 and CLK 2.

[0005] Where, for example, the frequency of CLK 1 is known, the ratio between the value of numerator latch 1 and denominator latch 4 can be used to compute the frequency of the clock signal CLK 2. This process is typically carried out as a part of a dedicated clock pulse count operation and is only as accurate as the resolution of the counting device will allow. These known ratio-counting devices do not provide for dynamically increasing the accuracy of the count while counting of the clock cycles takes place. Thus, a need exists in the industry to address the deficiencies and inadequacies.

[0006] This invention is directed to a personal communications device with a ratio counter providing tracking transitioning edges of two clocks so as to generate a signal to initiate capture of a clock cycle count. Provisions for tracking the transitioning edges include a storage memory for storing a first and a second value selected in accordance with the principles of convergents of continued fractions. A first and second counter each responding to first and second clock signal, respectively. The first and second counter each count clock cycles of the respective clock signal. A first register for capturing the count of the first counter and a second register for capturing the count of the second counter.

[0007] This invention provides a system and method for calculating a ratio between two clock frequencies in a personal communications device. In architecture, the system may be implemented by a first receiver that includes a first clock generating a first clock signal for clocking the first receiver; a second receiver that includes a second clock generating a second clock signal for clocking the second receiver; and a frequency ratio counter for providing a ratio between the frequency of the first clock signal and the frequency of the second clock signal.

[0008] The invention can also be viewed as providing a method for determining a ratio between the frequencies of two clocks. In this regard, the method can be broadly summarized by the following steps: counting successive clock pulses of a fist clock signal for a duration of time determined in accordance with a control signal, counting successive clock pulses of a second clock signal for the duration of time, reading the count of the clock pulses of the first clock signal upon the elapse of the duration; and reading the count of the clock pulses of the second clock signal upon the elapse of the duration. In this method, the control signal is generated where a transitioning pulse edge of the first clock coincides and is in synchronization with a transitioning pulse edge of the second clock.

[0009] Other systems, methods, features, and advantages of the invention will be or become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims.

[0010] The invention can be better understood with reference to the following figures. The components in the figures are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the invention. Moreover, in the figures, like reference numerals designate corresponding parts throughout the several views.

[0011] FIG. 1 is a diagram illustrating a typical system for determining a clock frequency ratio;

[0012] FIG. 2 is a diagram illustrating a personal communications device according to the invention;

[0013] FIG. 3 is a detailed description of one embodiment of a personal communications device according to the invention;

[0014] FIG. 4 is a timing diagram illustrating a relation between various clock signals and a control signal output;

[0015] FIG. 5 is a diagram illustrating a further embodiment of the invention; and

[0016] FIG. 6 is a flowchart illustrating the method of the invention.

[0017] With reference to FIG. 2, a general description of a personal communications device 100 with ratio counter provisions according to the invention is illustrated. Clock ratio counter 110 includes a register 10 and a register 11. There is also provided a control signal generator 15 that alternately selects and receives an input value from register 10 and register 11 as well as an input of a clock signal CLK 1 from a clock under examination. This may be, for example, a clock signal from the clock signal source (clock) of a telecommunications receiver. A second clock signal CLK 2 is received from a second clock source under evaluation. CLK 2 may be, for example, a clock signal from a clock source of a global positioning system (GPS) receiver. The values stored in register 10 and 11 are pre-selected. The selection of these values is discussed in more detail below. Control signal generator 15 responds to these inputs by producing a control signal S2 that is provided to count capture section 16.

[0018] FIG. 3 illustrates a more detailed description of an embodiment of the ration counter 110 according to the invention. It can be seen that control signal generator 15 includes multiplexer 26, a decrementing counter 17, a flip-flop 19 and a pulse generator 20. Multiplexer 26 is used to select between the input from either register 10 or register 11 in accordance with an edge transition signal S1 from flip-flop 19. Depending upon which register, 10 or 11, is selected by multiplexer 26, the contents of the selected register, 10 or 11, are input to decrementing counter 17. The value loaded into decrementing counter 17 is then decremented by one (1) for each pulse of the clock signal CLK 1. Once the contents of decrementing counter 17 have reached zero (0) value, decrementing counter 17 issues an enable signal 22 to flip-flop 19. Flip-flop 19 then outputs an edge transition signal S1, in accordance with the inputs of clock signals CLK 1 and CLK 2. The edge transitions signal S1 from flip-flop 19 is also fed to pulse generator 20. In response to edge transition output S1, pulse generator 20 generates a control signal S2. Control signal S2 is then used to enable numerator latch 1 and denominator latch 4 so as to receive the contents of incrementing counters 7 and 5, respectively. The contents of numerator latch 1 and denominator latch 4 can be read out and used to specify the ration between the frequency of clock signal CLK 1 and the frequency of clock signal CLK 2.

[0019] FIG. 4 illustrates a relation between a clock signal CLK 1 and a clock signal CLK 2 and edge transition signal S1. Both CLK 1 and CLK 2 have a leading edge 70, and a trailing edge 71. For purposes of discussion, it will be understood that leading edge 70 and trailing edge 71 are transitioning edges. From FIG. 4 it can be seen that the instances at which clock signal CLK 1 and clock signal CLK 2 have transitioning edges which coincide and are in synchronization with each other is a reoccurring, although not constant, scenario. FIG. 4 shows that at the point A, a leading edge 70 of clock signal CLK 1 begins to transition from low to high at the same time that a leading edge 70 of clock signal CLK 2 begins to transition from low to high. In response, edge transition signal S1 from flip-flop 19 changes from low to high and a control signal S2 is generated. Similarly, at point B, a trailing edge 71 of clock signal CLK 1 begins to transition from high to low at the same time that a trailing edge 71 of clock signal CLK 2 begins to transition from high to low. In response, edge transition signal S1 from flip-flop 19 changes from high to low and control signal S2 is again generated.

[0020] With reference to FIG. 5, a further embodiment of portable communications device 100 is illustrated. Here it can be seen that the ratio counter 110 of the invention is incorporated as a part of a baseband section 150 of portable communications device 100. There is provided a code division multiple access (CDMA) radio frequency (RF) section 125 which provides a clock signal CLK 1 to the ratio counter 110 of the baseband section 150. Further, global positioning system (GPS) radio frequency section 130 is provided which provides a second clock signal CLK 2 to the ratio counter 110 of the baseband section 150. The ratio counter output is utilized by the circuitry of the portable communications device 100 to optimize circuit operations and allow for reduced power consumption.

[0021] In personal communication device 100, information indicative of the ratio between the frequencies of the two clock signals CLK 1 and CLK 2 is generated and output for use by device circuitry. One of either register 10 or register 11 is used to store a value representing a reference clock frequency while the other of register 10 or register 11 is used to store a value representing a close approximation of the frequency of a second clock. These values are then alternately used to generate a control signal S2 for causing the count value of decrementing counters 5 and 7 to be captured and, if desired, read out. Typically, in the portable communications device 100 of FIG. 5, the clock signal CLK 1 driving the CDMA RF section 125 is relatively stable and of a known frequency. While the GPS clock signal CLK 2 driving the GPS RF section 130 is often generated by a crystal oscillator and is less stable thus, the accuracy of the frequency of CLK 2 at any given time is prone to vary. This is due to the fact that the frequency of a crystal oscillator tends to fluctuate as the temperature changes. Given this, register 11 is loaded with a value that is a close approximation of the frequency of the GPS clock signal CLK 2 is loaded into register 11 as the second value.

[0022] In a preferred embodiment of the invention, the values loaded into register 10 and register 11 are chosen in accordance with calculations based upon the principles of convergents of continued fractions. More particularly, convergents of continued fractions are used to generate a series of rational approximations to an actual ratio. These ratios are then used as the values input into in the registers 10 and register 11, respectively.

[0023] The continued fraction expansion of real number x is expressed by Equation 1 which follows. $\begin{array}{cc}{a}_0+\frac{1}{a_1+\frac{1}{a_2+\dots }}& \left[\mathrm{Equation}1\right]\end{array}$

[0024] Here, the integers a_{1 . . .}are partial quotients. Rational numbers have a finite number of partial quotients, while the rational numbers have an infinite continued fraction expansion. If the number x has partial quotients a₀, a₁. . . , the rational number p_n/q_nformed by considering the first n partial quotients a₀, a₁. . . , a sub n is called the n^thconvergent of x. The convergence of that number provides a rational approximation with a small denominator to a given real number. Successive convergence will have error that oscillates positive and negative and which sequentially converges to the exact ratio between, for example, the frequency of clock signal CLK 1 and clock signal CLK 2. In view of this, continued fraction expansions are useful for selecting the values (divisors) which should be loaded into register 10 and register 11 of the invention 100.

[0025] As an example of choosing values for registers 10 and 11, where, for example, CLK 1 is a known frequency of 13 MHz and CLK 2 is believed to be approximately 10.949 MHz; possible values (columns A-H) for loading into register 10 and 11 chosen in accordance with the principles of convergents of continued fractions are shown in TABLE 1 below.

[0026] With the above ratios, the value of the numerator of the ratio would be loaded into one register, register 10 for example, and the denominator would be loaded into the second register, register 11 for example. For example, the values shown for case B (Column B) in TABLE 1 above could be loaded into the registers as follows: the numerator value “5” could be loaded into register 10, while the denominator value “6” could be loaded into register 11.

[0027] FIG. 6 is a flowchart illustrating the method of determining a ratio between two clock frequencies of the invention. Successive clock pulses of a first clock signal are counted 300 for a predetermined duration of time and successive clock pulses of a second clock signal are counted 302 for the duration of time. It is then determined whether a transitioning edge of the first clock signal coincides with and is in synchronization with a transitioning edge of the second clock signal 305. If so, a control signal is generated which signals the elapse of the duration of time. Read out the count of clock pulses of the first clock signal 310 and the second clock signal 312 upon the elapse of the duration of time.

[0028] The ratio counter 110 of the invention can be implemented in hardware, software, firmware, or a combination thereof. In a preferred embodiment(s), the invention 100 is implemented in software or firmware that is stored in a memory and that is executed by a suitable instruction execution system. If implemented in hardware, as in an alternative embodiment, the invention 100 can implemented with any or a combination of the following technologies, which are all well known in the art: a discrete logic circuit(s) having logic gates for implementing logic functions upon data signals, an application specific integrated circuit having appropriate logic gates, a programmable gate array(s) (PGA), a fully programmable gate array (FPGA), etc.

[0029] The flow chart of FIG. 6 shows the architecture, functionality, and operation of a possible implementation of the ratio counting method of the invention in software. In this regard, each block represents a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the blocks may occur out of the order noted in FIG. 6. For example, two blocks shown in succession in FIG. 6 may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved, as will be further clarified hereinbelow.

[0030] It should be emphasized that the above-described embodiments of the invention, particularly, any “preferred” embodiments, are merely possible examples of implementations, merely set forth for a clear understanding of the principles of the invention. Many variations and modifications may be made to the above-described embodiment(s) of the invention without departing substantially from the spirit and principles of the invention. All such modifications and variations are intended to be included herein within the scope of this disclosure and the invention and protected by the following claims.