Method and apparatus for aligning sub-stream splice points in an information stream

[0002] This application is a continuation-in-part of U.S. application Ser. No. 09/092,809, filed on Jun. 5, 1998.

[0003] This application claims the benefit of U.S. Provisional Application No. 60/125,630 filed on Mar. 22, 1999, which is herein incorporated by reference.

[0004] The invention relates to communications systems generally and, more particularly, the invention relates to information distribution systems delivering one or more a relatively low bandwidth information streams as information sub-streams of a relatively high bandwidth information stream.

[0005] In several communications systems the data to be transmitted is compressed so that the available bandwidth is used more efficiently. For example, the Moving Pictures Experts Group (MPEG) has promulgated several standards relating to digital data delivery systems. The first, known as MPEG-1 refers to ISO/IEC standards 11172 and is incorporated herein by reference. The second, known as MPEG-2, refers to ISO/IEC standards 13818 and is incorporated herein by reference. A compressed digital video system is described in the Advanced Television Systems Committee (ATSC) digital television standard document A/53, and is incorporated herein by reference.

[0006] MPEG and MPEG-like information streams may be spliced together in a relatively seamless manner by defining “In Points” and “Out Points” for each stream that are indicative of, respectively, appropriate stream entry and exit points. An MPEG-like information stream that contains such In Points and Out Points is said to be spliceable. The Society of Motion Picture and Television Engineers (SMPTE) has proposed a standard SMPTE 312M defining such splicing points entitled “Splice Points for MPEG-2 Transport Streams,” which is incorporated herein be reference in its entirety.

[0007] Many information providers, such as television studios, continue to make substantial investments in equipment conforming to a serial digital interface defined in SMPTE standard 259M. The SMPTE 259 interface was originally developed to carry PAL and NTSC-format digital video in a particular uncompressed form and with a sampling rate of exactly 27.000 MHz. To help preserve this investment, a standard is emerging within SMPTE to carry other forms of video and audio over SMPTE 259. This emerging standard is often referred to as the Serial Data Transport Interface (SDTI) standard or SMPTE 305M. The SMPTE 259 standard and proposed SMPTE 305M standard are incorporated herein by reference in their entireties.

[0008] The proposed SMPTE 305M standard specifies a data stream used to transport packetized data, such as MPEG-like data, within a television studio or production center environment in a manner compatible with SMPTE 259. Thus, relatively low bitrate MPEG streams (e.g., 30 Mbps) may be transported within a studio environment as a sub-stream of a relatively high bitrate SDTI stream (e.g., 270 Mbps or 360 Mbps).

[0009] Unfortunately, the SMPTE 305M standard does not provide a solution to the problem of sub-stream splicing. Specifically, to seamlessly splice an MPEG stream carried in an SDTI stream, the MPEG stream must be removed from the SDTI stream, spliced with another MPEG stream (possibly within a respective SDTI stream) and inserted back into an SDTI stream. This is because typical switching equipment switches or edits SMPTE 259 streams only at frame boundaries.

[0010] Therefore, it is seen to be desirable to provide a method and apparatus that allows seamless splicing of MPEG information streams carried within SDTI streams. More generally, it is seen to be desirable to provide a method and apparatus that allows seamless splicing of any frame delineated or segmented information stream carried as a sub-stream within a relatively higher bitrate, frame delineated or segmented information stream.

[0011] The invention provides a low cost method and concomitant apparatus for incorporating one or more relatively low bitrate information streams (e.g., MPEG) into a relatively high bitrate information stream (e.g., SDTI) in a manner aligning low bitrate sub-stream splice entrance points and splice exit points within the frame boundaries of the high bitrate information stream. In this manner, the splicing of the relatively high bitrate information stream at appropriate In Frames and Out Frames will provide relatively seamless splicing of information sub-streams. Additionally, the packing and unpacking methods are implemented such that the temporal offset between elementary streams carried within relatively low bitrate information stream is removed, i.e., the elementary streams are synchronized.

[0012] The teachings of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which:

[0013] FIG. 1 depicts a prior art arrangement of carrying an MPEG data stream within an SDTI data stream;

[0014] FIG. 2 depicts a serial data transport (SDTI) bitstream data structure carrying an MPEG information sub-stream according to an embodiment of the invention;

[0015] FIG. 3 depicts a SDTI bitstream data structure carrying a constrained MPEG information sub-stream according to an embodiment of the invention;

[0016] FIG. 4 is a high level block diagram of an SDTI bitstream packaging apparatus according to the invention and suitable for producing the SDTI bitstream data structure of FIG. 2 and FIG. 3;

[0017] FIG. 5 depicts a controller suitable for use in the bitstream packaging apparatus of FIG. 4;

[0018] FIG. 6A depicts a flow diagram of a buffer management routine according to the invention and suitable for use in the SDTI bitstream packaging apparatus of FIG. 4 and the controller of FIG. 5;

[0019] FIG. 6B depicts a flow diagram of a framing routine according to the invention and suitable for use in the SDTI bitstream packaging apparatus of FIG. 4;

[0020] FIG. 7A is a high level block diagram of an SDTI bitstream switching apparatus suitable for switching between SDTI bitstreams having a data structure according to FIG. 3;

[0021] FIG. 7B is a high level block diagram of an SDTI bitstream switching apparatus suitable for switching between SDTI bitstreams having a data structure according to FIG. 2 or FIG. 3;

[0022] FIG. 8A depicts a flow diagram of a buffer write routine according to the invention and suitable for use in the SDTI bitstream packaging apparatus of FIG. 4 and the controller of FIG. 5;

[0023] FIG. 8B depicts a flow diagram of a buffer read routine 800B according to the invention and suitable for use in the SDTI bitstream packaging apparatus of FIG. 4 and the controller of FIG. 5;

[0024] FIG. 9 illustrates a sub-stream carrying both audio and video elementary streams;

[0025] FIG. 10 illustrates an MPEG transport stream having spliceable segments than can be transported in a frame synchronous environment;

[0026] FIG. 11 illustrates an SDTI bitstream switching apparatus suitable for switching SDTI bitstreams carrying sub-streams that, in turn, carry temporally offset elementary streams; and

[0027] FIG. 12 illustrates a detailed block diagram of the Splice Aware Audio/Video Aligner of the present invention.

[0028] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures.

[0029] After considering the following description, those skilled in the art will clearly realize that the teachings of the invention can be readily utilized in any information processing system in which a frame delineated information stream is carried as a sub-stream within a relatively higher bitrate, frame delineated information stream. The invention has particular applicability to frame delineated information sub-streams having defined splicing points, such as MPEG-like in points and out points.

[0030] An embodiment of the invention will be described within the context of a bitstream packaging method and concomitant apparatus that packages an MPEG transport stream into an SDTI bitstream. However, the scope and teachings of the invention have much broader applicability and, therefore, the invention should not be construed as being limited to the disclosed embodiments.

[0031] FIG. 1 depicts a prior art serial data transport (SDTI) bitstream data structure carrying an MPEG information sub-stream. The top row of FIG. 1 depicts three splicing segments SS1-SS3 of a 30 Mbps MPEG transport stream 110. Each splicing segment begins with an In Point and ends with an out point. The bottom row of FIG. 1 depicts a resulting 270 Mbps SDTI bitstream 120 formed using prior art techniques. Specifically, the MPEG data from the three splicing segments SS1-SS3 of MPEG transport stream 110 is distributed as “chunks” of data comprising one or more MPEG frames over, illustratively, 14 frames F1-F14 of the SDTI bitstream 120. Since the MPEG data is merely distributed throughout the available SDTI frames, the installed base of SDTI routing switchers (and other switching equipment performing switching operations at SDTI frame boundaries) will produce switched or spliced SDTI bitstreams including discontinuous, or non-seamless MPEG sub-streams. It should be noted that the “chunks” of data do not need to be evenly distributed or of similar size to utilize the teachings of the present invention.

[0032] The present invention aligns an information sub-stream, such as an MPEG transport stream or elementary stream within, illustratively, an SDTI stream. The information sub-stream is carried in a payload portion of an SDTI information frame. The information sub-stream may comprise any type of information stream, though the invention has particular applicability to framed information streams. The present incorporates one or more sub-stream information frames within a single SDTI frame. Each sub-stream information frame may be associated with an appropriate splicing entrance point (e.g., an In Point), an appropriate splicing exit point (e.g., an Out Point) or neither.

[0033] Within the context of MPEG sub-streams, an SDTI Out Frame is defined as a data frame that contains MPEG data including a terminating Out Point. The terminating Out Point is located in a terminal or terminating position of the payload portion of the SDTI frame. That is, an SDTI Out Frame does not contain any sub-stream data after the last Out Point. Within the context of MPEG sub-streams, an SDTI In Frame is defined as a data frame that contains MPEG data including an initial In Point. That is, an SDTI In Frame does not contain any sub-stream data before the first In Point. Within the context of MPEG sub-streams, an SDTI In/Out Frame is defined as a data frame that contains MPEG data including an initial In Point and a terminating Out Point. That is, an SDTI In/Out Frame does not contain any sub-stream data after the last Out Point or before the first In Point. Thus, an SDTI In/Out Frame comprises an In Point, followed by some sub-stream data (possibly including several In Points and Out Points), followed by a terminating Out Point. Within the context of MPEG sub-streams, an example SDTI In/Out Frame may comprise, illustratively, an entire MPEG group of pictures (GOP).

[0034] The terminating or terminal position described above is not necessarily the last possible memory or storage location within the payload of an SDTI stream. Rather, the terminating or terminal position is simply the last position within the payload portion that is utilized to store information associated with a particular sub-stream. In the case of a plurality of unique sub-streams, a payload portion is said to include several terminal or terminating positions, one for each respective unique sub-stream. Similarly, an initial position is not necessarily the first possible memory or storage location within the payload of an SDTI stream. Rather, the initial position is simply the first position within the payload portion that is utilized to store information associated with a particular sub-stream. In the case of a plurality of unique sub-streams, a payload portion is said to include several initial positions, one for each respective unique sub-stream.

[0035] FIG. 2 depicts a serial data transport (SDTI) bitstream data structure carrying an MPEG information sub-stream according to an embodiment of the invention. The top row of FIG. 2 depicts three splicing segments SS1-SS3 of a 30 Mbps MPEG transport stream 210. The bottom row of FIG. 1 depicts a resulting 270 Mbps SDTI bitstream 220 formed according to the present invention.

[0036] Specifically, with respect to the boundary of the first SS1 and second SS2 splicing segments of the MPEG data stream 210, the Out Point of SS1 is included within frame F6 of the SDTI data stream 220, while the In Point of SS2 is included within frame F7 of the SDTI data stream 220. With respect to the boundary of the second SS2 and third SS3 splicing segments of the MPEG data stream 210, the Out Point of SS2 of is included within frame F10 of the SDTI data stream 220, while the In Point of SS3 is included within frame F11 of the SDTI data stream 220.

[0037] To ensure that frames F6 and F10 of the SDTI data stream 220 are Out Frames, there is no additional data stored in frames F6 or F10 after the Out Points of, respectively, SS1 and SS2. Similarly, to ensure that frames F7 and F11 of the SDTI data stream 220 are In Frames, there is no additional data stored in frames F7 or F11 before the In Points of, respectively, SS2 and SS3.

[0038] The SDTI bitstream data structure of FIG. 2 will allow seamless switching and editing provided that a bitstream switcher or editor knows the particular frame at which to switch or edit. That is, for a bitstream switcher to switch from a “first selected” SDTI stream to a “next selected” SDTI stream in a seamless manner (with respect to the sub-stream), the bitstream switcher must identify the Out Frame of a first selected SDTI bitstream and the In Frame of the next selected bitstream. The resulting switched SDTI bitstream comprises the first selected bitstream of the identified Out Frame followed by the In Frame of the next selected bitstream and the subsequent next selected information frame. In this manner, the information sub-streams will be aligned at the appropriate In Points and Out Points when extracted from the resulting g switched SDTI bitstream. Splice Frame indication will be described in more detail below with respect to Table 1. To properly synchronize sub-streams to be spliced, a temporal alignment may also be required. Those skilled in the art will recognize that several known methods exist for the appropriate buffering of sub-streams or SDTI streams to be spliced.

[0039] FIG. 3 depicts a SDTI bitstream data structure carrying a constrained MPEG information sub-stream according to an embodiment of the invention. The top row 310 of FIG. 3 depicts two splicing segments SS1-SS2 of a 15 Mbps MPEG transport stream 310. The bottom row of FIG. 3 depicts a resulting 270 Mbps SDTI bitstream 320 formed according to the present invention.

[0040] Specifically, since each of the two splicing segments comprise an In Point followed by some data and a terminating Out Point (e.g., an MPEG-like GOP), each may be used to construct an SDTI In/Out Frame as previously discussed. Thus, the entirety of SS1 is incorporated into an SDTI frame 321 and the entirety of SS2 is incorporated into an SDTI frame 322. It must be noted that the payload portion of each In/Out Frame includes only the In Point, data and Out Point of the respective splice segment or GOP.

[0041] The SDTI bitstream data structure of FIG. 3 will allow seamless switching and editing even if a bitstream switcher or editor does not know the particular frame at which to switch or edit. That is, since any SDTI frame boundary separates one sub-stream Out Point from the next sub-stream In Point, the SDTI bitstream switcher may switch at any SDTI frame boundary and still produce a resultant stream that includes an Out Point from a first selected stream followed by an In Point from a next selected stream. Such flexibility is gained at the expense of constraining the information sub-stream to splicing segments that will fit within a single SDTI frame.

[0042] In one embodiment of the invention, portions of multiple sub-streams are included within a single SDTI frame. This is possible where the bandwidth or data carrying capacity of the SDTI stream exceeds the sum of the bandwidth or data carrying capacities of the multiple included sub-streams. For example, on a bandwidth availability basis, it is possible to carry several 30 Mbps MPEG streams within a single 270 Mbps or 360 Mbps SDTI stream.

[0043] Each included sub-stream within an SDTI stream is associated with a unique identifier such that a particular included sub-stream may be examined by, e.g., a “splice aware” switch or other receiving device. Moreover, to the extent that SDTI frames are classified as In Frames, Out Frames and In/Out frames, these classifications are readily adapted to multiple sub-stream alignments. Thus, an In Frame for a first included sub-stream may be, e.g., an Out Frame for a second included sub-stream. Alternatively, if the included sub-streams have sufficiently similar In Point and Out Point locations (e.g., similar GOP structures), then the included sub-streams may be mutually aligned prior to inclusion in the SDTI stream.

[0044] FIG. 4 depicts a bitstream packaging apparatus 400 according to the invention. The bitstream packaging apparatus 400 receives an input bitstream IN, illustratively an MPEG transport stream including splice point indicia as described above with respect to Table 1 and the SMPTE 312M proposed standard. The bitstream packaging apparatus 400 produces a framed output bitstream OUT, illustratively a SMPTE-259 compliant bitstream incorporating the input bitstream IN in a manner such as that described above with respect to FIG. 2 (i.e., SDTI In Frames and Out Frames). If the input bitstream includes splicing segments (e.g., MPEG-like GOPs or segments) or similar data structures that are small enough to fit inside a single SDTI frame, then the output bitstream may incorporate the input bitstream IN in a manner such as that described above with respect to FIG. 3 (i.e., SDTI In/Out Frames). In either case, the bitstream packaging apparatus 400 wraps SDTI information frames around input bitstream data such that input bitstream Out Points are not followed by input bitstream data in the same SDTI frame, and input bitstream In Points are not preceded by input bitstream data in the same SDTI frame.

[0045] The bitstream packaging apparatus 400 of FIG. 4 comprises a write controller 410, a buffer 420, a framing multiplexer 430, a splice detector 440, a read controller 450 and a clock generator 460. The bitstream packaging apparatus 400 of FIG. 4 optionally comprises a second write controller 410′, a second buffer 420′, a second splice detector 440′ and a second read controller 450′.

[0046] The input bitstream IN is coupled to the write controller 410, the buffer 420, and the splice detector 440. Write controller 410 produces a write control signal WC indicative of the presence of a valid input bitstream IN, illustratively an MPEG transport stream including splice In Points and splice Out Points.

[0047] Buffer 420, illustratively a first-in first-out (FIFO) memory, is coupled to receive the input bitstream IN and, in response to the write control signal WC produced by the write controller 410, begins storing the input bitstream IN. Buffer 420, in response to a read control signal RC produced by the read controller 450, begins retrieving the stored input stream IN to produce a buffer output bitstream BOUT. The buffer output stream BOUT is coupled to framing multiplexer 430. Buffer 420 produces a buffer full signal FULL indicative of an overutilization condition within the buffer, such as memory utilization beyond a predetermined level.

[0048] Splice detector 440 monitors the input bitstream IN to identify appropriate splicing points within the input bitstream IN. For example, in the case of an MPEG transport stream, the splice detector 440 may be used to detect splice point indicia such as described above with respect to Table 1 and the SMPTE 312M proposed standard. The splice detector 440 is optionally responsive to a signal SPLICE CRITERIA from an external source (not shown), such as a controller. The criteria defines parameters by which the splice detector may identify In Points and Out Points in a transport stream, elementary stream or packetized elementary stream (PES). That is, the splice detector may be used to identify In Points and Out Points within the elementary stream (or PES) by monitoring various stream parameters and system parameters, such as those in proposed standard SMPTE 312M. In response to the detection or determination of a splice point, illustratively an MPEG In Point or Out Point, splice detector 440 produces a splice detection signal SD that is coupled to read controller 450.

[0049] With respect to In Point and Out Point determination parameters, the first information frame (e.g., video access unit) at an In Point of an MPEG video splicing segment (SS) must be an I-Frame. The second frame should not reference information frames prior to the In Point (i.e., if the second frame is a B-frame, the B-frame should not reference frames prior to the I-frame). The last frame before an Out Point should not be a B-frame (in display order. There may be other constraints placed on the stream to address issues of, e.g., coding error-build-up, tuning-time and minimum picture quality. The identification and use of In Points and Out Points in a splicing arrangement are discussed in more detail in U.S. patent application Ser. No. 08/996,871, filed Dec. 23, 1997 (Attorney Docket 12186A), incorporated herein by reference in its entirety.

[0050] Read controller 450, in response to a frame pulse signal FP produced by the clock generator 460 and the splice detection signal SD produced by the splice detector 440, controls the transfer of data from the buffer 420 to the framing multiplexer 430. The splice detection signal SD indicates whether a particular information frame being stored in the buffer 420 comprises an spliceable frame, such as a frame comprising an In Point or an Out Point.

[0051] The frame pulse signal FP is used to delineate a period of time representing the temporal dimension of an SDTI information frame. Thus, the framing pulse signal FP indicates that a new SDTI frame is being formed in the framing multiplexer 430. As previously discussed, if the buffer 420 then transmits an In Point to the framing multiplexer 430, the resulting frame will comprise an SDTI In Frame. If the SDTI frame is sufficiently large to include the In Point and all the information frames up to and including an Out Point, then the SDTI frame will comprise an In/Out Frame.

[0052] The operation of read controller 450 will be described in more detail below with respect to FIGS. 5 and 6. Briefly, the read controller 450 operates to cause buffer 420 to store, e.g., a portion of a splicing segment, an entire splicing segment or a plurality of splicing segments prior to transmitting the splicing segment(s) to the framing multiplexer 430 as the buffer output stream BOUT. That is, buffer 420 will begin to fill when write controller 410 indicates that the input bitstream IN is a valid bitstream.

[0053] The read controller 450 optionally counts the number of framing pulses (FP) received from the clock generator. By counting the number of framing pulses between, e.g., successive In Frames or successive Out Frames, the read controller 450 can determine if the SDTI stream being formed has an appropriate amount In Frames and Out Frames. That is, the read controller 450 optionally monitors the “frame distance” between successive In Frames or successive Out Frames. If the frame distance exceeds a threshold level, then the read controller 450 adapts the buffer read process to cause the formation of an In Frame or an Out Frame.

[0054] In another embodiment of the invention, the buffer 420 is continuously filled by the input stream IN, illustratively a continuously received MPEG transport stream. Thus, the buffer utilization must be carefully managed to ensure that SDTI frames are appropriately formed without losing data due to, e.g., a buffer overflow condition. A bit level approach to such buffer management is discussed in more detail below with respect to FIGS. 8A and 8B.

[0055] In response to the splice detection signal SD indicating that an In Point has been detected, read controller 450 causes output from the buffer 420 to stop immediately prior to the In Point (i.e., the In Point is stored in the output position of a FIFO memory). Information frames following the In Point are stored in the buffer 420 in memory locations following the In Point memory location.

[0056] In response to a framing pulse FP indicating that a new SDTI frame is being formed, read controller 450 causes buffer 420 to begin transmitting the stored information frames, starting with the In Point and continuing until an Out Point is reached. Read controller 450 causes buffer 420 to stop transmitting stored information frames immediately upon the transmission of an Out Point. Thus, by beginning transmission at an In Point, the SDTI frame receiving the In Point becomes an In Frame. Similarly, by terminating transmission at an Out Point, the SDTI frame receiving the Out Point becomes an Out Frame. In the case of an SDTI frame receiving both an In Point and an Out Point, the SDTI frame becomes an In/Out Frame.

[0057] Read controller 450 controls the retrieval and transmission operations of buffer 420 via the read control signal RC. It must be noted that in response to overutilization of buffer 420, as indicated by the buffer fullness signal FULL, read controller 450 will cause the buffer to retrieve and transmit stored information frames at least until the buffer utilization level is sufficiently reduced. During such an overutilization response period, the alignment of information frames by the framing multiplexer may be incorrect in that In Points may be preceded by data within the same SDTI frame and Out Point may be followed by data within the same SDTI frame. While SDTI information frames formed with such incorrect alignment will not be seamlessly spliceable, the information sub-stream will not have been corrupted. Thus, unless a splice occurs at a misaligned SDTI information frame, the result of the misalignment will not be noticeable.

[0058] Read controller 450 produces a splice marker control signal SMC that indicates whether a particular information frame transmitted to the frame multiplexer 430 comprises an In Point or an Out Point. For example, a splicing segment transmitted to the framing multiplexer 430 may comprise an In Point, followed by a number of non-spliceable information frames (possibly including additional In Points) and a terminating Out Point frame. The status of all these frames, or at least the In Point and Out Point frames, is indicated by the splice marker control signal SMC.

[0059] Clock generator 460 produces a framing clock signal FC and the frame pulse signal FP. The framing clock signal FC is used as a data clock for the formation and transmission of SDTI information frames. As previously described, the frame pulse signal FP is used to delineate a period of time representing a temporal dimension of an SDTI information frame. Thus, the frame pulse signal FP is used to indicate the start of a new SDTI information frame. The time between each frame pulse signal SD is constant in the case of SDTI information frames, based on the fixed block nature of the SDTI information frame being formed ba the frame multiplexer 430. However, in the case of an SDTI-like information stream having a variable length block size, the frame pulse signal may be adapted to indicate such a variable length block size.

[0060] In a station or studio environment, it may be desirable to lock the framing clock signal FC and frame pulse signal FP to a studio genlock source. Thus, clock generator 460 optionally receives and locks to such a genlock signal in a known manner (not shown).

[0061] Framing multiplexer 430, in response to the framing clock signal FC produced by the clock generator 460, multiplexes the buffer output stream BOUT into a framed output bitstream, illustratively a SMPTE 305 bitstream (i.e., SDTI bitstream) having a data structure as described above with respect to FIGS. 2 or 3. Specifically, the framing multiplexer 430 generates a stream of SDTI information frames at a rate determined by the framing clock signal FC. Each of the SDTI information frames has a header portion and a payload portion. If the buffer 420 transmits data during the formation of an SDTI frame, the framing multiplexer 430 incorporates that data into the payload portion of the SDTI frame being formed.

[0062] The header portion of an SDTI frame being formed is optionally adjusted in response to the splice marker control signal SMC, which indicates whether a particular information frame provided by the buffer 420 comprises an In Point or an Out Point. If the first information frame stored in the payload portion of an SDTI frame comprises an In point, as indicated by the splice marker control signal SMC, then the SDTI frame is an In Frame. If the last information frame stored in the payload portion of an SDTI frame comprises an Out point, as indicated by the splice marker control signal SMC, then the SDTI frame is an Out Frame. If the first information frame stored in the payload portion of an SDTI frame comprises an In point and the last information frame stored in the payload portion of the SDTI frame comprises an Out point, then the SDTI frame is an In/Out Frame. The framing multiplexer optionally indicates that a particular SDTI frame is an In Frame, Out Frame or In/Out Frame using one of several techniques, which will now be described.

[0063] To properly splice or switch an SDTI bitstream, it is desirable to provide splice point indicative syntax within the SDTI bitstream so that the SDTI splicing or switching device may splice or switch the SDTI bitstream at the appropriate point. As previously discussed, an “In Frame” means that the first part of the sub-stream data contained in the frame is an In Point; an “Out Frame” means that the last part of the sub-stream data contained in the frame is an Out Point; and an “In/Out Frame” means that both the first part of the sub-stream data contained in the frame is an In Point and the last part of the sub-stream data contained in the frame is an Out Point.

[0064] The SMPTE 305M provides for an SDTI bitstream that supports the transport of many forms of user data, including user data comprising fixed block sizes or variable block sizes. Therefore, the SDTI syntax indicative of splice points may be accommodated at several levels, depending upon the type of user data being transported. Specifically, SDTI splice point syntax may be included in the SDTI header, as a new SDTI Data Type, or as an attribute of the User Data Fixed block segment or User Data Variable Block segment.

[0065] In one embodiment of the invention, SDTI splice points are indicated to a SMPTE 259 switch by incorporating SDTI splice point indicative syntax in the header portion of SDTI information frames. Specifically, syntax within the header portion of each SDTI frame is used to indicate if the respective frame is an In Frame, an Out Frame or an In/Out Frame. Moreover, additional syntax is optionally utilized to indicate, e.g., a splice coding delay required for seamless splicing of the SDTI bitstream. In this embodiment, In Frames and Out Frames are indicated to a SMPTE 259 switch by utilizing the first byte of the five byte Header expansion reserved data field a splice_point_marker byte. The splice_point_marker byte is examined by an SDTI splicing or switching device prior to splicing or switching the SDTI stream. Table 1 depicts an exemplary usage of the splice_point_marker byte. Optionally, the splice_point_marker information is carried in the payload portion of an SDTI frame.

[0066] In another embodiment of the invention, SDTI splice points are indicated to a SMPTE 259/305 switch by the use of a new data type within the SDTI Data Type Syntax. For example, a first Data Type code (e.g., 253h) may be used to indicate that an information sub-stream comprises an MPEG-2 transport stream. A second Data Type code (e.g., 263h) may be used to indicate that an information sub-stream comprises an MPEG-2 transport stream and that the particular SDTI frame comprises an In Frame. A third Data Type code (e.g., 264h) may be used to indicate that an information sub-stream comprises an MPEG-2 transport stream and that the particular SDTI frame comprises an Out Frame. This approach of simultaneously indicating information sub-stream data type and SDTI frame type may be readily adapted to all other compressed and uncompressed data representations carried in an SDTI bitstream.

[0067] In another embodiment of the invention, SDTI splice points are indicated to a SMPTE 259/305 switch by modifying the interpretation of the User Data Formats for Fixed or Variable Blocks. The new Data Type Syntax utilizes an additional field immediately following the Type code in the User Data Fixed/Variable Blocks. A splice point is indicated to a SMPTE 259/305 switch by defining such a byte as shown previously.

[0068] The relatively high bitrate framed information stream, illustratively an SDTI stream, is used to package one or more relatively low bitrate framed information streams, illustratively one or more MPEG transport and/or elementary streams. The packaging process optionally forms SDTI frames including one or more MPEG information frames. Specifically, an SDTI frame may include a single MPEG frame, a plurality of MPEG frames comprising a single group of pictures (GOP) or any number of frames depending upon the relative sizes of the SDTI and MPEG frames.

[0069] For the purpose of easing subsequent splicing of the resulting SDTI stream, it is important to form SDTI In Frames and Out Frames at a regular interval. Thus, in one embodiment of the invention, after a predetermined number of SDTI frames have been formed without the formation of an Out Frame, retrieval of information from the buffer is halted immediately after the next Out Point within the relatively low bitrate information stream is sent to the framing multiplexer. Upon receiving the next framing pulse, buffer retrieval is resumed. In this manner, that last Out Point causes the formation of an Out Frame since it will be the last sub-stream information component stored in the payload portion of the SDTI frame (i.e., the “terminal” payload frame). Ideally, the Out Point used to form the Out Frame is followed by an In Point. However, since the purpose of forming the Out Frame is to leave a stream at an appropriate point, the frames immediately following the Out Frame are probably not used anyway.

[0070] Similarly, after a predetermined number of SDTI frames have been formed without the formation of an In Frame, retrieval of information from the buffer is halted immediately before the next In Point within the relatively low bitrate information stream is sent to the framing multiplexer. Upon receiving the next framing pulse, buffer retrieval is resumed. Thus, the In Point will be the first frame stored in the payload portion of the SDTI frame (i.e., the “initial” payload frame). In this manner, that In Point will cause the formation of an In Frame. Ideally, the In Point used to form the Out Frame is preceded by an Out Point. However, since the purpose of forming the In Frame is to enter a stream at an appropriate point, the frames immediately preceding the In Frame are probably not used anyway.

[0071] The predetermined number of frames between Out Frame or In Frames is determined with respect to the particular splicing application. For example, in a studio switching or routing application a great deal of control may be desired such that frequent In Frames and Out Frames are necessary. In a less demanding application, fewer In Frames and Out Frames are necessary. The predetermined number of frames may be calculated with respect to the frame rate of the relatively high bitrate information stream used and the maximum time allowed to implement a stream switch or splice operation.

[0072] Referring now to a multiple input stream embodiment of the invention. FIG. 4 discloses optional second write controller 410′, second buffer 420′, second splice detector 440′ and second read controller 450′ operate in substantially the same manner as previously described with respect to the write controller 410, buffer 420, splice detector 440 and read controller 450. The purpose of these optional components is to package a second input signal IN′ along with the first input signal IN.

[0073] In this embodiment each input stream IN and IN′ includes a unique identification indicium, such as a stream id (SID) or program id (PID) code. The stream id is usually located in a header portion of the stream, though the exact type and location of the id is not critical. Regardless of the stream id scheme used, framing multiplexer 430 utilizes the id to package the first buffer output bitstream BOUT and the second buffer output bitstream BOUT′. Moreover, as previously discussed, multiple stream packaging results in a plurality of In Frame, Out Frame and In/Out Frame depending upon the contents of a particular frame. Specifically, an Out Frame for buffer output bitstream BOUT may actually be an In Frame for buffer output bitstream BOUT′. Additionally, the second splice marker control signal SMC′ is used to define information appropriate to the second buffer output bitstream BOUT′.

[0074] FIG. 5 depicts a controller suitable for use in the bitstream packaging apparatus of FIG. 4. Specifically, FIG. 5 depicts a read controller 450 suitable for use as the read controller 450 of the bitstream packaging apparatus of FIG. 4. Optionally, the read controller 450 of FIG. 5 may additionally perform the functions allocated to the write controller 410 of FIG. 4.

[0075] The read controller 450 contains a microprocessor 454 as well as memory 458 for storing a buffer management routine 600. The microprocessor 454 cooperates with conventional support circuitry 456 such as power supplies, clock circuits, cache memory and the like as well as circuits that assist in executing the software routines. As such, it is contemplated that some of the process steps discussed herein as software processes may be implemented within hardware, e.g., as circuitry that cooperates with the microprocessor 454 to perform various steps. The read controller 450 also contains input/output circuitry 452 that forms an interface between the splice detector 440, buffer 420, framing multiplexer 430 and clock generator 460 of the bitstream packaging apparatus 400 of FIG. 4. Although the read controller 450 is depicted as a general purpose computer that is programmed to perform buffer management functions, and, optionally input stream IN verification functions in accordance with the present invention, the invention can be implemented in hardware as an application specific integrated circuit (ASIC). As such, the process steps described herein are intended to be broadly interpreted as being equivalently performed by software, hardware, or a combination thereof and can be stored in computer-readable media, such as random access memory, magnetic or optical disks or drives.

[0076] The read controller 450 of the present invention executes a buffer management routine 600 that is used to temporally align information frames comprising In Points and Out Points of the input bitstream IN according to the frame pulse signal FP. The buffer management routine 600 causes information frames to be provided to the framing multiplexer 430 in a manner facilitating SDTI packaging of the information frames as an SDTI information sub-stream including appropriate splicing indicia so that subsequent splicing operations may be performed in a seamless manner.

[0077] Data interleaving is a known technique used to make a data stream more resistant to “burst errors,” which are periods where one or more sequential bits, bytes or other data structures in a sequence of bits, bytes or other data structures are corrupted. A data interleaving algorithm rearranges the bits, bytes or other data structures in a manner that converts a sequence of errors into a plurality of individual errors. The individual errors are more readily corrected using, e.g., forward error correction techniques. Data interleaving is commonly used to store data in storage media prone to sequential errors, such as magnetic tape.

[0078] In one embodiment of the invention, interleaved sub-stream data (e.g., MPEG transport or elementary streams stored on magnetic tape) is further constrained in that no block of data to be interleaved is allowed to contain data from both before and after a given splice point (In Point or Out Point). That is, while portions of a sub-stream delineated by an In Point and Out Point may include interleaved data, the reconstruction of the interleaved data does not require data from outside the delineated portion. In this manner, the relatively seamless splicing of SDTI streams including interleaved sub-streams is achieved.

[0079] FIG. 6 depicts a flow diagram of a buffer management routine 600A according to the invention and suitable for use in the SDTI bitstream packaging apparatus of FIG. 4 and the controller of FIG. 5. FIG. 6 also depicts a flow diagram of a framing routine 600B according to the invention and suitable for use in the SDTI bitstream packaging apparatus of FIG. 4. The buffer management routine 600A and the framing routine 600B will be described together to show the timing relationships of the respective routines. Moreover, though not shown explicitly, in the flow chart, the buffer 420 is continually receiving data from the input bitstream IN under the control of, e.g., the write controller 410.

[0080] The buffer management routine 600A is entered at step 605 and proceeds to step 610, where a query is made as to whether a new frame pulse FP has been received. As previously discussed, the frame pulse FP indicates that a new output frame, e.g., an SDTI information frame, is being formed by the framing multiplexer 430.

[0081] If the query at step 610 is answered affirmatively, then the routine 600A proceeds to step 620, where the read controller 450 causes buffer 420 to begin transmitting stored information frames, starting with (ideally) an In Point and continuing until an Out Point is reached. The read controller 450 also provides a splice marker control SMC signal that indicates if a transmitted information frame includes an In Point or an Out Point. The read controller 450 causes buffer 420 to stop transmitting stored information frames immediately upon the transmission of an Out Point. The routine 600A then proceeds to step 610 to wait for a new framing pulse FP. Since an Out Point should be followed by an In Point, the buffer 420 stores the In Point and the information frames following the In Point.

[0082] If the query at step 610 is answered negatively, then the routine 600A proceeds to step 615, where a query is made as to whether a buffer overutilization condition exists. If the query at step 615 is answered negatively, then the routine 600A proceeds to step 610. If the query at step 615 is answered affirmatively, then the routine 600A proceeds to step 625, where the read controller 450 causes buffer 420 to begin transmitting stored information frames and the associated splice marker control SMC signal. The read controller 450 causes buffer 420 to stop transmitting stored information frames immediately upon the transmission of an Out Point, or immediately prior to the next In Point or upon transmitting a predetermined number of information frames. The routine 600A then proceeds to step 610 to wait for a new framing pulse FP.

[0083] The frame multiplexer 430 operates according to the framing routine 600B of FIG. 6. Specifically, the frame multiplexer 430 continually forms information frames, e.g., SDTI information frames in response to the framing clock signal FC. Any information frames received from the buffer 420 are incorporated into the payload portion of an SDTI information frame being formed, along with appropriate splicing indicia.

[0084] The framing routine 600B is entered at step 650 when, as indicated by the dotted lines from steps 620 and 625, information frames and associated splice marker control SMC signals are received. The routine 600B then proceeds to step 655, where the received information frames are incorporated into the payload portion of an SDTI information frame being formed.

[0085] The routine 600B then proceeds to step 660 where a query is made as to whether the splice marker control SMC signal indicates that a received information frame includes an In Point or an Out Point. If the query is answered negatively, then the routine 600B proceeds to step 655.

[0086] If the query is answered affirmatively, then the routine 600B proceeds to step 665, where indicia of the In Point or Out Point is included within the SDTI header according to one of the splice indicia syntax rules previously described (e.g., the syntax described in Table 1). The routine 600B then proceeds to step 655.

[0087] FIG. 7A is a high level block diagram of an SDTI bitstream switching apparatus 700A suitable for switching between SDTI bitstreams having a data structure according to FIG. 3. Specifically, bitstream switching apparatus 700A comprises a switch controller 710A and a switch 720.

[0088] Switch 720 is coupled to receive a first bitstream SDTI A at a first input I1 and a second bitstream SDTI B at a second input 12. Switch 720, in response to a switch control signal C, couples either the first bitstream SDTI A or the second bitstream SDTI B to an output OUT.

[0089] Switch controller 710A generates the switch control signal C in response to a switch command signal SC and a frame timing pulse FT. The switch command signal is a signal indicative of a present need to switch bitstreams (e.g., a switch feed signal from a studio control console). The frame timing pulse FT is indicative of a frame boundary (such as an SDTI frame boundary, a vertical timing interval and the like). Thus, switch controller 710A will only cause a switching operation at an appropriate frame boundary.

[0090] Bitstream switching apparatus 700A may be defined as a “splice unaware” switching apparatus since it does not utilize any of the previously discussed splice point indicia included in, e.g., the SDTI bitstream, or a sub-stream within the SDTI bitstream or it does not examine the sub-stream to identify splice point indicia or, more generally, suitable sub-stream entrance and exit points. Thus, to guarantee a seamless splicing or switching between information sub-streams of, e.g., the first bitstream SDTI A and the second bitstream SDTI B, it is necessary for these SDTI streams to be constructed using the data structure defined in FIG. 3. Specifically, the first bitstream SDTI A and the second bitstream SDTI B must comprise only In/Out Frames. In this manner a first-selected SDTI stream will always be exited at an information sub-stream Out Point, while a next-selected SDTI stream will always be entered at an information sub-stream In Point.

[0091] FIG. 7B is a high level block diagram of an SDTI bitstream switching apparatus 700B suitable for switching between SDTI bitstreams having a data structure according to FIG. 2 or FIG. 3. Specifically, bitstream switching apparatus 700B comprises a switch controller 710B, a switch 720 and a splice detector 730. The switch 720 operates in the same manner as previously described with respect to FIG. 7A.

[0092] Splice detector 730 is coupled to receive the first bitstream SDTI A and the second bitstream SDTI B. The splice detector 730 scans the received bitstreams for splicing indicia and produces an output signal S indicative of identified splice point indicia within the bitstreams. Specifically, the splice detector 730 examines the header of each received SDTI frame to determine if In Frame, Out Frame or In/Out Frame syntax or other indicia is present. In an alternate embodiment, the splice detector 730 examines the header of each received SDTI information sub-stream frame to determine if a data type indicative of an In Frame, Out Frame or In/Out Frame is present. In another alternate embodiment, the splice detector 730 examines the header of each received SDTI information sub-stream frame to determine if In Point or Out Point syntax or other indicia is present. For example, in the case of a sub-stream comprising an MPEG-2 transport stream, a splice-aware SMPTE 259 switch examining splice-countdown field within the header portion of an MPEG-2 transport stream frame may readily determine, in a known manner, if a splice at the particular MPEG-2 frame will be seamless.

[0093] In addition to indicating the presence of a splice point within one or both of the bitstreams, the splice detector 730 also forwards to the switch controller any identified timing or delay information relating the identified splice points. The splice detector 730 may also be used to examine the bitstream at the elementary stream (or PES) level to identify splicing In Points and/or Out Points. The criteria for such an examination SPLICE CRITERIA may be received from an external source, such as the splice controller (not shown). This results of the examination may also be forwarded to the switch controller.

[0094] Switch controller 710B generates the switch control signal C in response to the switch command signal SC, the frame timing pulse FT and the splice detection signal S. If the splice detection signal indicates that a switch or splice operation must be delayed by some number of seconds or frames, such as indicated in the syntax of Table 1, then the switch controller 710B delays switching until the appropriate delay or frame count has occurred.

[0095] Bitstream switching apparatus 700B may be defined as a “splice aware” switching apparatus since it utilizes any of the previously discussed splice point indicia include in, e.g., the SDTI bitstream or a sub-stream within the SDTI bitstream. Thus, to guarantee a seamless splicing or switching between information sub-streams of, e.g., the first bitstream-SDTI A and the second bitstream SDTI B, it is only necessary for these SDTI streams to be constructed using the data structure defined in FIG. 2, rather than the more constrained data structure defined in FIG. 3.

[0096] FIG. 8A depicts a flow diagram of a buffer write routine 800A according to the invention and suitable for use in the SDTI bitstream packaging apparatus of FIG. 4 and the controller of FIG. 5. The routine 800A is entered at step 801 and proceeds to step 802, where a bit from an information sub-stream (such as IN or IN′ of FIG. 4) is written into a buffer (such as buffer 420 or 420′ of FIG. 4). The routine 800A then proceeds to step 803, where a query is made as to whether the data is indicative of a splice point. If the query at step 803 is answered affirmatively, then the routine 800A proceeds to step 804, where a splice point indicator is set. The routine 800A then proceeds to step 802. If the query at step 803 is answered negatively, then the routine 800A proceeds directly to step 802.

[0097] FIG. 8B depicts a flow diagram of a buffer read routine 800B according to the invention and suitable for use in the SDTI bitstream packaging apparatus of FIG. 4 and the controller of FIG. 5. Specifically, the buffer read routine 800B controls, at a bit level, the data output operation (i.e., read process) of a buffer (such as buffer 420 or 420′ of FIG. 4) associated with a particular input stream (such as IN or IN′ of FIG. 4). Data is written to the buffer as it becomes available form buffer is normally filled by data. The buffer read routine 800B includes within an output bitstream information that indicates to an SDTI frame multiplexer (or packaging unit) which SDTI frames formed with information from the buffer will be In Frames, which will be Out Frames and which will be In/Out Frames. The buffer read routine 800B also adapts the output data flow to buffer overutilization conditions.

[0098] The buffer read routine 800B is entered at step 805 and proceeds to step 810, where several variables are initialized. Specifically, a variable ID is set equal to a parameter STREAM_ID; a variable READ is set equal to one; a variable IN[ID] is set equal to zero; and a variable OUT[ID] is set equal to zero. The parameter STREAM_ID is indicative of a stream identification for a particular information stream being processed. For example, in the case of processing multiple information stream, each information stream will be associated with a unique stream identification, as previously described. The buffer read routine 800B utilizes the ID to manipulate the variables IN[ID] and OUT[ID], which are used to indicate if an SDTI frame being formed will be an In Frame (IN[I]=1), an Out Frame (OUT[I]=1) or an In/Out Frame (IN[I]=OUT[I]=1). In this manner, multiple sub-streams may be packaged within, e.g., a single SDTI stream such that each single SDTI frame may comprise an In Frame, Out Frame or In/Out Frame as necessary to accommodate each of the packaged sub-streams. This is an extremely useful and efficient method that allows for maximal utilization of the bandwidth in the SDTI stream. The routine 800B then proceeds to step 815.

[0099] At step 815, a query is made as to whether an In Point is present at the output of the buffer, e.g., the buffer associated with the sub-stream identified by the variable ID. If the query at step 815 is answered affirmatively, then the routine proceeds to step 820 where the variable READ is set equal to zero, and the variable IN[ID] is set equal to one. The routine 800B then proceeds to step 825. If the query at step 815 is answered negatively, then the routine 800B proceeds directly to step 825.

[0100] At step 825, a query is made as to whether an Out Point was just retrieved from the buffer output. If the query at step 825 is answered affirmatively, then the routine proceeds to step 830, where the variable READ is set equal to zero and the OUT_Iis set equal to one. The routine 800B then proceeds to step 835. If the query at step 825 is answered negatively, then the routine 800B proceeds directly to step 835.

[0101] At step 835, a query is made as to whether the buffer, e.g., the buffer associated with the sub-stream identified by the variable ID, is over utilized (i.e., approaching an overflow condition). If the query at step 835 is answered affirmatively, then the routine 800B proceeds to step 840 where the variable READ is set equal to one. The routine 800B then proceeds to step 845. If the query at step 835 is answered negatively, then the routine proceeds directly to step 845.

[0102] At step 845, a query is made as to whether a new SDTI frame is starting. The start of a new SDTI frame may be sensed via, e.g., the frame pulse FP condition previously described with respect to SDTI framing unit of FIG. 4. If the query at step 845 is answered affirmatively, then the routine 800B proceeds to step 850, where the READ variable is set equal to one. Additionally, a splice marker control (SMC) flag is set equal to the previous IN[ID] value logically ORed with the present OUT[ID] value and shifted left by one bit position. Additionally, the previous IN[ID] value is set equal to the present IN[ID] variable. The routine 800B then proceeds to step 855, where the splice marker control data is inserted at the end of the SDTI frame presently being formed. The routine 800B then proceeds to step 860. If the query at step 845 is answered negatively, then the routine 800B proceeds directly to step 860.

[0103] At step 860, a query is made as to whether the variable READ is equal to one. If the query at step 860 is answered affirmatively, then the routine 800B proceeds to step 865, where the next output bit is read from the buffer. The routine then proceeds to step 815. If the query at step 860 is answered negatively, then the routine proceeds directly to step 815.

[0104] With the teaching of the above disclosure, it will now be apparent to one skilled in the art that one or more frame delineated or segmented information streams may be included as a sub-streams within a relatively higher bitrate, frame delineated or segmented information stream. In this manner, high bitrate communications systems and protocols, such as the above-described Serial Data Transport Interface (SDTI) standard SMPTE 259 (and the related SMPTE 305M), may be advantageously utilized to transport relatively low bitrate information streams while preserving an ability to properly splice sub-streams.

[0105] Although the above disclosure generally describes a novel apparatus and method for synchronizing one or more lower bitrate sub-streams (e.g., MPEG transport streams) within a higher bitrate frame delineated information stream, the above method can also be extended for synchronizing elementary streams (e.g., audio and video elementary streams) within the lower bitrate sub-streams. Namely, information stream switching within the studio is presently accomplished at a frame synchronous level in which the switching operation occurs between two video streams at a frame boundary (e.g., the vertical blanking interval). Frames are synchronized with one another at a central routing switch to ensure that their vertical blanking intervals align. The transport of spliceable MPEG compressed bitstreams throughout the studio and their distinctive characteristics necessitate that a special accommodation be made to switch between them without corrupting/losing audio and video packets.

[0106] More specifically, the architects of SMPTE-305M have proposed a method of carrying MPEG transport streams (ATSC and DVB transport streams as a legal subset of MPEG transport streams fall into this category). However, as noted above, these proposals do not consider how to switch MPEG streams which is a difficult process when attempting to comply with the requirement noted earlier, i.e., that SMPTE-259 presently only defines switching at NTSC or PAL frame boundaries. As discussed above, seamless switching of video contained within the MPEG-2 transport streams can be achieved at SMPTE-259 frame boundaries when the MPEG-2 Transport Stream is being carried as SDTI payload. However, when the sub-streams (MPEG transport streams) carry both compressed video and audio elementary streams, then an additional complexity is introduced into the present synchronization method.

[0107] To illustrate, FIG. 9 illustrates a sub-stream 900, e.g., an MPEG transport stream, carrying two temporally offset elementary streams, e.g., audio 910 and video 920 elementary streams. It should be noted that elementary stream 910 is temporally delayed when compared to elementary stream 920 and this delay may vary over time. However, it should be noted that the gaps shown within each of the audio and video streams are only illustrative for the purpose of showing the relative timing offset between the audio and video streams. In other words, these gaps do not exist within each of the elementary streams.

[0108] Namely, an MPEG compressed bitstream that multiplexes both audio and video elementary streams will necessarily have the video lead the audio. This delay occurs as a result of the buffer requirements for the video and audio and the relationship between these as defined by the MPEG-2 Systems specification. The amount of this delay is likewise defined by these buffer requirements. This delay is illustrated in FIG. 9, that shows a single program MPEG transport stream containing multiplexed audio and video packets. In FIG. 9, a video elementary stream 920 is multiplexed with its associated audio elementary stream 910 and other program specific information as defined in the MPEG specification to provide a single transport stream 900. The first audio packet will be delayed from the video according to the buffer limitations in the decoder, e.g., for the Grand Alliance A/53 interface thin delay is about 200 milliseconds.

[0109] A spliceable MPEG compressed bitstream will be further constrained so that the start of the bitstream corresponds to a splice “In Point” and the end of the bitstream corresponds to a legal “Out Point” as discussed above. The first video packet in the transport stream 900 will therefore contain a picture start (among other constraints) and the last have a splice countdown=0 (among other constraints). The audio associated with this video (i.e., with presentation time stamps corresponding to the video) will be delayed within the stream by the amount specified by the buffer sizes. This causes an overlap between packets from an “old” and “new” stream when splicing.

[0110] FIG. 10 illustrates an MPEG transport stream 1000 having spliceable segments than can be transported in a frame synchronous environment. Unfortunately, FIG. 10 illustrates the video-lead-audio characteristic of the sub-stream, where gaps 1030 exist within the video. The embodiments described below are tailored to effect the removal of these gaps or minimization of the size of these gaps (if for some reasons these gaps are desirable for other purposes).

[0111] In FIG. 10, the video 1020 and audio 1010 components of the transport stream 1000 have been placed one above the other for illustrative purposes. In general, there is no requirement for exactly one splice segment to fit within a frame boundary, but instead this will be a function of the data rates. For example, the ratio between the GA A/53 transmission data rate of 19.4 Mb/s and the serial bit rate of the SMPTE 259 D frame switch at 270 Mb/s is about 14:1. Thus, on average, each synchronous frame could contain 14 frames at the compressed bit-rate. Thus, the gaps 1030 as shown in FIG. 10 should not be interpreted to occur uniformly between every MPEG frame, since there is no requirement that exactly one splice segment is to fit within a frame boundary. However, the gaps 1030 will occur at some points within the SDTI information stream, e.g., between successive SDTI frames or at the end of a group of SDTI frames.

[0112] Although the present invention is described illustratively below using a transport stream, it should be noted that this invention is not so limited and encompasses other stream format, e.g., PES streams, program streams and the likes. Furthermore, although the present invention is described illustratively below using two elementary streams (video and audio) that contain a temporal offset, it should be noted that elementary streams, e.g., data streams may be employed as well. For example, there may be a temporal offset between a video elementary stream and its associated data stream, e.g., “closed captioning” data stream that can be addressed in accordance with the methods described below.

[0113] Two embodiments for providing video/audio alignment in real time switching between frame synchronous boundaries are described below. First, FIG. 11 illustrates an SDTI bitstream switching apparatus suitable for switching SDTI bitstreams carrying sub-streams that, in turn, carry temporally offset elementary streams.

[0114] More specifically, FIG. 11 illustrates an SDTI bitstream switching apparatus 1100 having a splice aware bitstream framing multiplexer 1110, a frame switcher 1120 and a splice aware audio/video aligner 1130. Namely, splice aware bitstream framing multiplexer 1110 is the bitstream packaging apparatus 400 and frame switcher 1120 is the switching apparatus 700A or 700B as discussed above. Since these devices perform the same functions as those above, the descriptions for these devices are identical to the discussion above.

[0115] It should be noted that FIG. 11 illustrates an approach to audio/video alignment where the alignment occurs on the receiver side, i.e., receiver audio/video realignment. In this embodiment, the Splice Aware Bitstream Framing Mux 1110 accepts as input a sub-stream containing both audio and video (such as a single program transport stream) and produces SDTI frames that are frame synchronous in accordance with SMPTE-259. These streams are then transported through a SMPTE-259 switcher 1120 to the Splice Aware Audio/Video Aligner 1130. The Splice Aware Audio/Video Aligner 1130 serves to align the temporally offset elementary streams of the sub-streams carried within the SDTI information streams.

[0116] FIG. 12 illustrates a detailed block diagram of the Splice Aware Audio/Video Aligner 1130 of the present invention. The Splice Aware Audio/Video Aligner 1130 comprises a switch 1210, a switch control 1220, two buffers 1230 and 1240, a multiplexer 1250 and a clock generator 1260.

[0117] The operation of the Splice Aware Audio/Video Aligner 1130 is best understood by assuming that in two consecutive frames, the frame switcher 1120 will be directing synchronized compressed audio/video bitstreams on path 1205 to the Splice Aware Audio/Video Aligner 1130 and that these streams are to be combined to provide a single output bitstream on path 1270 that contains synchronized audio and video. Namely, it is assumed for the discussion below that gaps 1030 exist between the two consecutive input SDTI frames. However, in the event that gaps 1030 do not exist between consecutive input SDTI frames, the switching between the two buffers as described below will only occur when the gaps 1030 are detected in an SDTI frame.

[0118] Specifically, the switch control 1220 directs the first frame of the framed bitstream on path 1205 to one of two buffers, e.g., 1230. After a period equal to the audio delay has elapsed, the buffered bitstream, is read serially from the buffer 1230 (e.g., under the control of a read controller (not shown) and/or clock generator 1260), and passes through the transport multiplexer or output multiplexer 1250, and is clocked out in accordance with clock generator 1260 as the output MPEG transport stream on path 1270. Concurrently, as the buffer 1230 is being emptied, the switch control 1220 directs the next SDTI frame into the second buffer, e.g., 1240. Once the entire SDTI frame has been received, the transport multiplexer 1250 is switched to receive video packets from the second buffer 1240 (which will initially contain no audio) and the residual audio frames from the first buffer 1230 (which will now contain no video). During this period the first buffer 1230 may again be filled with the third SDTI frame (only if the third SDTI frame contains gaps 1030 relative to the second SDTI frame) and so on. This method is then repeated until the synchronized audio video sequence is complete. It should be noted that this process introduces a delay on the “Bitstream Out” on path 1270 that equals to one SDTI frame plus the audio delay time or temporal offset between the two elementary streams.

[0119] To summarize, the present Splice Aware Audio/Video Aligner 1130 employs a double buffer architecture at the receiver end, so that the new frame bitstream input can be buffered into one buffer while the old frame bitstream is drained from the other buffer. To provide seamless splicing of audio, the video frames from the new bitstream will be multiplexed with the audio frames of the old video stream during the switch from one stream to another.

[0120] Alternatively, in a second embodiment, audio/video alignment is achieved instead by realigning the audio with the video prior to its delivery over the frame synchronous system. Namely, the delay or gaps 1030 in the audio elementary stream is removed with respect to the video elementary stream when the SDTI frame is generated. This means that the audio and video are in the same SDTI frame as generated above in accordance with FIG. 4. In other words, the audio is not delayed with respect to the video by approximately 200 milliseconds, but instead, it is aligned and transported with the corresponding video frames within an SDTI frame. This makes the task of synchronizing the audio and video less complex since any given SDTI frame contains both the audio and corresponding video. Synchronization buffers for MPEG Transport input and output are required to align the audio packets with the corresponding video packets prior to switching. Namely, the SDTI bitstream packaging apparatus 400 includes an additional buffer 420a. Namely, the additional buffer 420ais used to removed the gaps or temporal offset between the two elementary streams, e.g., by delaying the video. However, the audio must be re-delayed at some point, e.g., at the receiver end, when the bitstreams are to be redelivered as compliant transport streams.

[0121] Although various embodiments which incorporate the teachings of the present invention have been shown and described in detail herein, those skilled in the art can readily devise many other varied embodiments that still incorporate these teachings.