Method and apparatus for gain control in a CMOS low noise amplifier

[0002] This invention relates to Complementary Metal Oxide Semiconductor (CMOS) low noise amplifiers (LNA).

[0003] One of the key building blocks of a conventional RF transceiver is a Low Noise Amplifier (LNA). FIG. 1 shows an implementation of a CMOS LNA high gain path 200 commonly adopted in conventional RF transceivers. The gain of this amplifier can be expressed as:

[0004] A_v=g_m·Q²·R_pwhere gm is the transconductance of the input device, Q is the quality factor of the load inductor and R_pis the parasitic resistance associated with the inductor.

[0005] Referring to the equation above, the gain is a strong function of gm of the input transistor, as well as the Q of the inductor of the LNA. gm may vary +/−30-40%, and the Q²R_pterm typically varies +/−10-20% due to process, temperature etc. variation. As a result, the gain of the LNA can easily vary by greater than 6 dB. This gain variation may affect receiver performance significantly in real life applications and hence, the implementation may not be desirable.

[0006] An amplifier comprising a Low Noise Amplifier (LNA) to amplify a Radio Frequency (RF) signal. The gain of the LNA varying as a function of changes in the process and environmental conditions. A bias assembly to generate a bias current to bias the LNA input stage. The bias assembly configured to reduce the variation of the LNA gain due to changes in process variations and environmental conditions.

[0007] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.

[0008] FIG. 1 is a block diagram of a conventional LNA.

[0009] FIG. 2 is a block diagram of an aspect of a transceiver.

[0010] FIG. 3 is a block diagram of an aspect of an amplifier for amplifying an RF signal.

[0011] FIG. 4 is a block diagram of an aspect of an LNA biasing scheme.

[0012] FIG. 5 is a detailed schematic diagram of an aspect of several bias impedance configurations.

[0013] FIG. 6 is a detailed schematic diagram of an aspect of a bias circuit for an LNA.

[0014] FIG. 7 is a flow diagram of an aspect of generating a bias current for an LNA.

[0015] Like reference symbols in the various drawings indicate like elements.

[0016] FIG. 2 shows an aspect of a wireless transceiver 210 for communicating information. The receive path of the wireless transceiver 210 may include an amplifier 212 for amplifying an input signal 214. The amplifier 212 may include a bias assembly 218 and LNA 216 constructed in accordance with the principles of the invention. A mixer 222 may combine the amplified input signal with a Radio Frequency (RF) LO signal 224. A filter 226 and adjustable amplifier 223 may filter and amplify the combined signal, and mix the generated signal with an Intermediate Frequency (IF) LO signal down to baseband for possibly further amplification and filtering. An analog-to-digital converter (ADC) 228 may convert the mixed signal to a digital signal for further processing.

[0017] In the transmit path, a digital-to-analog converter 227 may convert a digital signal to an analog signal for transmission by a transmitter 225.

[0018] FIG. 3 shows an aspect of an amplifier 230 for generating an RF output. The amplifier 230 is configured to compensate for gain variations that may be caused by process and environmental variations. The amplifier 230 is suitable for assembly as an integrated circuit fabricated with CMOS techniques. The amplifier 230 includes a bias assembly 232 for supplying a bias current, Iout, to an LNA 234. A bias current buffer 236 may be connected between the bias assembly 232 and LNA 234 to level shift and amplify the bias current.

[0019] In one aspect, the LNA 234 may include an input stage 238 and a shunt feedback stage 240 to amplify an RF_insignal 242. To compensate for gain changes related to resistive component variations in the shunt feedback stage 240, the bias assembly 232 may be configured to have a resistive variation that is about inversely proportional to the shunt feedback stage resistive variation. The bias assembly 232 may, for example, include a bias circuit 244 to generate the bias current as a function of a bias resistor 246, where environmental variations of the bias resistor resistance may partially or completely cancel resistance variations of the shunt feedback stage 240.

[0020] In another aspect, the LNA 234 may include an input stage 238 to amplify the RF_insignal 242, but not include a shunt feedback stage 240. A bias assembly 232 may include a bias circuit 244 to generate the bias current as a function of a bias resistor 246. The bias resistor 246 may be either an on-chip resistor or an external resistor. If an on-chip resistor is used, the bias assembly 232 may also include a calibration circuit 248 to partially or completely cancel resistance variations of the bias resistor 246.

[0021] FIG. 4 shows an aspect of a bias assembly 10 for supplying a bias current, Iout, to an LNA (not shown). The bias assembly 10 is suitable for assembly as an integrated circuit fabricated with CMOS techniques. The bias assembly 10 includes a bias circuit 12 and a calibration circuit 14. The bias circuit 12 generates the bias current as a function of a bias impedance 16. The bias impedance 16 may be controlled in response to a control signal 18 from the calibration circuit 14 to maintain a relatively constant value over variations in operating conditions such as process variations and environmental conditions variations.

[0022] Referring to FIG. 5, several configurations of the bias impedance are shown. A hybrid configuration 50 includes a series string of resistors 52 and control transistors 54 that are connected in shunt with one or more of the resistors 52. A series configuration 60 includes a series string of resistors 62 with control transistors 64 that are connected in shunt with each resistor 62. A shunt configuration 70 includes groupings of a resistor 72 connected in series with a control transistor 74 and the series combinations of resistor-transistor connected in shunt. The resistors in each of the configurations may be made from any suitable material including N+ poly and P+ poly.

[0023] Referring to FIG. 4, a bias voltage that may include temperature and process compensation is applied across the bias impedance 16 to generate the bias current. The bias current is supplied to a current mirror 20 that may reflect the bias current to a buffer 22. The buffer 22 supplies the bias current to an LNA (not shown) and may be configured as either a P Metal Oxide Semiconductor (PMOS) or an NMOS current mirroring gain buffer. The device characteristics of the buffer 22 may be varied in relation to the current mirror 20 to change the amplitude of the bias current supplied by the buffer 22. For example, the size of the buffer 22 may be varied relative to the current mirror to cause a corresponding change in the current supplied.

[0024] The calibration circuit 14 may determine the effect of process and environmental variations on a calibration impedance 24 such as a poly resistor. The calibration impedance 24 preferably is constructed from similar material, has a similar configuration, and is located in close proximity to the bias impedance 16 so that changes in the calibration impedance 24 may track changes in the bias impedance 16. A reference current, Iref, 26 may be applied to the calibration impedance 24 to generate a calibration voltage that is compared to a reference voltage, Vref, 28. The reference current 26 may be generated from a fixed voltage such as the reference voltage 28 and a fixed resistor that maintains a predictable value over process and environmental variations. A comparator 30 monitors changes in the calibration impedance 24 relative to the voltage reference 28. A latch 32 may latch the output of the comparator 30 synchronous to a clock. A calibration control circuit 34 may delay the latch output to reduce the impact of noise generated at the clock edges. The calibration control circuit 34 may include control logic and a up/down counter 38. A calibration signal, CAL, enables the calibration control circuit 34. A clock signal, Clk2, provides a timing reference for the counter 38. A decoder 40 interprets the signal from the calibration control circuit 34 and in response may control the resistance of the calibration impedance 24 by enabling or disabling control transistors.

[0025] FIG. 6 shows an aspect of a bias circuit 80 for generating an LNA bias current. The bias circuit 80 may include a PMOS current mirror pair, Q3 and Q4, and a pair of NMOS transistors, Q1 and Q2, 82 and 84 for generating a controlled current, Is, through a resistor, Rs, 86. A size ratio, K, of Q1 and Q2 is selected to provide a desired current amplitude of Is. The following equations show the relation between the transconductance of Q1 and Rs, if the currents flowing through Q1 and Q2 are equal, $\sqrt{\frac{2I_s}{\mu C\frac{W}{L}}}+V_{\mathrm{TH1}}=\sqrt{\frac{2I_s}{\mu C\left(\frac{W}{L}\right)·K}}+V_{\mathrm{TH2}}+I_s·R_s$

[0026] Canceling V_TH1and V_TH2and rearranging terms; $\begin{array}{cc}{I}_s=\frac{2}{\mu C\left(\frac{W}{L}\right)}·\frac{1}{R_s^2}{\left(1-\frac{1}{\sqrt{K}}\right)}^2& \mathrm{Equation}1\end{array}$

[0027] The pair of PMOS transistors, Q3 and Q4, 88 and 90 may be selected to have the same size so that the currents flowing through drains of Q1 and Q2 are substantially equal. With equal currents in Q1 and Q2, the relationship described by Equation 1 is maintained. A buffer 92 is preferably the same type of transistor as Q3 and Q4, 88 and 90, and may be sized in relation to Q3 to vary the amplitude of current, I_out1, flowing from the buffer 92. For example, if the buffer 92 is selected to be three times larger than Q3, then I_out1will be three times larger than Is. A current mirror 94 including transistors Q6 and Q7 may be connected to the buffer 92 to set a bias current, I_out2, of an LNA 95. The ratio of the sizes of Q6 and Q7 may be varied to change the amplitude of I_out2with respect to I_out1.

[0028] If the size ratio of Q5 and Q3 is M and the ratio of Q7 and Q6 is N, then the bias current I_outflowing into Qr. Will be: $I_{\mathrm{out2}}={\mathrm{MNI}}_s=\frac{2\mathrm{MN}}{\mu C\left(\frac{W}{L}\right)}·\frac{1}{R_s^2}{\left(1-\frac{1}{\sqrt{K}}\right)}^2$

[0029] Solving for g_{m, Q7} $g_{m,\mathrm{Q7}}=\sqrt{2\mu C\left(\frac{W}{L}\right)·I_{\mathrm{out2}}}=\frac{2\sqrt{\mathrm{MN}}}{R_s}\left(1-\frac{1}{\sqrt{K}}\right)$

[0030] It can be seen that the transconductance of the LNA input stage is predominantly dependent on the resistor value Rs. Rs may be implemented as an external resistor or an on chip resistor. If Rs is implemented as an on chip resistor, then the resistance value of Rs will vary with process and environmental variations. The variation of the LNA gain to process and environmental changes may be reduced by using any of several techniques including 1) a calibration scheme to reduce the variation of Rs with process and environmental changes, and 2) adding a shunt feedback stage to cancel out the resistor variation.

[0031] In one aspect, the LNA 95 may include an input stage 96 to amplify an RF input signal, RF_in. Recall that the gain of the LNA is: $A_v=g_m·Q^2·R_p\propto \frac{Q^2{R}_p}{R_s}$

[0032] Since Rs will be calibrated, the Q²Rp term becomes the dominant contributor of gain variation, varying by about 10%-20%.

[0033] In another aspect, the LNA 95 may also include a shunt feedback stage 97 connected to the input stage 96 to further amplify RF_in. The gain of this LNA can be expressed as: $A_v=g_m·R_f\propto \frac{R_f}{R_s},$

[0034] where Rf is the shunt feed back resistor. If Rf is chosen to be the same type of resistor as Rs, a good match can be achieved, leading to improved gain accuracy.

[0035] FIG. 7 shows an operation for amplifying an RF signal. Starting at block 100, a bias voltage may be generated by a two transistor circuit. The bias voltage may be equal to the difference between the Vgs voltages of the two transistors. At block 102, the bias voltage is applied across a bias impedance to generate a bias current. The bias impedance may be controllable and may include one or more poly resistors in combination with switches. The magnitude of the bias current may be a function of the poly resistors and the physical characteristics of the two transistors including size ratio, width, length, and capacitance. At block 104, the bias current is mirrored to generate an output current that is a function of the poly resistance.

[0036] In one aspect, at block 106, a reference current is generated. At block 108, the reference current is supplied to a controlled calibration impedance that may include several poly resistors in combination with switches. At block 110, the voltage developed across the controlled calibration impedance may be compared to a reference voltage. At block 112, the impedance of the controlled calibration impedance may be controlled as a function of the comparison to reduce the difference between the reference voltage and the voltage developed across the controlled calibration impedance. Different ones of the control switches are turned on or off to effect the desired control. At block 114, a control signal may be generated to indicate the change in the controlled calibration impedance that cancels the difference between the reference voltage and the voltage developed across the controlled calibration impedance. The control signal may indicate the state of each of the control switches. At block 116, the impedance of the controlled bias impedance may be controlled in response to the control signal so that changes in the poly resistance are compensated for by effecting the same changes to the controlled bias impedance that are affected for the controlled calibration impedance. Variations in the resistance of the poly resistors caused by process, environmental conditions, and operating conditions may be compensated for by controlling for the change in resistance of the controlled calibration impedance poly resistors and mirroring that control to the controlled bias impedance poly resistors. By compensating for changes in the resistance of the poly resistors, the transconductance of the LNA may be held constant over process variations and environmental conditions resulting in a relatively constant LNA gain, with the dominant variation resulting from the effective impedance from the inductor tank.

[0037] In another aspect, continuing from block 104 to block 118 an LNA is biased with the output current. The LNA may include an input stage to receive an RF input signal. At block 120, a portion of the amplified RF input signal may be communicated to the input stage using a shunt resistor to provide feedback. Variations in the shunt resistor may be compensated for by variations in the bias impedance to cause the gain of the amplifier to be substantially independent of changes in conditions that affect the values of the resistors.

[0038] A number of embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other embodiments are within the scope of the following claims.